src/mesa/drivers/dri/r300/radeon_span.c

   1 /**************************************************************************
   2
   3 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 The Weather Channel (TM) funded Tungsten Graphics to develop the
   8 initial release of the Radeon 8500 driver under the XFree86 license.
   9 This notice must be preserved.
  10
  11 All Rights Reserved.
  12
  13 Permission is hereby granted, free of charge, to any person obtaining
  14 a copy of this software and associated documentation files (the
  15 "Software"), to deal in the Software without restriction, including
  16 without limitation the rights to use, copy, modify, merge, publish,
  17 distribute, sublicense, and/or sell copies of the Software, and to
  18 permit persons to whom the Software is furnished to do so, subject to
  19 the following conditions:
  20
  21 The above copyright notice and this permission notice (including the
  22 next paragraph) shall be included in all copies or substantial
  23 portions of the Software.
  24
  25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  32
  33 **************************************************************************/
  34
  35 /*
  36  * Authors:
  37  *   Kevin E. Martin <martin@valinux.com>
  38  *   Gareth Hughes <gareth@valinux.com>
  39  *   Keith Whitwell <keith@tungstengraphics.com>
  40  *
  41  */
  42
  43 #include "glheader.h"
  44 #include "swrast/swrast.h"
  45
  46 #include "r300_state.h"
  47 #include "radeon_ioctl.h"
  48 #include "r300_ioctl.h"
  49 #include "radeon_span.h"
  50
  51 #include "drirenderbuffer.h"
  52
  53 #define DBG 0
  54
  55 /*
  56  * Note that all information needed to access pixels in a renderbuffer
  57  * should be obtained through the gl_renderbuffer parameter, not per-context
  58  * information.
  59  */
  60 #define LOCAL_VARS                                              \
  61    driRenderbuffer *drb = (driRenderbuffer *) rb;               \
  62    const __DRIdrawablePrivate *dPriv = drb->dPriv;              \
  63    const GLuint bottom = dPriv->h - 1;                          \
  64    GLubyte *buf = (GLubyte *) drb->flippedData                  \
  65       + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp;   \
  66    GLuint p;                                                    \
  67    (void) p;
  68
  69 #define LOCAL_DEPTH_VARS                                \
  70    driRenderbuffer *drb = (driRenderbuffer *) rb;       \
  71    const __DRIdrawablePrivate *dPriv = drb->dPriv;      \
  72    const GLuint bottom = dPriv->h - 1;                  \
  73    GLuint xo = dPriv->x;                                \
  74    GLuint yo = dPriv->y;                                \
  75    GLubyte *buf = (GLubyte *) drb->Base.Data;
  76
  77 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
  78
  79 #define Y_FLIP(Y) (bottom - (Y))
  80
  81 #define HW_LOCK()
  82
  83 #define HW_UNLOCK()
  84
  85 /* ================================================================
  86  * Color buffer
  87  */
  88
  89 /* 16 bit, RGB565 color spanline and pixel functions
  90  */
  91 #define SPANTMP_PIXEL_FMT GL_RGB
  92 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
  93
  94 #define TAG(x)    radeon##x##_RGB565
  95 #define TAG2(x,y) radeon##x##_RGB565##y
  96 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
  97 #include "spantmp2.h"
  98
  99 /* 32 bit, ARGB8888 color spanline and pixel functions
 100  */
 101 #define SPANTMP_PIXEL_FMT GL_BGRA
 102 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 103
 104 #define TAG(x)    radeon##x##_ARGB8888
 105 #define TAG2(x,y) radeon##x##_ARGB8888##y
 106 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
 107 #include "spantmp2.h"
 108
 109 /* ================================================================
 110  * Depth buffer
 111  */
 112
 113 /* The Radeon family has depth tiling on all the time, so we have to convert
 114  * the x,y coordinates into the memory bus address (mba) in the same
 115  * manner as the engine.  In each case, the linear block address (ba)
 116  * is calculated, and then wired with x and y to produce the final
 117  * memory address.
 118  * The chip will do address translation on its own if the surface registers
 119  * are set up correctly. It is not quite enough to get it working with hyperz
 120  * too...
 121  */
 122
 123 static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y)
 124 {
 125         GLuint pitch = drb->pitch;
 126         if (1 /*|| drb->depthHasSurface */ ) {
 127                 return 4 * (x + y * pitch);
 128         } else {
 129                 GLuint ba, address = 0; /* a[0..1] = 0           */
 130
 131                 ba = (y / 8) * (pitch / 8) + (x / 8);
 132
 133                 address |= (x & 0x7) << 2;      /* a[2..4] = x[0..2]     */
 134                 address |= (y & 0x3) << 5;      /* a[5..6] = y[0..1]     */
 135                 address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;        /* a[7]    = x[4] ^ y[2] */
 136                 address |= (ba & 0x3) << 8;     /* a[8..9] = ba[0..1]    */
 137
 138                 address |= (y & 0x8) << 7;      /* a[10]   = y[3]        */
 139                 address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7;        /* a[11]   = x[3] ^ y[4] */
 140                 address |= (ba & ~0x3) << 10;   /* a[12..] = ba[2..]     */
 141
 142                 return address;
 143         }
 144 }
 145
 146 static INLINE GLuint
 147 radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
 148 {
 149         GLuint pitch = drb->pitch;
 150         if (1 /*|| drb->depthHasSurface */ ) {
 151                 return 2 * (x + y * pitch);
 152         } else {
 153                 GLuint ba, address = 0; /* a[0]    = 0           */
 154
 155                 ba = (y / 16) * (pitch / 32) + (x / 32);
 156
 157                 address |= (x & 0x7) << 1;      /* a[1..3] = x[0..2]     */
 158                 address |= (y & 0x7) << 4;      /* a[4..6] = y[0..2]     */
 159                 address |= (x & 0x8) << 4;      /* a[7]    = x[3]        */
 160                 address |= (ba & 0x3) << 8;     /* a[8..9] = ba[0..1]    */
 161                 address |= (y & 0x8) << 7;      /* a[10]   = y[3]        */
 162                 address |= ((x & 0x10) ^ (y & 0x10)) << 7;      /* a[11]   = x[4] ^ y[4] */
 163                 address |= (ba & ~0x3) << 10;   /* a[12..] = ba[2..]     */
 164
 165                 return address;
 166         }
 167 }
 168
 169 /* 16-bit depth buffer functions
 170  */
 171 #define WRITE_DEPTH( _x, _y, d )                                        \
 172    *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
 173
 174 #define READ_DEPTH( d, _x, _y )                                         \
 175    d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
 176
 177 #define TAG(x) radeon##x##_z16
 178 #include "depthtmp.h"
 179
 180 /* 24 bit depth, 8 bit stencil depthbuffer functions
 181  *
 182  * Careful: It looks like the R300 uses ZZZS byte order while the R200
 183  * uses SZZZ for 24 bit depth, 8 bit stencil mode.
 184  */
 185 #define WRITE_DEPTH( _x, _y, d )                                        \
 186 do {                                                                    \
 187    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 188    GLuint tmp = *(GLuint *)(buf + offset);                              \
 189    tmp &= 0x000000ff;                                                   \
 190    tmp |= ((d << 8) & 0xffffff00);                                      \
 191    *(GLuint *)(buf + offset) = tmp;                                     \
 192 } while (0)
 193
 194 #define READ_DEPTH( d, _x, _y )                                         \
 195   do { \
 196     d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                \
 197                                          _y + yo )) & 0xffffff00) >> 8; \
 198   }while(0)
 199
 200 #define TAG(x) radeon##x##_z24_s8
 201 #include "depthtmp.h"
 202
 203 /* ================================================================
 204  * Stencil buffer
 205  */
 206
 207 /* 24 bit depth, 8 bit stencil depthbuffer functions
 208  */
 209 #define WRITE_STENCIL( _x, _y, d )                                      \
 210 do {                                                                    \
 211    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 212    GLuint tmp = *(GLuint *)(buf + offset);                              \
 213    tmp &= 0xffffff00;                                                   \
 214    tmp |= (d) & 0xff;                                                   \
 215    *(GLuint *)(buf + offset) = tmp;                                     \
 216 } while (0)
 217
 218 #define READ_STENCIL( d, _x, _y )                                       \
 219 do {                                                                    \
 220    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 221    GLuint tmp = *(GLuint *)(buf + offset);                              \
 222    d = tmp & 0x000000ff;                                                \
 223 } while (0)
 224
 225 #define TAG(x) radeon##x##_z24_s8
 226 #include "stenciltmp.h"
 227
 228 /* Move locking out to get reasonable span performance (10x better
 229  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 230  * culprit.
 231  */
 232
 233 static void radeonSpanRenderStart(GLcontext * ctx)
 234 {
 235         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 236
 237         static int first = 1;
 238         r300ContextPtr r300 = (r300ContextPtr) rmesa;
 239
 240         if (first) {
 241                 r300->span_dlocking =
 242                     getenv("R300_SPAN_DISABLE_LOCKING") ? 1 : 0;
 243                 if (r300->span_dlocking == 0) {
 244                         fprintf(stderr,
 245                                 "Try R300_SPAN_DISABLE_LOCKING env var if this hangs.\n");
 246                         fflush(stderr);
 247                         sleep(1);
 248                 }
 249                 first = 0;
 250         }
 251
 252         if (r300->span_dlocking) {
 253                 r300Flush(ctx);
 254                 LOCK_HARDWARE(rmesa);
 255                 radeonWaitForIdleLocked(rmesa);
 256                 UNLOCK_HARDWARE(rmesa);
 257
 258                 return;
 259         }
 260         //   R300_FIREVERTICES( rmesa );
 261         // old code has flush
 262         r300Flush(ctx);
 263         LOCK_HARDWARE(rmesa);
 264         radeonWaitForIdleLocked(rmesa);
 265 }
 266
 267 static void radeonSpanRenderFinish(GLcontext * ctx)
 268 {
 269         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 270         r300ContextPtr r300 = (r300ContextPtr) rmesa;
 271         _swrast_flush(ctx);
 272         if (r300->span_dlocking == 0)
 273                 UNLOCK_HARDWARE(rmesa);
 274 }
 275
 276 void radeonInitSpanFuncs(GLcontext * ctx)
 277 {
 278         struct swrast_device_driver *swdd =
 279             _swrast_GetDeviceDriverReference(ctx);
 280         swdd->SpanRenderStart = radeonSpanRenderStart;
 281         swdd->SpanRenderFinish = radeonSpanRenderFinish;
 282 }
 283
 284 /**
 285  * Plug in the Get/Put routines for the given driRenderbuffer.
 286  */
 287 void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
 288 {
 289         if (drb->Base.InternalFormat == GL_RGBA) {
 290                 if (vis->redBits == 5 && vis->greenBits == 6
 291                     && vis->blueBits == 5) {
 292                         radeonInitPointers_RGB565(&drb->Base);
 293                 } else {
 294                         radeonInitPointers_ARGB8888(&drb->Base);
 295                 }
 296         } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
 297                 radeonInitDepthPointers_z16(&drb->Base);
 298         } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
 299                 radeonInitDepthPointers_z24_s8(&drb->Base);
 300         } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 301                 radeonInitStencilPointers_z24_s8(&drb->Base);
 302         }
 303 }