src/mesa/drivers/dri/r300/radeon_span.c

   1 /**************************************************************************
   2
   3 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 The Weather Channel (TM) funded Tungsten Graphics to develop the
   8 initial release of the Radeon 8500 driver under the XFree86 license.
   9 This notice must be preserved.
  10
  11 All Rights Reserved.
  12
  13 Permission is hereby granted, free of charge, to any person obtaining
  14 a copy of this software and associated documentation files (the
  15 "Software"), to deal in the Software without restriction, including
  16 without limitation the rights to use, copy, modify, merge, publish,
  17 distribute, sublicense, and/or sell copies of the Software, and to
  18 permit persons to whom the Software is furnished to do so, subject to
  19 the following conditions:
  20
  21 The above copyright notice and this permission notice (including the
  22 next paragraph) shall be included in all copies or substantial
  23 portions of the Software.
  24
  25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  32
  33 **************************************************************************/
  34
  35 /*
  36  * Authors:
  37  *   Kevin E. Martin <martin@valinux.com>
  38  *   Gareth Hughes <gareth@valinux.com>
  39  *   Keith Whitwell <keith@tungstengraphics.com>
  40  *
  41  */
  42
  43 #include "glheader.h"
  44 #include "swrast/swrast.h"
  45
  46 #include "r300_state.h"
  47 #include "radeon_ioctl.h"
  48 #include "r300_ioctl.h"
  49 #include "radeon_span.h"
  50
  51 #include "drirenderbuffer.h"
  52
  53 #define DBG 0
  54
  55 /*
  56  * Note that all information needed to access pixels in a renderbuffer
  57  * should be obtained through the gl_renderbuffer parameter, not per-context
  58  * information.
  59  */
  60 #define LOCAL_VARS                                              \
  61    driRenderbuffer *drb = (driRenderbuffer *) rb;               \
  62    const __DRIdrawablePrivate *dPriv = drb->dPriv;              \
  63    const GLuint bottom = dPriv->h - 1;                          \
  64    GLubyte *buf = (GLubyte *) drb->flippedData                  \
  65       + (dPriv->y * drb->flippedPitch + dPriv->x) * drb->cpp;   \
  66    GLuint p;                                                    \
  67    (void) p;
  68
  69 #define LOCAL_DEPTH_VARS                                \
  70    driRenderbuffer *drb = (driRenderbuffer *) rb;       \
  71    const __DRIdrawablePrivate *dPriv = drb->dPriv;      \
  72    const GLuint bottom = dPriv->h - 1;                  \
  73    GLuint xo = dPriv->x;                                \
  74    GLuint yo = dPriv->y;                                \
  75    GLubyte *buf = (GLubyte *) drb->Base.Data;
  76
  77 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
  78
  79 #define Y_FLIP(Y) (bottom - (Y))
  80
  81 #define HW_LOCK()
  82
  83 #define HW_UNLOCK()
  84
  85 /* ================================================================
  86  * Color buffer
  87  */
  88
  89 /* 16 bit, RGB565 color spanline and pixel functions
  90  */
  91 #define SPANTMP_PIXEL_FMT GL_RGB
  92 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
  93
  94 #define TAG(x)    radeon##x##_RGB565
  95 #define TAG2(x,y) radeon##x##_RGB565##y
  96 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 2)
  97 #include "spantmp2.h"
  98
  99 /* 32 bit, ARGB8888 color spanline and pixel functions
 100  */
 101 #define SPANTMP_PIXEL_FMT GL_BGRA
 102 #define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
 103
 104 #define TAG(x)    radeon##x##_ARGB8888
 105 #define TAG2(x,y) radeon##x##_ARGB8888##y
 106 #define GET_PTR(X,Y) (buf + ((Y) * drb->flippedPitch + (X)) * 4)
 107 #include "spantmp2.h"
 108
 109 /* ================================================================
 110  * Depth buffer
 111  */
 112
 113 /* The Radeon family has depth tiling on all the time, so we have to convert
 114  * the x,y coordinates into the memory bus address (mba) in the same
 115  * manner as the engine.  In each case, the linear block address (ba)
 116  * is calculated, and then wired with x and y to produce the final
 117  * memory address.
 118  * The chip will do address translation on its own if the surface registers
 119  * are set up correctly. It is not quite enough to get it working with hyperz
 120  * too...
 121  */
 122
 123 static GLuint radeon_mba_z32(const driRenderbuffer * drb, GLint x, GLint y)
 124 {
 125         GLuint pitch = drb->pitch;
 126         if (drb->depthHasSurface) {
 127                 return 4 * (x + y * pitch);
 128         } else {
 129                 GLuint ba, address = 0; /* a[0..1] = 0           */
 130
 131 #ifdef COMPILE_R300
 132                 ba = (y / 8) * (pitch / 8) + (x / 8);
 133 #else
 134                 ba = (y / 16) * (pitch / 16) + (x / 16);
 135 #endif
 136
 137                 address |= (x & 0x7) << 2;      /* a[2..4] = x[0..2]     */
 138                 address |= (y & 0x3) << 5;      /* a[5..6] = y[0..1]     */
 139                 address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5;        /* a[7]    = x[4] ^ y[2] */
 140                 address |= (ba & 0x3) << 8;     /* a[8..9] = ba[0..1]    */
 141
 142                 address |= (y & 0x8) << 7;      /* a[10]   = y[3]        */
 143                 address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7;        /* a[11]   = x[3] ^ y[4] */
 144                 address |= (ba & ~0x3) << 10;   /* a[12..] = ba[2..]     */
 145
 146                 return address;
 147         }
 148 }
 149
 150 static INLINE GLuint
 151 radeon_mba_z16(const driRenderbuffer * drb, GLint x, GLint y)
 152 {
 153         GLuint pitch = drb->pitch;
 154         if (drb->depthHasSurface) {
 155                 return 2 * (x + y * pitch);
 156         } else {
 157                 GLuint ba, address = 0; /* a[0]    = 0           */
 158
 159                 ba = (y / 16) * (pitch / 32) + (x / 32);
 160
 161                 address |= (x & 0x7) << 1;      /* a[1..3] = x[0..2]     */
 162                 address |= (y & 0x7) << 4;      /* a[4..6] = y[0..2]     */
 163                 address |= (x & 0x8) << 4;      /* a[7]    = x[3]        */
 164                 address |= (ba & 0x3) << 8;     /* a[8..9] = ba[0..1]    */
 165                 address |= (y & 0x8) << 7;      /* a[10]   = y[3]        */
 166                 address |= ((x & 0x10) ^ (y & 0x10)) << 7;      /* a[11]   = x[4] ^ y[4] */
 167                 address |= (ba & ~0x3) << 10;   /* a[12..] = ba[2..]     */
 168
 169                 return address;
 170         }
 171 }
 172
 173 /* 16-bit depth buffer functions
 174  */
 175 #define WRITE_DEPTH( _x, _y, d )                                        \
 176    *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo )) = d;
 177
 178 #define READ_DEPTH( d, _x, _y )                                         \
 179    d = *(GLushort *)(buf + radeon_mba_z16( drb, _x + xo, _y + yo ));
 180
 181 #define TAG(x) radeon##x##_z16
 182 #include "depthtmp.h"
 183
 184 /* 24 bit depth, 8 bit stencil depthbuffer functions
 185  *
 186  * Careful: It looks like the R300 uses ZZZS byte order while the R200
 187  * uses SZZZ for 24 bit depth, 8 bit stencil mode.
 188  */
 189 #ifdef COMPILE_R300
 190 #define WRITE_DEPTH( _x, _y, d )                                        \
 191 do {                                                                    \
 192    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 193    GLuint tmp = *(GLuint *)(buf + offset);                              \
 194    tmp &= 0x000000ff;                                                   \
 195    tmp |= ((d << 8) & 0xffffff00);                                      \
 196    *(GLuint *)(buf + offset) = tmp;                                     \
 197 } while (0)
 198 #else
 199 #define WRITE_DEPTH( _x, _y, d )                                        \
 200 do {                                                                    \
 201    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 202    GLuint tmp = *(GLuint *)(buf + offset);                              \
 203    tmp &= 0xff000000;                                                   \
 204    tmp |= ((d) & 0x00ffffff);                                           \
 205    *(GLuint *)(buf + offset) = tmp;                                     \
 206 } while (0)
 207 #endif
 208
 209 #ifdef COMPILE_R300
 210 #define READ_DEPTH( d, _x, _y )                                         \
 211   do { \
 212     d = (*(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                \
 213                                          _y + yo )) & 0xffffff00) >> 8; \
 214   }while(0)
 215 #else
 216 #define READ_DEPTH( d, _x, _y )                                         \
 217    d = *(GLuint *)(buf + radeon_mba_z32( drb, _x + xo,                  \
 218                                          _y + yo )) & 0x00ffffff;
 219 #endif
 220
 221 #define TAG(x) radeon##x##_z24_s8
 222 #include "depthtmp.h"
 223
 224 /* ================================================================
 225  * Stencil buffer
 226  */
 227
 228 /* 24 bit depth, 8 bit stencil depthbuffer functions
 229  */
 230 #ifdef COMPILE_R300
 231 #define WRITE_STENCIL( _x, _y, d )                                      \
 232 do {                                                                    \
 233    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 234    GLuint tmp = *(GLuint *)(buf + offset);                              \
 235    tmp &= 0xffffff00;                                                   \
 236    tmp |= (d) & 0xff;                                                   \
 237    *(GLuint *)(buf + offset) = tmp;                                     \
 238 } while (0)
 239 #else
 240 #define WRITE_STENCIL( _x, _y, d )                                      \
 241 do {                                                                    \
 242    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 243    GLuint tmp = *(GLuint *)(buf + offset);                              \
 244    tmp &= 0x00ffffff;                                                   \
 245    tmp |= (((d) & 0xff) << 24);                                         \
 246    *(GLuint *)(buf + offset) = tmp;                                     \
 247 } while (0)
 248 #endif
 249
 250 #ifdef COMPILE_R300
 251 #define READ_STENCIL( d, _x, _y )                                       \
 252 do {                                                                    \
 253    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 254    GLuint tmp = *(GLuint *)(buf + offset);                              \
 255    d = tmp & 0x000000ff;                                                \
 256 } while (0)
 257 #else
 258 #define READ_STENCIL( d, _x, _y )                                       \
 259 do {                                                                    \
 260    GLuint offset = radeon_mba_z32( drb, _x + xo, _y + yo );             \
 261    GLuint tmp = *(GLuint *)(buf + offset);                              \
 262    d = (tmp & 0xff000000) >> 24;                                        \
 263 } while (0)
 264 #endif
 265
 266 #define TAG(x) radeon##x##_z24_s8
 267 #include "stenciltmp.h"
 268
 269 /* Move locking out to get reasonable span performance (10x better
 270  * than doing this in HW_LOCK above).  WaitForIdle() is the main
 271  * culprit.
 272  */
 273
 274 static void radeonSpanRenderStart(GLcontext * ctx)
 275 {
 276         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 277 #ifdef COMPILE_R300
 278         r300ContextPtr r300 = (r300ContextPtr) rmesa;
 279         R300_FIREVERTICES(r300);
 280 #else
 281         RADEON_FIREVERTICES(rmesa);
 282 #endif
 283         LOCK_HARDWARE(rmesa);
 284         radeonWaitForIdleLocked(rmesa);
 285 }
 286
 287 static void radeonSpanRenderFinish(GLcontext * ctx)
 288 {
 289         radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 290         _swrast_flush(ctx);
 291         UNLOCK_HARDWARE(rmesa);
 292 }
 293
 294 void radeonInitSpanFuncs(GLcontext * ctx)
 295 {
 296         struct swrast_device_driver *swdd =
 297             _swrast_GetDeviceDriverReference(ctx);
 298         swdd->SpanRenderStart = radeonSpanRenderStart;
 299         swdd->SpanRenderFinish = radeonSpanRenderFinish;
 300 }
 301
 302 /**
 303  * Plug in the Get/Put routines for the given driRenderbuffer.
 304  */
 305 void radeonSetSpanFunctions(driRenderbuffer * drb, const GLvisual * vis)
 306 {
 307         if (drb->Base.InternalFormat == GL_RGBA) {
 308                 if (vis->redBits == 5 && vis->greenBits == 6
 309                     && vis->blueBits == 5) {
 310                         radeonInitPointers_RGB565(&drb->Base);
 311                 } else {
 312                         radeonInitPointers_ARGB8888(&drb->Base);
 313                 }
 314         } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
 315                 radeonInitDepthPointers_z16(&drb->Base);
 316         } else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
 317                 radeonInitDepthPointers_z24_s8(&drb->Base);
 318         } else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
 319                 radeonInitStencilPointers_z24_s8(&drb->Base);
 320         }
 321 }