2 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "r600_context.h"
31 #include "evergreen_off.h"
32 #include "evergreen_diff.h"
34 #include "evergreen_blit.h"
35 #include "evergreen_blit_shaders.h"
36 #include "r600_cmdbuf.h"
38 /* common formats supported as both textures and render targets */
39 unsigned evergreen_check_blit(gl_format mesa_format
)
41 switch (mesa_format
) {
42 case MESA_FORMAT_RGBA8888
:
43 case MESA_FORMAT_SIGNED_RGBA8888
:
44 case MESA_FORMAT_RGBA8888_REV
:
45 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
46 case MESA_FORMAT_ARGB8888
:
47 case MESA_FORMAT_XRGB8888
:
48 case MESA_FORMAT_ARGB8888_REV
:
49 case MESA_FORMAT_XRGB8888_REV
:
50 case MESA_FORMAT_RGB565
:
51 case MESA_FORMAT_RGB565_REV
:
52 case MESA_FORMAT_ARGB4444
:
53 case MESA_FORMAT_ARGB4444_REV
:
54 case MESA_FORMAT_ARGB1555
:
55 case MESA_FORMAT_ARGB1555_REV
:
56 case MESA_FORMAT_AL88
:
57 case MESA_FORMAT_AL88_REV
:
58 case MESA_FORMAT_RGB332
:
62 case MESA_FORMAT_RGBA_FLOAT32
:
63 case MESA_FORMAT_RGBA_FLOAT16
:
64 case MESA_FORMAT_ALPHA_FLOAT32
:
65 case MESA_FORMAT_ALPHA_FLOAT16
:
66 case MESA_FORMAT_LUMINANCE_FLOAT32
:
67 case MESA_FORMAT_LUMINANCE_FLOAT16
:
68 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
69 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
70 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
71 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
72 case MESA_FORMAT_X8_Z24
:
73 case MESA_FORMAT_S8_Z24
:
74 case MESA_FORMAT_Z24_S8
:
77 case MESA_FORMAT_SARGB8
:
78 case MESA_FORMAT_SLA8
:
86 /* not sure blit to depth works or not yet */
87 if (_mesa_get_format_bits(mesa_format
, GL_DEPTH_BITS
) > 0)
94 eg_set_render_target(context_t
*context
, struct radeon_bo
*bo
, gl_format mesa_format
,
95 int nPitchInPixel
, int w
, int h
, intptr_t dst_offset
)
97 uint32_t cb_color0_base
, cb_color0_info
= 0;
98 uint32_t cb_color0_pitch
= 0, cb_color0_slice
= 0, cb_color0_attrib
= 0;
100 uint32_t endian
, comp_swap
, format
, source_format
, number_type
;
101 BATCH_LOCALS(&context
->radeon
);
103 cb_color0_base
= dst_offset
/ 256;
104 endian
= ENDIAN_NONE
;
107 SETfield(cb_color0_pitch
, (nPitchInPixel
/ 8) - 1,
108 EG_CB_COLOR0_PITCH__TILE_MAX_shift
,
109 EG_CB_COLOR0_PITCH__TILE_MAX_mask
);
112 SETfield(cb_color0_slice
,
113 ((nPitchInPixel
* h
) / 64) - 1,
114 EG_CB_COLOR0_SLICE__TILE_MAX_shift
,
115 EG_CB_COLOR0_SLICE__TILE_MAX_mask
);
117 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
118 SETbit(cb_color0_attrib
,
119 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit
);
121 SETfield(cb_color0_info
,
122 ARRAY_LINEAR_GENERAL
,
123 EG_CB_COLOR0_INFO__ARRAY_MODE_shift
,
124 EG_CB_COLOR0_INFO__ARRAY_MODE_mask
);
126 SETbit(cb_color0_info
, EG_CB_COLOR0_INFO__BLEND_BYPASS_bit
);
128 switch(mesa_format
) {
129 case MESA_FORMAT_RGBA8888
:
130 #ifdef MESA_BIG_ENDIAN
131 endian
= ENDIAN_8IN32
;
133 format
= COLOR_8_8_8_8
;
134 comp_swap
= SWAP_STD_REV
;
135 number_type
= NUMBER_UNORM
;
138 case MESA_FORMAT_SIGNED_RGBA8888
:
139 #ifdef MESA_BIG_ENDIAN
140 endian
= ENDIAN_8IN32
;
142 format
= COLOR_8_8_8_8
;
143 comp_swap
= SWAP_STD_REV
;
144 number_type
= NUMBER_SNORM
;
147 case MESA_FORMAT_RGBA8888_REV
:
148 #ifdef MESA_BIG_ENDIAN
149 endian
= ENDIAN_8IN32
;
151 format
= COLOR_8_8_8_8
;
152 comp_swap
= SWAP_STD
;
153 number_type
= NUMBER_UNORM
;
156 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
157 #ifdef MESA_BIG_ENDIAN
158 endian
= ENDIAN_8IN32
;
160 format
= COLOR_8_8_8_8
;
161 comp_swap
= SWAP_STD
;
162 number_type
= NUMBER_SNORM
;
165 case MESA_FORMAT_ARGB8888
:
166 case MESA_FORMAT_XRGB8888
:
167 #ifdef MESA_BIG_ENDIAN
168 endian
= ENDIAN_8IN32
;
170 format
= COLOR_8_8_8_8
;
171 comp_swap
= SWAP_ALT
;
172 number_type
= NUMBER_UNORM
;
175 case MESA_FORMAT_ARGB8888_REV
:
176 case MESA_FORMAT_XRGB8888_REV
:
177 #ifdef MESA_BIG_ENDIAN
178 endian
= ENDIAN_8IN32
;
180 format
= COLOR_8_8_8_8
;
181 comp_swap
= SWAP_ALT_REV
;
182 number_type
= NUMBER_UNORM
;
185 case MESA_FORMAT_RGB565
:
186 #ifdef MESA_BIG_ENDIAN
187 endian
= ENDIAN_8IN16
;
189 format
= COLOR_5_6_5
;
190 comp_swap
= SWAP_STD_REV
;
191 number_type
= NUMBER_UNORM
;
194 case MESA_FORMAT_RGB565_REV
:
195 #ifdef MESA_BIG_ENDIAN
196 endian
= ENDIAN_8IN16
;
198 format
= COLOR_5_6_5
;
199 comp_swap
= SWAP_STD
;
200 number_type
= NUMBER_UNORM
;
203 case MESA_FORMAT_ARGB4444
:
204 #ifdef MESA_BIG_ENDIAN
205 endian
= ENDIAN_8IN16
;
207 format
= COLOR_4_4_4_4
;
208 comp_swap
= SWAP_ALT
;
209 number_type
= NUMBER_UNORM
;
212 case MESA_FORMAT_ARGB4444_REV
:
213 #ifdef MESA_BIG_ENDIAN
214 endian
= ENDIAN_8IN16
;
216 format
= COLOR_4_4_4_4
;
217 comp_swap
= SWAP_ALT_REV
;
218 number_type
= NUMBER_UNORM
;
221 case MESA_FORMAT_ARGB1555
:
222 #ifdef MESA_BIG_ENDIAN
223 endian
= ENDIAN_8IN16
;
225 format
= COLOR_1_5_5_5
;
226 comp_swap
= SWAP_ALT
;
227 number_type
= NUMBER_UNORM
;
230 case MESA_FORMAT_ARGB1555_REV
:
231 #ifdef MESA_BIG_ENDIAN
232 endian
= ENDIAN_8IN16
;
234 format
= COLOR_1_5_5_5
;
235 comp_swap
= SWAP_ALT_REV
;
236 number_type
= NUMBER_UNORM
;
239 case MESA_FORMAT_AL88
:
240 #ifdef MESA_BIG_ENDIAN
241 endian
= ENDIAN_8IN16
;
244 comp_swap
= SWAP_STD
;
245 number_type
= NUMBER_UNORM
;
248 case MESA_FORMAT_AL88_REV
:
249 #ifdef MESA_BIG_ENDIAN
250 endian
= ENDIAN_8IN16
;
253 comp_swap
= SWAP_STD_REV
;
254 number_type
= NUMBER_UNORM
;
257 case MESA_FORMAT_RGB332
:
258 format
= COLOR_3_3_2
;
259 comp_swap
= SWAP_STD_REV
;
260 number_type
= NUMBER_UNORM
;
265 comp_swap
= SWAP_ALT_REV
;
266 number_type
= NUMBER_UNORM
;
271 comp_swap
= SWAP_STD
;
272 number_type
= NUMBER_UNORM
;
277 comp_swap
= SWAP_ALT
;
278 number_type
= NUMBER_UNORM
;
281 case MESA_FORMAT_RGBA_FLOAT32
:
282 #ifdef MESA_BIG_ENDIAN
283 endian
= ENDIAN_8IN32
;
285 format
= COLOR_32_32_32_32_FLOAT
;
286 comp_swap
= SWAP_STD
;
287 number_type
= NUMBER_FLOAT
;
290 case MESA_FORMAT_RGBA_FLOAT16
:
291 #ifdef MESA_BIG_ENDIAN
292 endian
= ENDIAN_8IN16
;
294 format
= COLOR_16_16_16_16_FLOAT
;
295 comp_swap
= SWAP_STD
;
296 number_type
= NUMBER_FLOAT
;
299 case MESA_FORMAT_ALPHA_FLOAT32
:
300 #ifdef MESA_BIG_ENDIAN
301 endian
= ENDIAN_8IN32
;
303 format
= COLOR_32_FLOAT
;
304 comp_swap
= SWAP_ALT_REV
;
305 number_type
= NUMBER_FLOAT
;
308 case MESA_FORMAT_ALPHA_FLOAT16
:
309 #ifdef MESA_BIG_ENDIAN
310 endian
= ENDIAN_8IN16
;
312 format
= COLOR_16_FLOAT
;
313 comp_swap
= SWAP_ALT_REV
;
314 number_type
= NUMBER_FLOAT
;
317 case MESA_FORMAT_LUMINANCE_FLOAT32
:
318 #ifdef MESA_BIG_ENDIAN
319 endian
= ENDIAN_8IN32
;
321 format
= COLOR_32_FLOAT
;
322 comp_swap
= SWAP_ALT
;
323 number_type
= NUMBER_FLOAT
;
326 case MESA_FORMAT_LUMINANCE_FLOAT16
:
327 #ifdef MESA_BIG_ENDIAN
328 endian
= ENDIAN_8IN16
;
330 format
= COLOR_16_FLOAT
;
331 comp_swap
= SWAP_ALT
;
332 number_type
= NUMBER_FLOAT
;
335 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
336 #ifdef MESA_BIG_ENDIAN
337 endian
= ENDIAN_8IN32
;
339 format
= COLOR_32_32_FLOAT
;
340 comp_swap
= SWAP_ALT_REV
;
341 number_type
= NUMBER_FLOAT
;
344 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
345 #ifdef MESA_BIG_ENDIAN
346 endian
= ENDIAN_8IN16
;
348 format
= COLOR_16_16_FLOAT
;
349 comp_swap
= SWAP_ALT_REV
;
350 number_type
= NUMBER_FLOAT
;
353 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
354 #ifdef MESA_BIG_ENDIAN
355 endian
= ENDIAN_8IN32
;
357 format
= COLOR_32_FLOAT
;
358 comp_swap
= SWAP_STD
;
359 number_type
= NUMBER_FLOAT
;
362 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
363 #ifdef MESA_BIG_ENDIAN
364 endian
= ENDIAN_8IN16
;
366 format
= COLOR_16_FLOAT
;
367 comp_swap
= SWAP_STD
;
368 number_type
= NUMBER_UNORM
;
371 case MESA_FORMAT_X8_Z24
:
372 case MESA_FORMAT_S8_Z24
:
373 #ifdef MESA_BIG_ENDIAN
374 endian
= ENDIAN_8IN32
;
377 comp_swap
= SWAP_STD
;
378 number_type
= NUMBER_UNORM
;
379 SETfield(cb_color0_info
,
380 ARRAY_1D_TILED_THIN1
,
381 EG_CB_COLOR0_INFO__ARRAY_MODE_shift
,
382 EG_CB_COLOR0_INFO__ARRAY_MODE_mask
);
385 case MESA_FORMAT_Z24_S8
:
386 #ifdef MESA_BIG_ENDIAN
387 endian
= ENDIAN_8IN32
;
390 comp_swap
= SWAP_STD
;
391 number_type
= NUMBER_UNORM
;
392 SETfield(cb_color0_info
,
393 ARRAY_1D_TILED_THIN1
,
394 EG_CB_COLOR0_INFO__ARRAY_MODE_shift
,
395 EG_CB_COLOR0_INFO__ARRAY_MODE_mask
);
398 case MESA_FORMAT_Z16
:
399 #ifdef MESA_BIG_ENDIAN
400 endian
= ENDIAN_8IN16
;
403 comp_swap
= SWAP_STD
;
404 number_type
= NUMBER_UNORM
;
405 SETfield(cb_color0_info
,
406 ARRAY_1D_TILED_THIN1
,
407 EG_CB_COLOR0_INFO__ARRAY_MODE_shift
,
408 EG_CB_COLOR0_INFO__ARRAY_MODE_mask
);
411 case MESA_FORMAT_Z32
:
412 #ifdef MESA_BIG_ENDIAN
413 endian
= ENDIAN_8IN32
;
416 comp_swap
= SWAP_STD
;
417 number_type
= NUMBER_UNORM
;
418 SETfield(cb_color0_info
,
419 ARRAY_1D_TILED_THIN1
,
420 EG_CB_COLOR0_INFO__ARRAY_MODE_shift
,
421 EG_CB_COLOR0_INFO__ARRAY_MODE_mask
);
424 case MESA_FORMAT_SARGB8
:
425 #ifdef MESA_BIG_ENDIAN
426 endian
= ENDIAN_8IN32
;
428 format
= COLOR_8_8_8_8
;
429 comp_swap
= SWAP_ALT
;
430 number_type
= NUMBER_SRGB
;
433 case MESA_FORMAT_SLA8
:
434 #ifdef MESA_BIG_ENDIAN
435 endian
= ENDIAN_8IN16
;
438 comp_swap
= SWAP_ALT_REV
;
439 number_type
= NUMBER_SRGB
;
442 case MESA_FORMAT_SL8
:
444 comp_swap
= SWAP_ALT_REV
;
445 number_type
= NUMBER_SRGB
;
449 fprintf(stderr
,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format
));
450 assert("Invalid format for US output\n");
454 SETfield(cb_color0_info
,
456 EG_CB_COLOR0_INFO__ENDIAN_shift
,
457 EG_CB_COLOR0_INFO__ENDIAN_mask
);
458 SETfield(cb_color0_info
,
460 EG_CB_COLOR0_INFO__FORMAT_shift
,
461 EG_CB_COLOR0_INFO__FORMAT_mask
);
462 SETfield(cb_color0_info
,
464 EG_CB_COLOR0_INFO__COMP_SWAP_shift
,
465 EG_CB_COLOR0_INFO__COMP_SWAP_mask
);
466 SETfield(cb_color0_info
,
468 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift
,
469 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask
);
470 SETfield(cb_color0_info
,
472 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift
,
473 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask
);
475 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
476 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE
+ (4 * id
), 1);
477 R600_OUT_BATCH(cb_color0_base
);
478 R600_OUT_BATCH_RELOC(cb_color0_base
,
481 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
484 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
485 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO
, cb_color0_info
);
486 R600_OUT_BATCH_RELOC(cb_color0_info
,
489 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
492 BEGIN_BATCH_NO_AUTOSTATE(5);
493 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH
, 3);
494 R600_OUT_BATCH(cb_color0_pitch
);
495 R600_OUT_BATCH(cb_color0_slice
);
499 BEGIN_BATCH_NO_AUTOSTATE(4);
500 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB
, 2);
501 R600_OUT_BATCH(cb_color0_attrib
);
504 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
505 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
506 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
507 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
515 static inline void eg_load_shaders(struct gl_context
* ctx
)
518 radeonContextPtr radeonctx
= RADEON_CONTEXT(ctx
);
519 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
523 if (context
->blit_bo_loaded
== 1)
527 context
->blit_bo
= radeon_bo_open(radeonctx
->radeonScreen
->bom
, 0,
528 size
, 256, RADEON_GEM_DOMAIN_GTT
, 0);
529 radeon_bo_map(context
->blit_bo
, 1);
530 shader
= context
->blit_bo
->ptr
;
532 for(i
=0; i
<sizeof(evergreen_vs
)/4; i
++) {
533 shader
[128+i
] = CPU_TO_LE32(evergreen_vs
[i
]);
535 for(i
=0; i
<sizeof(evergreen_ps
)/4; i
++) {
536 shader
[256+i
] = CPU_TO_LE32(evergreen_ps
[i
]);
539 radeon_bo_unmap(context
->blit_bo
);
540 context
->blit_bo_loaded
= 1;
545 eg_set_shaders(context_t
*context
)
547 struct radeon_bo
* pbo
= context
->blit_bo
;
548 uint32_t sq_pgm_start_fs
= (512 >> 8);
549 uint32_t sq_pgm_resources_fs
= 0;
551 uint32_t sq_pgm_start_vs
= (512 >> 8);
552 uint32_t sq_pgm_resources_vs
= (2 << NUM_GPRS_shift
);
554 uint32_t sq_pgm_start_ps
= (1024 >> 8);
555 uint32_t sq_pgm_resources_ps
= (1 << NUM_GPRS_shift
);
556 uint32_t sq_pgm_exports_ps
= (1 << 1);
557 BATCH_LOCALS(&context
->radeon
);
559 r700SyncSurf(context
, pbo
, RADEON_GEM_DOMAIN_GTT
, 0, SH_ACTION_ENA_bit
);
562 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
563 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_FS
, 1);
564 R600_OUT_BATCH(sq_pgm_start_fs
);
565 R600_OUT_BATCH_RELOC(sq_pgm_start_fs
,
568 RADEON_GEM_DOMAIN_GTT
, 0, 0);
571 BEGIN_BATCH_NO_AUTOSTATE(3);
572 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_PGM_RESOURCES_FS
, sq_pgm_resources_fs
);
576 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
577 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS
, 1);
578 R600_OUT_BATCH(sq_pgm_start_vs
);
579 R600_OUT_BATCH_RELOC(sq_pgm_start_vs
,
582 RADEON_GEM_DOMAIN_GTT
, 0, 0);
585 BEGIN_BATCH_NO_AUTOSTATE(4);
586 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS
, 2);
587 R600_OUT_BATCH(sq_pgm_resources_vs
);
592 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
593 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS
, 1);
594 R600_OUT_BATCH(sq_pgm_start_ps
);
595 R600_OUT_BATCH_RELOC(sq_pgm_start_ps
,
598 RADEON_GEM_DOMAIN_GTT
, 0, 0);
601 BEGIN_BATCH_NO_AUTOSTATE(5);
602 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS
, 3);
603 R600_OUT_BATCH(sq_pgm_resources_ps
);
605 R600_OUT_BATCH(sq_pgm_exports_ps
);
613 eg_set_vtx_resource(context_t
*context
)
615 struct radeon_bo
*bo
= context
->blit_bo
;
616 uint32_t sq_vtx_constant_word3
= 0;
617 uint32_t sq_vtx_constant_word2
= 0;
618 BATCH_LOCALS(&context
->radeon
);
620 BEGIN_BATCH_NO_AUTOSTATE(6);
621 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 1));
622 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
625 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 1));
626 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
630 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_CEDAR
)
631 r700SyncSurf(context
, bo
, RADEON_GEM_DOMAIN_GTT
, 0, TC_ACTION_ENA_bit
);
633 r700SyncSurf(context
, bo
, RADEON_GEM_DOMAIN_GTT
, 0, VC_ACTION_ENA_bit
);
635 SETfield(sq_vtx_constant_word3
, SQ_SEL_X
,
636 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift
,
637 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask
);
638 SETfield(sq_vtx_constant_word3
, SQ_SEL_Y
,
639 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift
,
640 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask
);
641 SETfield(sq_vtx_constant_word3
, SQ_SEL_Z
,
642 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift
,
643 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask
);
644 SETfield(sq_vtx_constant_word3
, SQ_SEL_W
,
645 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift
,
646 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask
);
648 sq_vtx_constant_word2
= 0
649 #ifdef MESA_BIG_ENDIAN
650 | (SQ_ENDIAN_8IN32
<< SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift
)
652 | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift
);
654 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
656 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE
, 8));
657 R600_OUT_BATCH(EG_SQ_FETCH_RESOURCE_VS_OFFSET
* EG_FETCH_RESOURCE_STRIDE
);
659 R600_OUT_BATCH(48 - 1);
660 R600_OUT_BATCH(sq_vtx_constant_word2
);
661 R600_OUT_BATCH(sq_vtx_constant_word3
);
665 R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER
<< SQ_TEX_RESOURCE_WORD6_0__TYPE_shift
);
666 R600_OUT_BATCH_RELOC(0,
669 RADEON_GEM_DOMAIN_GTT
, 0, 0);
676 eg_set_tex_resource(context_t
* context
,
677 gl_format mesa_format
, struct radeon_bo
*bo
, int w
, int h
,
678 int TexelPitch
, intptr_t src_offset
)
680 uint32_t sq_tex_resource0
, sq_tex_resource1
, sq_tex_resource2
, sq_tex_resource4
, sq_tex_resource7
;
682 sq_tex_resource0
= sq_tex_resource1
= sq_tex_resource2
= sq_tex_resource4
= sq_tex_resource7
= 0;
683 BATCH_LOCALS(&context
->radeon
);
685 SETfield(sq_tex_resource0
, SQ_TEX_DIM_2D
, DIM_shift
, DIM_mask
);
686 SETfield(sq_tex_resource0
, ARRAY_LINEAR_GENERAL
,
687 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
688 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
690 switch (mesa_format
) {
691 case MESA_FORMAT_RGBA8888
:
692 case MESA_FORMAT_SIGNED_RGBA8888
:
693 SETfield(sq_tex_resource7
, FMT_8_8_8_8
,
694 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
695 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
696 SETfield(sq_tex_resource4
, SQ_SEL_W
,
697 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
698 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
699 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
700 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
701 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
702 SETfield(sq_tex_resource4
, SQ_SEL_X
,
703 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
704 if (mesa_format
== MESA_FORMAT_SIGNED_RGBA8888
) {
705 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
706 FORMAT_COMP_X_shift
, FORMAT_COMP_X_mask
);
707 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
708 FORMAT_COMP_Y_shift
, FORMAT_COMP_Y_mask
);
709 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
710 FORMAT_COMP_Z_shift
, FORMAT_COMP_Z_mask
);
711 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
712 FORMAT_COMP_W_shift
, FORMAT_COMP_W_mask
);
715 case MESA_FORMAT_RGBA8888_REV
:
716 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
717 SETfield(sq_tex_resource7
, FMT_8_8_8_8
,
718 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
719 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
720 SETfield(sq_tex_resource4
, SQ_SEL_X
,
721 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
722 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
723 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
724 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
725 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
726 SETfield(sq_tex_resource4
, SQ_SEL_W
,
727 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
728 if (mesa_format
== MESA_FORMAT_SIGNED_RGBA8888_REV
) {
729 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
730 FORMAT_COMP_X_shift
, FORMAT_COMP_X_mask
);
731 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
732 FORMAT_COMP_Y_shift
, FORMAT_COMP_Y_mask
);
733 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
734 FORMAT_COMP_Z_shift
, FORMAT_COMP_Z_mask
);
735 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
736 FORMAT_COMP_W_shift
, FORMAT_COMP_W_mask
);
739 case MESA_FORMAT_ARGB8888
:
740 SETfield(sq_tex_resource7
, FMT_8_8_8_8
,
741 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
742 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
743 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
744 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
745 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
746 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
747 SETfield(sq_tex_resource4
, SQ_SEL_X
,
748 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
749 SETfield(sq_tex_resource4
, SQ_SEL_W
,
750 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
752 case MESA_FORMAT_XRGB8888
:
753 SETfield(sq_tex_resource7
, FMT_8_8_8_8
,
754 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
755 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
756 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
757 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
758 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
759 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
760 SETfield(sq_tex_resource4
, SQ_SEL_X
,
761 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
762 SETfield(sq_tex_resource4
, SQ_SEL_1
,
763 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
765 case MESA_FORMAT_ARGB8888_REV
:
766 SETfield(sq_tex_resource7
, FMT_8_8_8_8
,
767 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
768 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
769 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
770 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
771 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
772 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
773 SETfield(sq_tex_resource4
, SQ_SEL_W
,
774 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
775 SETfield(sq_tex_resource4
, SQ_SEL_X
,
776 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
778 case MESA_FORMAT_XRGB8888_REV
:
779 SETfield(sq_tex_resource7
, FMT_8_8_8_8
,
780 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
781 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
782 SETfield(sq_tex_resource4
, SQ_SEL_1
,
783 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
784 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
785 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
786 SETfield(sq_tex_resource4
, SQ_SEL_W
,
787 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
788 SETfield(sq_tex_resource4
, SQ_SEL_X
,
789 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
791 case MESA_FORMAT_RGB565
:
792 SETfield(sq_tex_resource7
, FMT_5_6_5
,
793 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
794 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
795 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
796 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
797 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
798 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
799 SETfield(sq_tex_resource4
, SQ_SEL_X
,
800 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
801 SETfield(sq_tex_resource4
, SQ_SEL_1
,
802 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
804 case MESA_FORMAT_RGB565_REV
:
805 SETfield(sq_tex_resource7
, FMT_5_6_5
,
806 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
807 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
808 SETfield(sq_tex_resource4
, SQ_SEL_X
,
809 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
810 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
811 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
812 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
813 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
814 SETfield(sq_tex_resource4
, SQ_SEL_1
,
815 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
817 case MESA_FORMAT_ARGB4444
:
818 SETfield(sq_tex_resource7
, FMT_4_4_4_4
,
819 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
820 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
821 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
822 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
823 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
824 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
825 SETfield(sq_tex_resource4
, SQ_SEL_X
,
826 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
827 SETfield(sq_tex_resource4
, SQ_SEL_W
,
828 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
830 case MESA_FORMAT_ARGB4444_REV
:
831 SETfield(sq_tex_resource7
, FMT_4_4_4_4
,
832 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
833 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
834 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
835 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
836 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
837 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
838 SETfield(sq_tex_resource4
, SQ_SEL_W
,
839 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
840 SETfield(sq_tex_resource4
, SQ_SEL_X
,
841 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
843 case MESA_FORMAT_ARGB1555
:
844 SETfield(sq_tex_resource7
, FMT_1_5_5_5
,
845 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
846 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
847 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
848 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
849 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
850 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
851 SETfield(sq_tex_resource4
, SQ_SEL_X
,
852 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
853 SETfield(sq_tex_resource4
, SQ_SEL_W
,
854 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
856 case MESA_FORMAT_ARGB1555_REV
:
857 SETfield(sq_tex_resource7
, FMT_1_5_5_5
,
858 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
859 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
860 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
861 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
862 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
863 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
864 SETfield(sq_tex_resource4
, SQ_SEL_W
,
865 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
866 SETfield(sq_tex_resource4
, SQ_SEL_X
,
867 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
869 case MESA_FORMAT_AL88
:
870 case MESA_FORMAT_AL88_REV
: /* TODO : Check this. */
871 SETfield(sq_tex_resource7
, FMT_8_8
,
872 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
873 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
874 SETfield(sq_tex_resource4
, SQ_SEL_X
,
875 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
876 SETfield(sq_tex_resource4
, SQ_SEL_X
,
877 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
878 SETfield(sq_tex_resource4
, SQ_SEL_X
,
879 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
880 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
881 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
883 case MESA_FORMAT_RGB332
:
884 SETfield(sq_tex_resource7
, FMT_3_3_2
,
885 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
886 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
887 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
888 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
889 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
890 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
891 SETfield(sq_tex_resource4
, SQ_SEL_X
,
892 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
893 SETfield(sq_tex_resource4
, SQ_SEL_1
,
894 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
896 case MESA_FORMAT_A8
: /* ZERO, ZERO, ZERO, X */
897 SETfield(sq_tex_resource7
, FMT_8
,
898 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
899 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
900 SETfield(sq_tex_resource4
, SQ_SEL_0
,
901 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
902 SETfield(sq_tex_resource4
, SQ_SEL_0
,
903 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
904 SETfield(sq_tex_resource4
, SQ_SEL_0
,
905 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
906 SETfield(sq_tex_resource4
, SQ_SEL_X
,
907 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
909 case MESA_FORMAT_L8
: /* X, X, X, ONE */
910 SETfield(sq_tex_resource7
, FMT_8
,
911 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
912 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
913 SETfield(sq_tex_resource4
, SQ_SEL_X
,
914 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
915 SETfield(sq_tex_resource4
, SQ_SEL_X
,
916 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
917 SETfield(sq_tex_resource4
, SQ_SEL_X
,
918 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
919 SETfield(sq_tex_resource4
, SQ_SEL_1
,
920 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
922 case MESA_FORMAT_I8
: /* X, X, X, X */
923 SETfield(sq_tex_resource7
, FMT_8
,
924 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
925 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
926 SETfield(sq_tex_resource4
, SQ_SEL_X
,
927 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
928 SETfield(sq_tex_resource4
, SQ_SEL_X
,
929 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
930 SETfield(sq_tex_resource4
, SQ_SEL_X
,
931 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
932 SETfield(sq_tex_resource4
, SQ_SEL_X
,
933 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
935 case MESA_FORMAT_RGBA_FLOAT32
:
936 SETfield(sq_tex_resource7
, FMT_32_32_32_32_FLOAT
,
937 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
938 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
939 SETfield(sq_tex_resource4
, SQ_SEL_X
,
940 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
941 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
942 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
943 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
944 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
945 SETfield(sq_tex_resource4
, SQ_SEL_W
,
946 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
948 case MESA_FORMAT_RGBA_FLOAT16
:
949 SETfield(sq_tex_resource7
, FMT_16_16_16_16_FLOAT
,
950 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
951 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
952 SETfield(sq_tex_resource4
, SQ_SEL_X
,
953 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
954 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
955 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
956 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
957 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
958 SETfield(sq_tex_resource4
, SQ_SEL_W
,
959 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
961 case MESA_FORMAT_ALPHA_FLOAT32
: /* ZERO, ZERO, ZERO, X */
962 SETfield(sq_tex_resource7
, FMT_32_FLOAT
,
963 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
964 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
965 SETfield(sq_tex_resource4
, SQ_SEL_0
,
966 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
967 SETfield(sq_tex_resource4
, SQ_SEL_0
,
968 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
969 SETfield(sq_tex_resource4
, SQ_SEL_0
,
970 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
971 SETfield(sq_tex_resource4
, SQ_SEL_X
,
972 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
974 case MESA_FORMAT_ALPHA_FLOAT16
: /* ZERO, ZERO, ZERO, X */
975 SETfield(sq_tex_resource7
, FMT_16_FLOAT
,
976 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
977 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
978 SETfield(sq_tex_resource4
, SQ_SEL_0
,
979 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
980 SETfield(sq_tex_resource4
, SQ_SEL_0
,
981 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
982 SETfield(sq_tex_resource4
, SQ_SEL_0
,
983 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
984 SETfield(sq_tex_resource4
, SQ_SEL_X
,
985 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
987 case MESA_FORMAT_LUMINANCE_FLOAT32
: /* X, X, X, ONE */
988 SETfield(sq_tex_resource7
, FMT_32_FLOAT
,
989 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
990 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
991 SETfield(sq_tex_resource4
, SQ_SEL_X
,
992 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
993 SETfield(sq_tex_resource4
, SQ_SEL_X
,
994 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
995 SETfield(sq_tex_resource4
, SQ_SEL_X
,
996 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
997 SETfield(sq_tex_resource4
, SQ_SEL_1
,
998 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1000 case MESA_FORMAT_LUMINANCE_FLOAT16
: /* X, X, X, ONE */
1001 SETfield(sq_tex_resource7
, FMT_16_FLOAT
,
1002 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1003 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1004 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1005 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1006 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1007 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1008 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1009 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1010 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1011 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1013 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
1014 SETfield(sq_tex_resource7
, FMT_32_32_FLOAT
,
1015 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1016 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1017 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1018 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1019 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1020 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1021 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1022 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1023 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1024 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1026 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
1027 SETfield(sq_tex_resource7
, FMT_16_16_FLOAT
,
1028 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1029 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1030 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1031 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1032 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1033 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1034 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1035 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1036 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1037 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1039 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
1040 SETfield(sq_tex_resource7
, FMT_32_FLOAT
,
1041 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1042 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1043 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1044 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1045 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1046 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1047 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1048 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1049 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1050 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1052 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
1053 SETfield(sq_tex_resource7
, FMT_16_FLOAT
,
1054 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1055 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1056 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1057 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1058 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1059 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1060 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1061 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1062 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1063 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1065 case MESA_FORMAT_Z16
:
1067 CLEARbit(sq_tex_resource0
, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit
);
1068 SETfield(sq_tex_resource1
, ARRAY_1D_TILED_THIN1
,
1069 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift
,
1070 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask
);
1071 SETfield(sq_tex_resource7
, FMT_16
,
1072 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1073 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1074 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1075 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1076 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1077 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1078 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1079 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1080 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1081 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1083 case MESA_FORMAT_X8_Z24
:
1085 CLEARbit(sq_tex_resource0
, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit
);
1086 SETfield(sq_tex_resource1
, ARRAY_1D_TILED_THIN1
,
1087 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift
,
1088 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask
);
1089 SETfield(sq_tex_resource7
, FMT_8_24
,
1090 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1091 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1092 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1093 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1094 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1095 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1096 SETfield(sq_tex_resource4
, SQ_SEL_0
,
1097 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1098 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1099 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1101 case MESA_FORMAT_S8_Z24
:
1103 CLEARbit(sq_tex_resource0
, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit
);
1104 SETfield(sq_tex_resource1
, ARRAY_1D_TILED_THIN1
,
1105 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift
,
1106 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask
);
1107 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1108 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1109 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1110 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1111 SETfield(sq_tex_resource7
, FMT_8_24
,
1112 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1113 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1114 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1115 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1116 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1117 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1118 SETfield(sq_tex_resource4
, SQ_SEL_0
,
1119 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1120 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1121 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1123 case MESA_FORMAT_Z24_S8
:
1125 CLEARbit(sq_tex_resource0
, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit
);
1126 SETfield(sq_tex_resource1
, ARRAY_1D_TILED_THIN1
,
1127 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift
,
1128 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask
);
1129 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1130 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1131 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1132 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1133 SETfield(sq_tex_resource7
, FMT_24_8
,
1134 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1135 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1136 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1137 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1138 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1139 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1140 SETfield(sq_tex_resource4
, SQ_SEL_0
,
1141 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1142 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1143 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1145 case MESA_FORMAT_Z32
:
1147 CLEARbit(sq_tex_resource0
, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit
);
1148 SETfield(sq_tex_resource1
, ARRAY_1D_TILED_THIN1
,
1149 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift
,
1150 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask
);
1151 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1152 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1153 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1154 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1155 SETfield(sq_tex_resource7
, FMT_32
,
1156 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1157 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1158 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1159 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1160 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1161 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1162 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1163 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1164 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1165 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1167 case MESA_FORMAT_S8
:
1169 CLEARbit(sq_tex_resource0
, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit
);
1170 SETfield(sq_tex_resource1
, ARRAY_1D_TILED_THIN1
,
1171 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift
,
1172 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask
);
1173 SETfield(sq_tex_resource7
, FMT_8
,
1174 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1175 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1176 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1177 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1178 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1179 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1180 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1181 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1182 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1183 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1185 case MESA_FORMAT_SARGB8
:
1186 SETfield(sq_tex_resource7
, FMT_8_8_8_8
,
1187 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1188 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1189 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
1190 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1191 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1192 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1193 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1194 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1195 SETfield(sq_tex_resource4
, SQ_SEL_W
,
1196 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1197 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1199 case MESA_FORMAT_SLA8
:
1200 SETfield(sq_tex_resource7
, FMT_8_8
,
1201 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1202 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1203 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1204 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1205 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1206 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1207 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1208 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1209 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1210 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1211 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1213 case MESA_FORMAT_SL8
: /* X, X, X, ONE */
1214 SETfield(sq_tex_resource7
, FMT_8
,
1215 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift
,
1216 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask
);
1217 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1218 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1219 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1220 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1221 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1222 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1223 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1224 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1225 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1228 fprintf(stderr
,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format
));
1229 assert("Invalid format for US output\n");
1233 SETfield(sq_tex_resource0
, (TexelPitch
/8)-1,
1234 EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift
,
1235 EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask
);
1236 SETfield(sq_tex_resource0
, w
- 1,
1237 EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift
,
1238 EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask
);
1239 SETfield(sq_tex_resource1
, h
- 1,
1240 EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift
,
1241 EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask
);
1243 sq_tex_resource2
= src_offset
/ 256;
1245 SETfield(sq_tex_resource7
, SQ_TEX_VTX_VALID_TEXTURE
,
1246 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift
,
1247 SQ_TEX_RESOURCE_WORD6_0__TYPE_mask
);
1249 r700SyncSurf(context
, bo
,
1250 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
,
1251 0, TC_ACTION_ENA_bit
);
1253 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
1254 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE
, 8));
1255 R600_OUT_BATCH(0 * 7);
1256 R600_OUT_BATCH(sq_tex_resource0
);
1257 R600_OUT_BATCH(sq_tex_resource1
);
1258 R600_OUT_BATCH(sq_tex_resource2
);
1260 R600_OUT_BATCH(sq_tex_resource4
);
1263 R600_OUT_BATCH(sq_tex_resource7
);
1264 R600_OUT_BATCH_RELOC(0,
1267 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
1268 R600_OUT_BATCH_RELOC(0,
1271 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
1277 eg_set_tex_sampler(context_t
* context
)
1279 uint32_t sq_tex_sampler_word0
= 0, sq_tex_sampler_word1
= 0, sq_tex_sampler_word2
= 0;
1282 SETbit(sq_tex_sampler_word2
, EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit
);
1284 BATCH_LOCALS(&context
->radeon
);
1286 BEGIN_BATCH_NO_AUTOSTATE(5);
1287 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER
, 3));
1288 R600_OUT_BATCH(i
* 3);
1289 R600_OUT_BATCH(sq_tex_sampler_word0
);
1290 R600_OUT_BATCH(sq_tex_sampler_word1
);
1291 R600_OUT_BATCH(sq_tex_sampler_word2
);
1297 eg_set_scissors(context_t
*context
, int x1
, int y1
, int x2
, int y2
)
1299 BATCH_LOCALS(&context
->radeon
);
1301 BEGIN_BATCH_NO_AUTOSTATE(17);
1302 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL
, 2);
1303 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16));
1304 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1306 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET
, 3);
1307 R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1308 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
)); //PA_SC_WINDOW_SCISSOR_TL
1309 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1311 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL
, 2);
1312 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
));
1313 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1315 /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1316 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1317 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
));
1318 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1326 eg_set_vb_data(context_t
* context
, int src_x
, int src_y
, int dst_x
, int dst_y
,
1327 int w
, int h
, int src_h
, unsigned flip_y
)
1330 radeon_bo_map(context
->blit_bo
, 1);
1331 vb
= context
->blit_bo
->ptr
;
1333 vb
[0] = (float)(dst_x
);
1334 vb
[1] = (float)(dst_y
);
1335 vb
[2] = (float)(src_x
);
1336 vb
[3] = (flip_y
) ? (float)(src_h
- src_y
) : (float)src_y
;
1338 vb
[4] = (float)(dst_x
);
1339 vb
[5] = (float)(dst_y
+ h
);
1340 vb
[6] = (float)(src_x
);
1341 vb
[7] = (flip_y
) ? (float)(src_h
- (src_y
+ h
)) : (float)(src_y
+ h
);
1343 vb
[8] = (float)(dst_x
+ w
);
1344 vb
[9] = (float)(dst_y
+ h
);
1345 vb
[10] = (float)(src_x
+ w
);
1346 vb
[11] = (flip_y
) ? (float)(src_h
- (src_y
+ h
)) : (float)(src_y
+ h
);
1348 radeon_bo_unmap(context
->blit_bo
);
1353 eg_draw_auto(context_t
*context
)
1355 BATCH_LOCALS(&context
->radeon
);
1356 uint32_t vgt_primitive_type
= 0, vgt_index_type
= 0, vgt_draw_initiator
= 0, vgt_num_indices
;
1358 SETfield(vgt_primitive_type
, DI_PT_RECTLIST
,
1359 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
,
1360 VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
1361 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
,
1363 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
,
1365 SETfield(vgt_draw_initiator
, DI_SRC_SEL_AUTO_INDEX
, SOURCE_SELECT_shift
,
1366 SOURCE_SELECT_mask
);
1368 vgt_num_indices
= 3;
1370 BEGIN_BATCH_NO_AUTOSTATE(10);
1372 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVE_TYPE
, 1);
1373 R600_OUT_BATCH(vgt_primitive_type
);
1375 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
1376 R600_OUT_BATCH(vgt_index_type
);
1378 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
1381 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO
, 1));
1382 R600_OUT_BATCH(vgt_num_indices
);
1383 R600_OUT_BATCH(vgt_draw_initiator
);
1390 eg_set_default_state(context_t
*context
)
1405 int num_ps_stack_entries
;
1406 int num_vs_stack_entries
;
1407 int num_gs_stack_entries
;
1408 int num_es_stack_entries
;
1409 int num_hs_stack_entries
;
1410 int num_ls_stack_entries
;
1411 uint32_t sq_config
= 0, sq_gpr_resource_mgmt_1
= 0, sq_gpr_resource_mgmt_2
= 0;
1412 uint32_t sq_gpr_resource_mgmt_3
= 0;
1413 uint32_t sq_thread_resource_mgmt
= 0, sq_thread_resource_mgmt_2
= 0;
1414 uint32_t sq_stack_resource_mgmt_1
= 0, sq_stack_resource_mgmt_2
= 0, sq_stack_resource_mgmt_3
= 0;
1415 BATCH_LOCALS(&context
->radeon
);
1417 switch (context
->radeon
.radeonScreen
->chip_family
) {
1418 case CHIP_FAMILY_CEDAR
:
1427 num_ps_threads
= 96;
1428 num_vs_threads
= 16;
1429 num_gs_threads
= 16;
1430 num_es_threads
= 16;
1431 num_hs_threads
= 16;
1432 num_ls_threads
= 16;
1433 num_ps_stack_entries
= 42;
1434 num_vs_stack_entries
= 42;
1435 num_gs_stack_entries
= 42;
1436 num_es_stack_entries
= 42;
1437 num_hs_stack_entries
= 42;
1438 num_ls_stack_entries
= 42;
1440 case CHIP_FAMILY_REDWOOD
:
1448 num_ps_threads
= 128;
1449 num_vs_threads
= 20;
1450 num_gs_threads
= 20;
1451 num_es_threads
= 20;
1452 num_hs_threads
= 20;
1453 num_ls_threads
= 20;
1454 num_ps_stack_entries
= 42;
1455 num_vs_stack_entries
= 42;
1456 num_gs_stack_entries
= 42;
1457 num_es_stack_entries
= 42;
1458 num_hs_stack_entries
= 42;
1459 num_ls_stack_entries
= 42;
1461 case CHIP_FAMILY_JUNIPER
:
1469 num_ps_threads
= 128;
1470 num_vs_threads
= 20;
1471 num_gs_threads
= 20;
1472 num_es_threads
= 20;
1473 num_hs_threads
= 20;
1474 num_ls_threads
= 20;
1475 num_ps_stack_entries
= 85;
1476 num_vs_stack_entries
= 85;
1477 num_gs_stack_entries
= 85;
1478 num_es_stack_entries
= 85;
1479 num_hs_stack_entries
= 85;
1480 num_ls_stack_entries
= 85;
1482 case CHIP_FAMILY_CYPRESS
:
1483 case CHIP_FAMILY_HEMLOCK
:
1491 num_ps_threads
= 128;
1492 num_vs_threads
= 20;
1493 num_gs_threads
= 20;
1494 num_es_threads
= 20;
1495 num_hs_threads
= 20;
1496 num_ls_threads
= 20;
1497 num_ps_stack_entries
= 85;
1498 num_vs_stack_entries
= 85;
1499 num_gs_stack_entries
= 85;
1500 num_es_stack_entries
= 85;
1501 num_hs_stack_entries
= 85;
1502 num_ls_stack_entries
= 85;
1504 case CHIP_FAMILY_PALM
:
1512 num_ps_threads
= 96;
1513 num_vs_threads
= 16;
1514 num_gs_threads
= 16;
1515 num_es_threads
= 16;
1516 num_hs_threads
= 16;
1517 num_ls_threads
= 16;
1518 num_ps_stack_entries
= 42;
1519 num_vs_stack_entries
= 42;
1520 num_gs_stack_entries
= 42;
1521 num_es_stack_entries
= 42;
1522 num_hs_stack_entries
= 42;
1523 num_ls_stack_entries
= 42;
1525 case CHIP_FAMILY_SUMO
:
1533 num_ps_threads
= 96;
1534 num_vs_threads
= 25;
1535 num_gs_threads
= 25;
1536 num_es_threads
= 25;
1537 num_hs_threads
= 25;
1538 num_ls_threads
= 25;
1539 num_ps_stack_entries
= 42;
1540 num_vs_stack_entries
= 42;
1541 num_gs_stack_entries
= 42;
1542 num_es_stack_entries
= 42;
1543 num_hs_stack_entries
= 42;
1544 num_ls_stack_entries
= 42;
1546 case CHIP_FAMILY_SUMO2
:
1554 num_ps_threads
= 96;
1555 num_vs_threads
= 25;
1556 num_gs_threads
= 25;
1557 num_es_threads
= 25;
1558 num_hs_threads
= 25;
1559 num_ls_threads
= 25;
1560 num_ps_stack_entries
= 85;
1561 num_vs_stack_entries
= 85;
1562 num_gs_stack_entries
= 85;
1563 num_es_stack_entries
= 85;
1564 num_hs_stack_entries
= 85;
1565 num_ls_stack_entries
= 85;
1567 case CHIP_FAMILY_BARTS
:
1575 num_ps_threads
= 128;
1576 num_vs_threads
= 20;
1577 num_gs_threads
= 20;
1578 num_es_threads
= 20;
1579 num_hs_threads
= 20;
1580 num_ls_threads
= 20;
1581 num_ps_stack_entries
= 85;
1582 num_vs_stack_entries
= 85;
1583 num_gs_stack_entries
= 85;
1584 num_es_stack_entries
= 85;
1585 num_hs_stack_entries
= 85;
1586 num_ls_stack_entries
= 85;
1588 case CHIP_FAMILY_TURKS
:
1596 num_ps_threads
= 128;
1597 num_vs_threads
= 20;
1598 num_gs_threads
= 20;
1599 num_es_threads
= 20;
1600 num_hs_threads
= 20;
1601 num_ls_threads
= 20;
1602 num_ps_stack_entries
= 42;
1603 num_vs_stack_entries
= 42;
1604 num_gs_stack_entries
= 42;
1605 num_es_stack_entries
= 42;
1606 num_hs_stack_entries
= 42;
1607 num_ls_stack_entries
= 42;
1609 case CHIP_FAMILY_CAICOS
:
1617 num_ps_threads
= 128;
1618 num_vs_threads
= 10;
1619 num_gs_threads
= 10;
1620 num_es_threads
= 10;
1621 num_hs_threads
= 10;
1622 num_ls_threads
= 10;
1623 num_ps_stack_entries
= 42;
1624 num_vs_stack_entries
= 42;
1625 num_gs_stack_entries
= 42;
1626 num_es_stack_entries
= 42;
1627 num_hs_stack_entries
= 42;
1628 num_ls_stack_entries
= 42;
1632 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_CEDAR
) ||
1633 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_PALM
) ||
1634 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_SUMO
) ||
1635 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_SUMO2
) ||
1636 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_CAICOS
))
1637 CLEARbit(sq_config
, EG_SQ_CONFIG__VC_ENABLE_bit
);
1639 SETbit(sq_config
, EG_SQ_CONFIG__VC_ENABLE_bit
);
1640 SETbit(sq_config
, EG_SQ_CONFIG__EXPORT_SRC_C_bit
);
1642 SETfield(sq_config
, 0,
1643 EG_SQ_CONFIG__PS_PRIO_shift
,
1644 EG_SQ_CONFIG__PS_PRIO_mask
);
1645 SETfield(sq_config
, 1,
1646 EG_SQ_CONFIG__VS_PRIO_shift
,
1647 EG_SQ_CONFIG__VS_PRIO_mask
);
1648 SETfield(sq_config
, 2,
1649 EG_SQ_CONFIG__GS_PRIO_shift
,
1650 EG_SQ_CONFIG__GS_PRIO_mask
);
1651 SETfield(sq_config
, 3,
1652 EG_SQ_CONFIG__ES_PRIO_shift
,
1653 EG_SQ_CONFIG__ES_PRIO_mask
);
1656 SETfield(sq_gpr_resource_mgmt_1
, num_ps_gprs
,
1657 NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1658 SETfield(sq_gpr_resource_mgmt_1
, num_vs_gprs
,
1659 NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1660 SETfield(sq_gpr_resource_mgmt_1
, num_temp_gprs
,
1661 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1662 SETfield(sq_gpr_resource_mgmt_2
, num_gs_gprs
,
1663 NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1664 SETfield(sq_gpr_resource_mgmt_2
, num_es_gprs
,
1665 NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1666 SETfield(sq_gpr_resource_mgmt_3
, num_hs_gprs
,
1667 NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1668 SETfield(sq_gpr_resource_mgmt_3
, num_ls_gprs
,
1669 NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1671 SETfield(sq_thread_resource_mgmt
, num_ps_threads
,
1672 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1673 SETfield(sq_thread_resource_mgmt
, num_vs_threads
,
1674 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1675 SETfield(sq_thread_resource_mgmt
, num_gs_threads
,
1676 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1677 SETfield(sq_thread_resource_mgmt
, num_es_threads
,
1678 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1679 SETfield(sq_thread_resource_mgmt_2
, num_hs_threads
,
1680 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1681 SETfield(sq_thread_resource_mgmt_2
, num_ls_threads
,
1682 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1684 SETfield(sq_stack_resource_mgmt_1
, num_ps_stack_entries
,
1685 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1686 SETfield(sq_stack_resource_mgmt_1
, num_vs_stack_entries
,
1687 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1688 SETfield(sq_stack_resource_mgmt_2
, num_gs_stack_entries
,
1689 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1690 SETfield(sq_stack_resource_mgmt_2
, num_es_stack_entries
,
1691 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1692 SETfield(sq_stack_resource_mgmt_3
, num_hs_stack_entries
,
1693 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1694 SETfield(sq_stack_resource_mgmt_3
, num_ls_stack_entries
,
1695 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1698 BEGIN_BATCH_NO_AUTOSTATE(196);
1700 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
1702 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG
, 4);
1703 R600_OUT_BATCH(sq_config
);
1704 R600_OUT_BATCH(sq_gpr_resource_mgmt_1
);
1705 R600_OUT_BATCH(sq_gpr_resource_mgmt_2
);
1706 R600_OUT_BATCH(sq_gpr_resource_mgmt_3
);
1708 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT
, 5);
1709 R600_OUT_BATCH(sq_thread_resource_mgmt
);
1710 R600_OUT_BATCH(sq_thread_resource_mgmt_2
);
1711 R600_OUT_BATCH(sq_stack_resource_mgmt_1
);
1712 R600_OUT_BATCH(sq_stack_resource_mgmt_2
);
1713 R600_OUT_BATCH(sq_stack_resource_mgmt_3
);
1715 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL
, 1));
1716 R600_OUT_BATCH(0x80000000);
1717 R600_OUT_BATCH(0x80000000);
1719 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LDS_ALLOC_PS
, 0);
1721 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE
, 6);
1729 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE
, 4);
1735 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL
, 0);
1737 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL
, 5);
1738 R600_OUT_BATCH(0x00000060);
1741 R600_OUT_BATCH(0x0000002a);
1744 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR
, 2);
1748 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK
, 0x0000aa00);
1750 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_CLIPRECT_RULE
, 13);
1751 R600_OUT_BATCH(0x0000ffff);
1752 R600_OUT_BATCH(0x00000000);
1753 R600_OUT_BATCH(0x20002000);
1754 R600_OUT_BATCH(0x00000000);
1755 R600_OUT_BATCH(0x20002000);
1756 R600_OUT_BATCH(0x00000000);
1757 R600_OUT_BATCH(0x20002000);
1758 R600_OUT_BATCH(0x00000000);
1759 R600_OUT_BATCH(0x20002000);
1760 R600_OUT_BATCH(0xaaaaaaaa);
1762 R600_OUT_BATCH(0x0000000f);
1763 R600_OUT_BATCH(0x0000000f);
1765 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0
, 2);
1767 R600_OUT_BATCH(0x3f800000);
1769 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC
, 0);
1771 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0
, 2);
1775 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL
, 16);
1778 R600_OUT_BATCH(0x00000005);
1779 R600_OUT_BATCH(0x3f800000);
1780 R600_OUT_BATCH(0x3f800000);
1781 R600_OUT_BATCH(0x3f800000);
1782 R600_OUT_BATCH(0x3f800000);
1791 R600_OUT_BATCH(0xffffffff);
1793 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR_CONTROL
, 13);
1794 R600_OUT_BATCH(0x00cc0010);
1795 R600_OUT_BATCH(0x00000210);
1796 R600_OUT_BATCH(0x00010000);
1797 R600_OUT_BATCH(0x00000004);
1798 R600_OUT_BATCH(0x00000100);
1808 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, 6);
1816 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX
, 9);
1817 R600_OUT_BATCH(0x00ffffff);
1827 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0
, 2);
1831 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF
, 2);
1835 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE
, 17);
1838 R600_OUT_BATCH(0x00000008);
1854 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_PRIMITIVEID_EN
, 0);
1856 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_MULTI_PRIM_IB_RESET_EN
, 0);
1858 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN
, 0);
1860 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG
, 2);
1864 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL
, 0);
1866 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_CONFIG
, 0);
1868 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_ID_0
, 0);
1870 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_PS_INPUT_CNTL_0
, 0);
1872 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_IN_CONTROL_0
, 11);
1873 R600_OUT_BATCH(0x20000001);
1878 R600_OUT_BATCH(0x00100000);
1889 static GLboolean
eg_validate_buffers(context_t
*rmesa
,
1890 struct radeon_bo
*src_bo
,
1891 struct radeon_bo
*dst_bo
)
1895 radeon_cs_space_reset_bos(rmesa
->radeon
.cmdbuf
.cs
);
1897 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1898 src_bo
, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
1902 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1903 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
);
1907 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1909 RADEON_GEM_DOMAIN_GTT
, 0);
1916 unsigned evergreen_blit(struct gl_context
*ctx
,
1917 struct radeon_bo
*src_bo
,
1918 intptr_t src_offset
,
1919 gl_format src_mesaformat
,
1922 unsigned src_height
,
1925 struct radeon_bo
*dst_bo
,
1926 intptr_t dst_offset
,
1927 gl_format dst_mesaformat
,
1930 unsigned dst_height
,
1937 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1940 if (!evergreen_check_blit(dst_mesaformat
))
1943 if (src_bo
== dst_bo
) {
1947 if (src_offset
% 256 || dst_offset
% 256) {
1952 fprintf(stderr
, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1953 src_width
, src_height
, src_pitch
,
1954 _mesa_format_row_stride(src_mesaformat
, src_width
),
1955 _mesa_get_format_name(src_mesaformat
));
1956 fprintf(stderr
, "dst: width %d, height %d, pitch %d, format %s\n",
1957 dst_width
, dst_height
,
1958 _mesa_format_row_stride(dst_mesaformat
, dst_width
),
1959 _mesa_get_format_name(dst_mesaformat
));
1962 /* Flush is needed to make sure that source buffer has correct data */
1965 rcommonEnsureCmdBufSpace(&context
->radeon
, 327, __FUNCTION__
);
1968 eg_load_shaders(context
->radeon
.glCtx
);
1970 if (!eg_validate_buffers(context
, src_bo
, dst_bo
))
1973 /* set clear state */
1975 eg_set_default_state(context
);
1979 eg_set_shaders(context
);
1983 eg_set_tex_resource(context
, src_mesaformat
, src_bo
,
1984 src_width
, src_height
, src_pitch
, src_offset
);
1987 eg_set_tex_sampler(context
);
1991 eg_set_render_target(context
, dst_bo
, dst_mesaformat
,
1992 dst_pitch
, dst_width
, dst_height
, dst_offset
);
1995 eg_set_scissors(context
, dst_x
, dst_y
, dst_x
+ dst_width
, dst_y
+ dst_height
);
1997 eg_set_vb_data(context
, src_x
, src_y
, dst_x
, dst_y
, w
, h
, src_height
, flip_y
);
1998 /* Vertex buffer setup */
2000 eg_set_vtx_resource(context
);
2004 eg_draw_auto(context
);
2007 r700SyncSurf(context
, dst_bo
, 0,
2008 RADEON_GEM_DOMAIN_VRAM
|RADEON_GEM_DOMAIN_GTT
,
2009 CB_ACTION_ENA_bit
| (1 << (id
+ 6)));