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Merge branch 'lp-offset-twoside'
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_blit.c
1 /*
2 * Copyright (C) 2010 Advanced Micro Devices, Inc.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #include "radeon_common.h"
29 #include "r600_context.h"
30
31 #include "evergreen_off.h"
32 #include "evergreen_diff.h"
33
34 #include "evergreen_blit.h"
35 #include "evergreen_blit_shaders.h"
36 #include "r600_cmdbuf.h"
37
38 /* common formats supported as both textures and render targets */
39 unsigned evergreen_check_blit(gl_format mesa_format)
40 {
41 switch (mesa_format) {
42 case MESA_FORMAT_RGBA8888:
43 case MESA_FORMAT_SIGNED_RGBA8888:
44 case MESA_FORMAT_RGBA8888_REV:
45 case MESA_FORMAT_SIGNED_RGBA8888_REV:
46 case MESA_FORMAT_ARGB8888:
47 case MESA_FORMAT_XRGB8888:
48 case MESA_FORMAT_ARGB8888_REV:
49 case MESA_FORMAT_XRGB8888_REV:
50 case MESA_FORMAT_RGB565:
51 case MESA_FORMAT_RGB565_REV:
52 case MESA_FORMAT_ARGB4444:
53 case MESA_FORMAT_ARGB4444_REV:
54 case MESA_FORMAT_ARGB1555:
55 case MESA_FORMAT_ARGB1555_REV:
56 case MESA_FORMAT_AL88:
57 case MESA_FORMAT_AL88_REV:
58 case MESA_FORMAT_RGB332:
59 case MESA_FORMAT_A8:
60 case MESA_FORMAT_I8:
61 case MESA_FORMAT_CI8:
62 case MESA_FORMAT_L8:
63 case MESA_FORMAT_RGBA_FLOAT32:
64 case MESA_FORMAT_RGBA_FLOAT16:
65 case MESA_FORMAT_ALPHA_FLOAT32:
66 case MESA_FORMAT_ALPHA_FLOAT16:
67 case MESA_FORMAT_LUMINANCE_FLOAT32:
68 case MESA_FORMAT_LUMINANCE_FLOAT16:
69 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
70 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
71 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
72 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
73 case MESA_FORMAT_X8_Z24:
74 case MESA_FORMAT_S8_Z24:
75 case MESA_FORMAT_Z24_S8:
76 case MESA_FORMAT_Z16:
77 case MESA_FORMAT_Z32:
78 case MESA_FORMAT_SARGB8:
79 case MESA_FORMAT_SLA8:
80 case MESA_FORMAT_SL8:
81 break;
82 default:
83 return 0;
84 }
85
86 /* ??? */
87 /* not sure blit to depth works or not yet */
88 if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
89 return 0;
90
91 return 1;
92 }
93
94 static inline void
95 eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
96 int nPitchInPixel, int w, int h, intptr_t dst_offset)
97 {
98 uint32_t cb_color0_base, cb_color0_info = 0;
99 uint32_t cb_color0_pitch = 0, cb_color0_slice = 0, cb_color0_attrib = 0;
100 int id = 0;
101 uint32_t comp_swap, format, source_format, number_type;
102 BATCH_LOCALS(&context->radeon);
103
104 cb_color0_base = dst_offset / 256;
105
106 /* pitch */
107 SETfield(cb_color0_pitch, (nPitchInPixel / 8) - 1,
108 EG_CB_COLOR0_PITCH__TILE_MAX_shift,
109 EG_CB_COLOR0_PITCH__TILE_MAX_mask);
110
111 /* slice */
112 SETfield(cb_color0_slice,
113 ((nPitchInPixel * h) / 64) - 1,
114 EG_CB_COLOR0_SLICE__TILE_MAX_shift,
115 EG_CB_COLOR0_SLICE__TILE_MAX_mask);
116
117 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
118 SETbit(cb_color0_attrib,
119 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
120
121 SETfield(cb_color0_info,
122 ENDIAN_NONE,
123 EG_CB_COLOR0_INFO__ENDIAN_shift,
124 EG_CB_COLOR0_INFO__ENDIAN_mask);
125 SETfield(cb_color0_info,
126 ARRAY_LINEAR_GENERAL,
127 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
128 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
129
130 SETbit(cb_color0_info, EG_CB_COLOR0_INFO__BLEND_BYPASS_bit);
131
132 switch(mesa_format) {
133 case MESA_FORMAT_RGBA8888:
134 format = COLOR_8_8_8_8;
135 comp_swap = SWAP_STD_REV;
136 number_type = NUMBER_UNORM;
137 source_format = 1;
138 break;
139 case MESA_FORMAT_SIGNED_RGBA8888:
140 format = COLOR_8_8_8_8;
141 comp_swap = SWAP_STD_REV;
142 number_type = NUMBER_SNORM;
143 source_format = 1;
144 break;
145 case MESA_FORMAT_RGBA8888_REV:
146 format = COLOR_8_8_8_8;
147 comp_swap = SWAP_STD;
148 number_type = NUMBER_UNORM;
149 source_format = 1;
150 break;
151 case MESA_FORMAT_SIGNED_RGBA8888_REV:
152 format = COLOR_8_8_8_8;
153 comp_swap = SWAP_STD;
154 number_type = NUMBER_SNORM;
155 source_format = 1;
156 break;
157 case MESA_FORMAT_ARGB8888:
158 case MESA_FORMAT_XRGB8888:
159 format = COLOR_8_8_8_8;
160 comp_swap = SWAP_ALT;
161 number_type = NUMBER_UNORM;
162 source_format = 1;
163 break;
164 case MESA_FORMAT_ARGB8888_REV:
165 case MESA_FORMAT_XRGB8888_REV:
166 format = COLOR_8_8_8_8;
167 comp_swap = SWAP_ALT_REV;
168 number_type = NUMBER_UNORM;
169 source_format = 1;
170 break;
171 case MESA_FORMAT_RGB565:
172 format = COLOR_5_6_5;
173 comp_swap = SWAP_STD_REV;
174 number_type = NUMBER_UNORM;
175 source_format = 1;
176 break;
177 case MESA_FORMAT_RGB565_REV:
178 format = COLOR_5_6_5;
179 comp_swap = SWAP_STD;
180 number_type = NUMBER_UNORM;
181 source_format = 1;
182 break;
183 case MESA_FORMAT_ARGB4444:
184 format = COLOR_4_4_4_4;
185 comp_swap = SWAP_ALT;
186 number_type = NUMBER_UNORM;
187 source_format = 1;
188 break;
189 case MESA_FORMAT_ARGB4444_REV:
190 format = COLOR_4_4_4_4;
191 comp_swap = SWAP_ALT_REV;
192 number_type = NUMBER_UNORM;
193 source_format = 1;
194 break;
195 case MESA_FORMAT_ARGB1555:
196 format = COLOR_1_5_5_5;
197 comp_swap = SWAP_ALT;
198 number_type = NUMBER_UNORM;
199 source_format = 1;
200 break;
201 case MESA_FORMAT_ARGB1555_REV:
202 format = COLOR_1_5_5_5;
203 comp_swap = SWAP_ALT_REV;
204 number_type = NUMBER_UNORM;
205 source_format = 1;
206 break;
207 case MESA_FORMAT_AL88:
208 format = COLOR_8_8;
209 comp_swap = SWAP_STD;
210 number_type = NUMBER_UNORM;
211 source_format = 1;
212 break;
213 case MESA_FORMAT_AL88_REV:
214 format = COLOR_8_8;
215 comp_swap = SWAP_STD_REV;
216 number_type = NUMBER_UNORM;
217 source_format = 1;
218 break;
219 case MESA_FORMAT_RGB332:
220 format = COLOR_3_3_2;
221 comp_swap = SWAP_STD_REV;
222 number_type = NUMBER_UNORM;
223 source_format = 1;
224 break;
225 case MESA_FORMAT_A8:
226 format = COLOR_8;
227 comp_swap = SWAP_ALT_REV;
228 number_type = NUMBER_UNORM;
229 source_format = 1;
230 break;
231 case MESA_FORMAT_I8:
232 case MESA_FORMAT_CI8:
233 format = COLOR_8;
234 comp_swap = SWAP_STD;
235 number_type = NUMBER_UNORM;
236 source_format = 1;
237 break;
238 case MESA_FORMAT_L8:
239 format = COLOR_8;
240 comp_swap = SWAP_ALT;
241 number_type = NUMBER_UNORM;
242 source_format = 1;
243 break;
244 case MESA_FORMAT_RGBA_FLOAT32:
245 format = COLOR_32_32_32_32_FLOAT;
246 comp_swap = SWAP_STD;
247 number_type = NUMBER_FLOAT;
248 source_format = 0;
249 break;
250 case MESA_FORMAT_RGBA_FLOAT16:
251 format = COLOR_16_16_16_16_FLOAT;
252 comp_swap = SWAP_STD;
253 number_type = NUMBER_FLOAT;
254 source_format = 0;
255 break;
256 case MESA_FORMAT_ALPHA_FLOAT32:
257 format = COLOR_32_FLOAT;
258 comp_swap = SWAP_ALT_REV;
259 number_type = NUMBER_FLOAT;
260 source_format = 0;
261 break;
262 case MESA_FORMAT_ALPHA_FLOAT16:
263 format = COLOR_16_FLOAT;
264 comp_swap = SWAP_ALT_REV;
265 number_type = NUMBER_FLOAT;
266 source_format = 0;
267 break;
268 case MESA_FORMAT_LUMINANCE_FLOAT32:
269 format = COLOR_32_FLOAT;
270 comp_swap = SWAP_ALT;
271 number_type = NUMBER_FLOAT;
272 source_format = 0;
273 break;
274 case MESA_FORMAT_LUMINANCE_FLOAT16:
275 format = COLOR_16_FLOAT;
276 comp_swap = SWAP_ALT;
277 number_type = NUMBER_FLOAT;
278 source_format = 0;
279 break;
280 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
281 format = COLOR_32_32_FLOAT;
282 comp_swap = SWAP_ALT_REV;
283 number_type = NUMBER_FLOAT;
284 source_format = 0;
285 break;
286 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
287 format = COLOR_16_16_FLOAT;
288 comp_swap = SWAP_ALT_REV;
289 number_type = NUMBER_FLOAT;
290 source_format = 0;
291 break;
292 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
293 format = COLOR_32_FLOAT;
294 comp_swap = SWAP_STD;
295 number_type = NUMBER_FLOAT;
296 source_format = 0;
297 break;
298 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
299 format = COLOR_16_FLOAT;
300 comp_swap = SWAP_STD;
301 number_type = NUMBER_UNORM;
302 source_format = 0;
303 break;
304 case MESA_FORMAT_X8_Z24:
305 case MESA_FORMAT_S8_Z24:
306 format = COLOR_8_24;
307 comp_swap = SWAP_STD;
308 number_type = NUMBER_UNORM;
309 SETfield(cb_color0_info,
310 ARRAY_1D_TILED_THIN1,
311 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
312 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
313 source_format = 0;
314 break;
315 case MESA_FORMAT_Z24_S8:
316 format = COLOR_24_8;
317 comp_swap = SWAP_STD;
318 number_type = NUMBER_UNORM;
319 SETfield(cb_color0_info,
320 ARRAY_1D_TILED_THIN1,
321 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
322 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
323 source_format = 0;
324 break;
325 case MESA_FORMAT_Z16:
326 format = COLOR_16;
327 comp_swap = SWAP_STD;
328 number_type = NUMBER_UNORM;
329 SETfield(cb_color0_info,
330 ARRAY_1D_TILED_THIN1,
331 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
332 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
333 source_format = 0;
334 break;
335 case MESA_FORMAT_Z32:
336 format = COLOR_32;
337 comp_swap = SWAP_STD;
338 number_type = NUMBER_UNORM;
339 SETfield(cb_color0_info,
340 ARRAY_1D_TILED_THIN1,
341 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
342 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
343 source_format = 0;
344 break;
345 case MESA_FORMAT_SARGB8:
346 format = COLOR_8_8_8_8;
347 comp_swap = SWAP_ALT;
348 number_type = NUMBER_SRGB;
349 source_format = 1;
350 break;
351 case MESA_FORMAT_SLA8:
352 format = COLOR_8_8;
353 comp_swap = SWAP_ALT_REV;
354 number_type = NUMBER_SRGB;
355 source_format = 1;
356 break;
357 case MESA_FORMAT_SL8:
358 format = COLOR_8;
359 comp_swap = SWAP_ALT_REV;
360 number_type = NUMBER_SRGB;
361 source_format = 1;
362 break;
363 default:
364 fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
365 assert("Invalid format for US output\n");
366 return;
367 }
368
369 SETfield(cb_color0_info,
370 format,
371 EG_CB_COLOR0_INFO__FORMAT_shift,
372 EG_CB_COLOR0_INFO__FORMAT_mask);
373 SETfield(cb_color0_info,
374 comp_swap,
375 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
376 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
377 SETfield(cb_color0_info,
378 number_type,
379 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
380 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
381 SETfield(cb_color0_info,
382 source_format,
383 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
384 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
385
386 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
387 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
388 R600_OUT_BATCH(cb_color0_base);
389 R600_OUT_BATCH_RELOC(cb_color0_base,
390 bo,
391 cb_color0_base,
392 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
393 END_BATCH();
394
395 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
396 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, cb_color0_info);
397 R600_OUT_BATCH_RELOC(cb_color0_info,
398 bo,
399 cb_color0_info,
400 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
401 END_BATCH();
402
403 BEGIN_BATCH_NO_AUTOSTATE(5);
404 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
405 R600_OUT_BATCH(cb_color0_pitch);
406 R600_OUT_BATCH(cb_color0_slice);
407 R600_OUT_BATCH(0);
408 END_BATCH();
409
410 BEGIN_BATCH_NO_AUTOSTATE(4);
411 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2);
412 R600_OUT_BATCH(cb_color0_attrib);
413 R600_OUT_BATCH(0);
414 /*
415 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
416 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
417 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
418 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
419 */
420 END_BATCH();
421
422 COMMIT_BATCH();
423
424 }
425
426 static inline void eg_load_shaders(struct gl_context * ctx)
427 {
428
429 radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
430 context_t *context = EVERGREEN_CONTEXT(ctx);
431 int i, size;
432 uint32_t *shader;
433
434 if (context->blit_bo_loaded == 1)
435 return;
436
437 size = 4096;
438 context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
439 size, 256, RADEON_GEM_DOMAIN_GTT, 0);
440 radeon_bo_map(context->blit_bo, 1);
441 shader = context->blit_bo->ptr;
442
443 for(i=0; i<sizeof(evergreen_vs)/4; i++) {
444 shader[128+i] = evergreen_vs[i];
445 }
446 for(i=0; i<sizeof(evergreen_ps)/4; i++) {
447 shader[256+i] = evergreen_ps[i];
448 }
449
450 radeon_bo_unmap(context->blit_bo);
451 context->blit_bo_loaded = 1;
452
453 }
454
455 static inline void
456 eg_set_shaders(context_t *context)
457 {
458 struct radeon_bo * pbo = context->blit_bo;
459 uint32_t sq_pgm_start_fs = (512 >> 8);
460 uint32_t sq_pgm_resources_fs = 0;
461
462 uint32_t sq_pgm_start_vs = (512 >> 8);
463 uint32_t sq_pgm_resources_vs = (2 << NUM_GPRS_shift);
464
465 uint32_t sq_pgm_start_ps = (1024 >> 8);
466 uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
467 uint32_t sq_pgm_exports_ps = (1 << 1);
468 BATCH_LOCALS(&context->radeon);
469
470 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
471
472 /* FS */
473 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
474 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_FS, 1);
475 R600_OUT_BATCH(sq_pgm_start_fs);
476 R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
477 pbo,
478 sq_pgm_start_fs,
479 RADEON_GEM_DOMAIN_GTT, 0, 0);
480 END_BATCH();
481
482 BEGIN_BATCH_NO_AUTOSTATE(3);
483 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
484 END_BATCH();
485
486 /* VS */
487 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
488 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
489 R600_OUT_BATCH(sq_pgm_start_vs);
490 R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
491 pbo,
492 sq_pgm_start_vs,
493 RADEON_GEM_DOMAIN_GTT, 0, 0);
494 END_BATCH();
495
496 BEGIN_BATCH_NO_AUTOSTATE(4);
497 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
498 R600_OUT_BATCH(sq_pgm_resources_vs);
499 R600_OUT_BATCH(0);
500 END_BATCH();
501
502 /* PS */
503 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
504 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
505 R600_OUT_BATCH(sq_pgm_start_ps);
506 R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
507 pbo,
508 sq_pgm_start_ps,
509 RADEON_GEM_DOMAIN_GTT, 0, 0);
510 END_BATCH();
511
512 BEGIN_BATCH_NO_AUTOSTATE(5);
513 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
514 R600_OUT_BATCH(sq_pgm_resources_ps);
515 R600_OUT_BATCH(0);
516 R600_OUT_BATCH(sq_pgm_exports_ps);
517 END_BATCH();
518
519 COMMIT_BATCH();
520
521 }
522
523 static inline void
524 eg_set_vtx_resource(context_t *context)
525 {
526 struct radeon_bo *bo = context->blit_bo;
527 uint32_t sq_vtx_constant_word3 = 0;
528 BATCH_LOCALS(&context->radeon);
529
530 BEGIN_BATCH_NO_AUTOSTATE(6);
531 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
532 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
533 R600_OUT_BATCH(0);
534
535 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
536 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
537 R600_OUT_BATCH(0);
538 END_BATCH();
539
540 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR)
541 r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
542 else
543 r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
544
545 SETfield(sq_vtx_constant_word3, SQ_SEL_X,
546 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
547 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
548 SETfield(sq_vtx_constant_word3, SQ_SEL_Y,
549 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
550 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
551 SETfield(sq_vtx_constant_word3, SQ_SEL_Z,
552 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
553 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
554 SETfield(sq_vtx_constant_word3, SQ_SEL_W,
555 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
556 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
557
558 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
559
560 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
561 R600_OUT_BATCH(EG_SQ_FETCH_RESOURCE_VS_OFFSET * EG_FETCH_RESOURCE_STRIDE);
562 R600_OUT_BATCH(0);
563 R600_OUT_BATCH(48 - 1);
564 R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
565 R600_OUT_BATCH(sq_vtx_constant_word3);
566 R600_OUT_BATCH(0);
567 R600_OUT_BATCH(0);
568 R600_OUT_BATCH(0);
569 R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
570 R600_OUT_BATCH_RELOC(0,
571 bo,
572 0,
573 RADEON_GEM_DOMAIN_GTT, 0, 0);
574 END_BATCH();
575 COMMIT_BATCH();
576
577 }
578
579 static inline void
580 eg_set_tex_resource(context_t * context,
581 gl_format mesa_format, struct radeon_bo *bo, int w, int h,
582 int TexelPitch, intptr_t src_offset)
583 {
584 uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource7;
585
586 sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource7 = 0;
587 BATCH_LOCALS(&context->radeon);
588
589 SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
590 SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
591 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
592 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
593
594 switch (mesa_format) {
595 case MESA_FORMAT_RGBA8888:
596 case MESA_FORMAT_SIGNED_RGBA8888:
597 SETfield(sq_tex_resource7, FMT_8_8_8_8,
598 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
599 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
600 SETfield(sq_tex_resource4, SQ_SEL_W,
601 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
602 SETfield(sq_tex_resource4, SQ_SEL_Z,
603 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
604 SETfield(sq_tex_resource4, SQ_SEL_Y,
605 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
606 SETfield(sq_tex_resource4, SQ_SEL_X,
607 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
608 if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
609 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
610 FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
611 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
612 FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
613 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
614 FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
615 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
616 FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
617 }
618 break;
619 case MESA_FORMAT_RGBA8888_REV:
620 case MESA_FORMAT_SIGNED_RGBA8888_REV:
621 SETfield(sq_tex_resource7, FMT_8_8_8_8,
622 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
623 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
624 SETfield(sq_tex_resource4, SQ_SEL_X,
625 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
626 SETfield(sq_tex_resource4, SQ_SEL_Y,
627 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
628 SETfield(sq_tex_resource4, SQ_SEL_Z,
629 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
630 SETfield(sq_tex_resource4, SQ_SEL_W,
631 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
632 if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
633 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
634 FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
635 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
636 FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
637 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
638 FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
639 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
640 FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
641 }
642 break;
643 case MESA_FORMAT_ARGB8888:
644 SETfield(sq_tex_resource7, FMT_8_8_8_8,
645 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
646 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
647 SETfield(sq_tex_resource4, SQ_SEL_Z,
648 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
649 SETfield(sq_tex_resource4, SQ_SEL_Y,
650 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
651 SETfield(sq_tex_resource4, SQ_SEL_X,
652 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
653 SETfield(sq_tex_resource4, SQ_SEL_W,
654 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
655 break;
656 case MESA_FORMAT_XRGB8888:
657 SETfield(sq_tex_resource7, FMT_8_8_8_8,
658 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
659 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
660 SETfield(sq_tex_resource4, SQ_SEL_Z,
661 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
662 SETfield(sq_tex_resource4, SQ_SEL_Y,
663 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
664 SETfield(sq_tex_resource4, SQ_SEL_X,
665 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
666 SETfield(sq_tex_resource4, SQ_SEL_1,
667 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
668 break;
669 case MESA_FORMAT_ARGB8888_REV:
670 SETfield(sq_tex_resource7, FMT_8_8_8_8,
671 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
672 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
673 SETfield(sq_tex_resource4, SQ_SEL_Y,
674 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
675 SETfield(sq_tex_resource4, SQ_SEL_Z,
676 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
677 SETfield(sq_tex_resource4, SQ_SEL_W,
678 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
679 SETfield(sq_tex_resource4, SQ_SEL_X,
680 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
681 break;
682 case MESA_FORMAT_XRGB8888_REV:
683 SETfield(sq_tex_resource7, FMT_8_8_8_8,
684 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
685 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
686 SETfield(sq_tex_resource4, SQ_SEL_1,
687 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
688 SETfield(sq_tex_resource4, SQ_SEL_Z,
689 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
690 SETfield(sq_tex_resource4, SQ_SEL_W,
691 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
692 SETfield(sq_tex_resource4, SQ_SEL_X,
693 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
694 break;
695 case MESA_FORMAT_RGB565:
696 SETfield(sq_tex_resource7, FMT_5_6_5,
697 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
698 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
699 SETfield(sq_tex_resource4, SQ_SEL_Z,
700 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
701 SETfield(sq_tex_resource4, SQ_SEL_Y,
702 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
703 SETfield(sq_tex_resource4, SQ_SEL_X,
704 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
705 SETfield(sq_tex_resource4, SQ_SEL_1,
706 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
707 break;
708 case MESA_FORMAT_RGB565_REV:
709 SETfield(sq_tex_resource7, FMT_5_6_5,
710 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
711 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
712 SETfield(sq_tex_resource4, SQ_SEL_X,
713 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
714 SETfield(sq_tex_resource4, SQ_SEL_Y,
715 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
716 SETfield(sq_tex_resource4, SQ_SEL_Z,
717 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
718 SETfield(sq_tex_resource4, SQ_SEL_1,
719 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
720 break;
721 case MESA_FORMAT_ARGB4444:
722 SETfield(sq_tex_resource7, FMT_4_4_4_4,
723 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
724 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
725 SETfield(sq_tex_resource4, SQ_SEL_Z,
726 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
727 SETfield(sq_tex_resource4, SQ_SEL_Y,
728 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
729 SETfield(sq_tex_resource4, SQ_SEL_X,
730 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
731 SETfield(sq_tex_resource4, SQ_SEL_W,
732 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
733 break;
734 case MESA_FORMAT_ARGB4444_REV:
735 SETfield(sq_tex_resource7, FMT_4_4_4_4,
736 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
737 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
738 SETfield(sq_tex_resource4, SQ_SEL_Y,
739 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
740 SETfield(sq_tex_resource4, SQ_SEL_Z,
741 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
742 SETfield(sq_tex_resource4, SQ_SEL_W,
743 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
744 SETfield(sq_tex_resource4, SQ_SEL_X,
745 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
746 break;
747 case MESA_FORMAT_ARGB1555:
748 SETfield(sq_tex_resource7, FMT_1_5_5_5,
749 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
750 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
751 SETfield(sq_tex_resource4, SQ_SEL_Z,
752 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
753 SETfield(sq_tex_resource4, SQ_SEL_Y,
754 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
755 SETfield(sq_tex_resource4, SQ_SEL_X,
756 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
757 SETfield(sq_tex_resource4, SQ_SEL_W,
758 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
759 break;
760 case MESA_FORMAT_ARGB1555_REV:
761 SETfield(sq_tex_resource7, FMT_1_5_5_5,
762 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
763 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
764 SETfield(sq_tex_resource4, SQ_SEL_Y,
765 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
766 SETfield(sq_tex_resource4, SQ_SEL_Z,
767 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
768 SETfield(sq_tex_resource4, SQ_SEL_W,
769 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
770 SETfield(sq_tex_resource4, SQ_SEL_X,
771 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
772 break;
773 case MESA_FORMAT_AL88:
774 case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
775 SETfield(sq_tex_resource7, FMT_8_8,
776 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
777 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
778 SETfield(sq_tex_resource4, SQ_SEL_X,
779 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
780 SETfield(sq_tex_resource4, SQ_SEL_X,
781 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
782 SETfield(sq_tex_resource4, SQ_SEL_X,
783 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
784 SETfield(sq_tex_resource4, SQ_SEL_Y,
785 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
786 break;
787 case MESA_FORMAT_RGB332:
788 SETfield(sq_tex_resource7, FMT_3_3_2,
789 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
790 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
791 SETfield(sq_tex_resource4, SQ_SEL_Z,
792 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
793 SETfield(sq_tex_resource4, SQ_SEL_Y,
794 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
795 SETfield(sq_tex_resource4, SQ_SEL_X,
796 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
797 SETfield(sq_tex_resource4, SQ_SEL_1,
798 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
799 break;
800 case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
801 SETfield(sq_tex_resource7, FMT_8,
802 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
803 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
804 SETfield(sq_tex_resource4, SQ_SEL_0,
805 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
806 SETfield(sq_tex_resource4, SQ_SEL_0,
807 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
808 SETfield(sq_tex_resource4, SQ_SEL_0,
809 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
810 SETfield(sq_tex_resource4, SQ_SEL_X,
811 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
812 break;
813 case MESA_FORMAT_L8: /* X, X, X, ONE */
814 SETfield(sq_tex_resource7, FMT_8,
815 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
816 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
817 SETfield(sq_tex_resource4, SQ_SEL_X,
818 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
819 SETfield(sq_tex_resource4, SQ_SEL_X,
820 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
821 SETfield(sq_tex_resource4, SQ_SEL_X,
822 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
823 SETfield(sq_tex_resource4, SQ_SEL_1,
824 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
825 break;
826 case MESA_FORMAT_I8: /* X, X, X, X */
827 case MESA_FORMAT_CI8:
828 SETfield(sq_tex_resource7, FMT_8,
829 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
830 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
831 SETfield(sq_tex_resource4, SQ_SEL_X,
832 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
833 SETfield(sq_tex_resource4, SQ_SEL_X,
834 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
835 SETfield(sq_tex_resource4, SQ_SEL_X,
836 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
837 SETfield(sq_tex_resource4, SQ_SEL_X,
838 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
839 break;
840 case MESA_FORMAT_RGBA_FLOAT32:
841 SETfield(sq_tex_resource7, FMT_32_32_32_32_FLOAT,
842 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
843 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
844 SETfield(sq_tex_resource4, SQ_SEL_X,
845 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
846 SETfield(sq_tex_resource4, SQ_SEL_Y,
847 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
848 SETfield(sq_tex_resource4, SQ_SEL_Z,
849 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
850 SETfield(sq_tex_resource4, SQ_SEL_W,
851 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
852 break;
853 case MESA_FORMAT_RGBA_FLOAT16:
854 SETfield(sq_tex_resource7, FMT_16_16_16_16_FLOAT,
855 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
856 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
857 SETfield(sq_tex_resource4, SQ_SEL_X,
858 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
859 SETfield(sq_tex_resource4, SQ_SEL_Y,
860 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
861 SETfield(sq_tex_resource4, SQ_SEL_Z,
862 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
863 SETfield(sq_tex_resource4, SQ_SEL_W,
864 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
865 break;
866 case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
867 SETfield(sq_tex_resource7, FMT_32_FLOAT,
868 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
869 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
870 SETfield(sq_tex_resource4, SQ_SEL_0,
871 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
872 SETfield(sq_tex_resource4, SQ_SEL_0,
873 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
874 SETfield(sq_tex_resource4, SQ_SEL_0,
875 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
876 SETfield(sq_tex_resource4, SQ_SEL_X,
877 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
878 break;
879 case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
880 SETfield(sq_tex_resource7, FMT_16_FLOAT,
881 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
882 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
883 SETfield(sq_tex_resource4, SQ_SEL_0,
884 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
885 SETfield(sq_tex_resource4, SQ_SEL_0,
886 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
887 SETfield(sq_tex_resource4, SQ_SEL_0,
888 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
889 SETfield(sq_tex_resource4, SQ_SEL_X,
890 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
891 break;
892 case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
893 SETfield(sq_tex_resource7, FMT_32_FLOAT,
894 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
895 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
896 SETfield(sq_tex_resource4, SQ_SEL_X,
897 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
898 SETfield(sq_tex_resource4, SQ_SEL_X,
899 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
900 SETfield(sq_tex_resource4, SQ_SEL_X,
901 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
902 SETfield(sq_tex_resource4, SQ_SEL_1,
903 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
904 break;
905 case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
906 SETfield(sq_tex_resource7, FMT_16_FLOAT,
907 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
908 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
909 SETfield(sq_tex_resource4, SQ_SEL_X,
910 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
911 SETfield(sq_tex_resource4, SQ_SEL_X,
912 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
913 SETfield(sq_tex_resource4, SQ_SEL_X,
914 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
915 SETfield(sq_tex_resource4, SQ_SEL_1,
916 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
917 break;
918 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
919 SETfield(sq_tex_resource7, FMT_32_32_FLOAT,
920 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
921 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
922 SETfield(sq_tex_resource4, SQ_SEL_X,
923 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
924 SETfield(sq_tex_resource4, SQ_SEL_X,
925 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
926 SETfield(sq_tex_resource4, SQ_SEL_X,
927 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
928 SETfield(sq_tex_resource4, SQ_SEL_Y,
929 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
930 break;
931 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
932 SETfield(sq_tex_resource7, FMT_16_16_FLOAT,
933 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
934 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
935 SETfield(sq_tex_resource4, SQ_SEL_X,
936 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
937 SETfield(sq_tex_resource4, SQ_SEL_X,
938 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
939 SETfield(sq_tex_resource4, SQ_SEL_X,
940 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
941 SETfield(sq_tex_resource4, SQ_SEL_Y,
942 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
943 break;
944 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
945 SETfield(sq_tex_resource7, FMT_32_FLOAT,
946 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
947 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
948 SETfield(sq_tex_resource4, SQ_SEL_X,
949 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
950 SETfield(sq_tex_resource4, SQ_SEL_X,
951 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
952 SETfield(sq_tex_resource4, SQ_SEL_X,
953 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
954 SETfield(sq_tex_resource4, SQ_SEL_X,
955 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
956 break;
957 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
958 SETfield(sq_tex_resource7, FMT_16_FLOAT,
959 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
960 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
961 SETfield(sq_tex_resource4, SQ_SEL_X,
962 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
963 SETfield(sq_tex_resource4, SQ_SEL_X,
964 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
965 SETfield(sq_tex_resource4, SQ_SEL_X,
966 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
967 SETfield(sq_tex_resource4, SQ_SEL_X,
968 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
969 break;
970 case MESA_FORMAT_Z16:
971 /* ??? */
972 CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
973 SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
974 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
975 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
976 SETfield(sq_tex_resource7, FMT_16,
977 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
978 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
979 SETfield(sq_tex_resource4, SQ_SEL_X,
980 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
981 SETfield(sq_tex_resource4, SQ_SEL_X,
982 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
983 SETfield(sq_tex_resource4, SQ_SEL_X,
984 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
985 SETfield(sq_tex_resource4, SQ_SEL_X,
986 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
987 break;
988 case MESA_FORMAT_X8_Z24:
989 /* ??? */
990 CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
991 SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
992 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
993 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
994 SETfield(sq_tex_resource7, FMT_8_24,
995 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
996 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
997 SETfield(sq_tex_resource4, SQ_SEL_X,
998 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
999 SETfield(sq_tex_resource4, SQ_SEL_1,
1000 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1001 SETfield(sq_tex_resource4, SQ_SEL_0,
1002 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1003 SETfield(sq_tex_resource4, SQ_SEL_1,
1004 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1005 break;
1006 case MESA_FORMAT_S8_Z24:
1007 /* ??? */
1008 CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1009 SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1010 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1011 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1012 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1013 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1014 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1015 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1016 SETfield(sq_tex_resource7, FMT_8_24,
1017 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1018 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1019 SETfield(sq_tex_resource4, SQ_SEL_X,
1020 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1021 SETfield(sq_tex_resource4, SQ_SEL_Y,
1022 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1023 SETfield(sq_tex_resource4, SQ_SEL_0,
1024 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1025 SETfield(sq_tex_resource4, SQ_SEL_1,
1026 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1027 break;
1028 case MESA_FORMAT_Z24_S8:
1029 /* ??? */
1030 CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1031 SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1032 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1033 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1034 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1035 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1036 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1037 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1038 SETfield(sq_tex_resource7, FMT_24_8,
1039 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1040 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1041 SETfield(sq_tex_resource4, SQ_SEL_X,
1042 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1043 SETfield(sq_tex_resource4, SQ_SEL_Y,
1044 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1045 SETfield(sq_tex_resource4, SQ_SEL_0,
1046 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1047 SETfield(sq_tex_resource4, SQ_SEL_1,
1048 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1049 break;
1050 case MESA_FORMAT_Z32:
1051 /* ??? */
1052 CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1053 SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1054 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1055 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1056 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1057 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1058 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1059 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1060 SETfield(sq_tex_resource7, FMT_32,
1061 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1062 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1063 SETfield(sq_tex_resource4, SQ_SEL_X,
1064 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1065 SETfield(sq_tex_resource4, SQ_SEL_X,
1066 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1067 SETfield(sq_tex_resource4, SQ_SEL_X,
1068 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1069 SETfield(sq_tex_resource4, SQ_SEL_X,
1070 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1071 break;
1072 case MESA_FORMAT_S8:
1073 /* ??? */
1074 CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1075 SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1076 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1077 EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1078 SETfield(sq_tex_resource7, FMT_8,
1079 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1080 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1081 SETfield(sq_tex_resource4, SQ_SEL_X,
1082 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1083 SETfield(sq_tex_resource4, SQ_SEL_X,
1084 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1085 SETfield(sq_tex_resource4, SQ_SEL_X,
1086 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1087 SETfield(sq_tex_resource4, SQ_SEL_X,
1088 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1089 break;
1090 case MESA_FORMAT_SARGB8:
1091 SETfield(sq_tex_resource7, FMT_8_8_8_8,
1092 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1093 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1094 SETfield(sq_tex_resource4, SQ_SEL_Z,
1095 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1096 SETfield(sq_tex_resource4, SQ_SEL_Y,
1097 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1098 SETfield(sq_tex_resource4, SQ_SEL_X,
1099 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1100 SETfield(sq_tex_resource4, SQ_SEL_W,
1101 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1102 SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1103 break;
1104 case MESA_FORMAT_SLA8:
1105 SETfield(sq_tex_resource7, FMT_8_8,
1106 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1107 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1108 SETfield(sq_tex_resource4, SQ_SEL_X,
1109 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1110 SETfield(sq_tex_resource4, SQ_SEL_X,
1111 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1112 SETfield(sq_tex_resource4, SQ_SEL_X,
1113 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1114 SETfield(sq_tex_resource4, SQ_SEL_Y,
1115 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1116 SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1117 break;
1118 case MESA_FORMAT_SL8: /* X, X, X, ONE */
1119 SETfield(sq_tex_resource7, FMT_8,
1120 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1121 EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1122 SETfield(sq_tex_resource4, SQ_SEL_X,
1123 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1124 SETfield(sq_tex_resource4, SQ_SEL_X,
1125 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1126 SETfield(sq_tex_resource4, SQ_SEL_X,
1127 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1128 SETfield(sq_tex_resource4, SQ_SEL_1,
1129 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1130 SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1131 break;
1132 default:
1133 fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
1134 assert("Invalid format for US output\n");
1135 return;
1136 };
1137
1138 SETfield(sq_tex_resource0, (TexelPitch/8)-1,
1139 EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift,
1140 EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask);
1141 SETfield(sq_tex_resource0, w - 1,
1142 EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift,
1143 EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask);
1144 SETfield(sq_tex_resource1, h - 1,
1145 EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift,
1146 EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask);
1147
1148 sq_tex_resource2 = src_offset / 256;
1149
1150 SETfield(sq_tex_resource7, SQ_TEX_VTX_VALID_TEXTURE,
1151 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
1152 SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
1153
1154 r700SyncSurf(context, bo,
1155 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
1156 0, TC_ACTION_ENA_bit);
1157
1158 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
1159 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
1160 R600_OUT_BATCH(0 * 7);
1161 R600_OUT_BATCH(sq_tex_resource0);
1162 R600_OUT_BATCH(sq_tex_resource1);
1163 R600_OUT_BATCH(sq_tex_resource2);
1164 R600_OUT_BATCH(0);
1165 R600_OUT_BATCH(sq_tex_resource4);
1166 R600_OUT_BATCH(0);
1167 R600_OUT_BATCH(0);
1168 R600_OUT_BATCH(sq_tex_resource7);
1169 R600_OUT_BATCH_RELOC(0,
1170 bo,
1171 0,
1172 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1173 R600_OUT_BATCH_RELOC(0,
1174 bo,
1175 0,
1176 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1177 END_BATCH();
1178 COMMIT_BATCH();
1179 }
1180
1181 static inline void
1182 eg_set_tex_sampler(context_t * context)
1183 {
1184 uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
1185 int i = 0;
1186
1187 SETbit(sq_tex_sampler_word2, EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
1188
1189 BATCH_LOCALS(&context->radeon);
1190
1191 BEGIN_BATCH_NO_AUTOSTATE(5);
1192 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
1193 R600_OUT_BATCH(i * 3);
1194 R600_OUT_BATCH(sq_tex_sampler_word0);
1195 R600_OUT_BATCH(sq_tex_sampler_word1);
1196 R600_OUT_BATCH(sq_tex_sampler_word2);
1197 END_BATCH();
1198
1199 }
1200
1201 static inline void
1202 eg_set_scissors(context_t *context, int x1, int y1, int x2, int y2)
1203 {
1204 BATCH_LOCALS(&context->radeon);
1205
1206 BEGIN_BATCH_NO_AUTOSTATE(17);
1207 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
1208 R600_OUT_BATCH((x1 << 0) | (y1 << 16));
1209 R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1210
1211 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 3);
1212 R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1213 R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
1214 R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1215
1216 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
1217 R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1218 R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1219
1220 /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1221 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 2);
1222 R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1223 R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1224 END_BATCH();
1225
1226 COMMIT_BATCH();
1227
1228 }
1229
1230 static inline void
1231 eg_set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
1232 int w, int h, int src_h, unsigned flip_y)
1233 {
1234 float *vb;
1235 radeon_bo_map(context->blit_bo, 1);
1236 vb = context->blit_bo->ptr;
1237
1238 vb[0] = (float)(dst_x);
1239 vb[1] = (float)(dst_y);
1240 vb[2] = (float)(src_x);
1241 vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
1242
1243 vb[4] = (float)(dst_x);
1244 vb[5] = (float)(dst_y + h);
1245 vb[6] = (float)(src_x);
1246 vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1247
1248 vb[8] = (float)(dst_x + w);
1249 vb[9] = (float)(dst_y + h);
1250 vb[10] = (float)(src_x + w);
1251 vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1252
1253 radeon_bo_unmap(context->blit_bo);
1254
1255 }
1256
1257 static inline void
1258 eg_draw_auto(context_t *context)
1259 {
1260 BATCH_LOCALS(&context->radeon);
1261 uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
1262
1263 SETfield(vgt_primitive_type, DI_PT_RECTLIST,
1264 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
1265 VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
1266 SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
1267 INDEX_TYPE_mask);
1268 SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
1269 MAJOR_MODE_mask);
1270 SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
1271 SOURCE_SELECT_mask);
1272
1273 vgt_num_indices = 3;
1274
1275 BEGIN_BATCH_NO_AUTOSTATE(10);
1276 // prim
1277 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVE_TYPE, 1);
1278 R600_OUT_BATCH(vgt_primitive_type);
1279 // index type
1280 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1281 R600_OUT_BATCH(vgt_index_type);
1282 // num instances
1283 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1284 R600_OUT_BATCH(1);
1285 //
1286 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1287 R600_OUT_BATCH(vgt_num_indices);
1288 R600_OUT_BATCH(vgt_draw_initiator);
1289
1290 END_BATCH();
1291 COMMIT_BATCH();
1292 }
1293
1294 static inline void
1295 eg_set_default_state(context_t *context)
1296 {
1297 int num_ps_gprs;
1298 int num_vs_gprs;
1299 int num_gs_gprs;
1300 int num_es_gprs;
1301 int num_hs_gprs;
1302 int num_ls_gprs;
1303 int num_temp_gprs;
1304 int num_ps_threads;
1305 int num_vs_threads;
1306 int num_gs_threads;
1307 int num_es_threads;
1308 int num_hs_threads;
1309 int num_ls_threads;
1310 int num_ps_stack_entries;
1311 int num_vs_stack_entries;
1312 int num_gs_stack_entries;
1313 int num_es_stack_entries;
1314 int num_hs_stack_entries;
1315 int num_ls_stack_entries;
1316 uint32_t sq_config = 0, sq_gpr_resource_mgmt_1 = 0, sq_gpr_resource_mgmt_2 = 0;
1317 uint32_t sq_gpr_resource_mgmt_3 = 0;
1318 uint32_t sq_thread_resource_mgmt = 0, sq_thread_resource_mgmt_2 = 0;
1319 uint32_t sq_stack_resource_mgmt_1 = 0, sq_stack_resource_mgmt_2 = 0, sq_stack_resource_mgmt_3 = 0;
1320 BATCH_LOCALS(&context->radeon);
1321
1322 switch (context->radeon.radeonScreen->chip_family) {
1323 case CHIP_FAMILY_CEDAR:
1324 default:
1325 num_ps_gprs = 93;
1326 num_vs_gprs = 46;
1327 num_temp_gprs = 4;
1328 num_gs_gprs = 31;
1329 num_es_gprs = 31;
1330 num_hs_gprs = 23;
1331 num_ls_gprs = 23;
1332 num_ps_threads = 96;
1333 num_vs_threads = 16;
1334 num_gs_threads = 16;
1335 num_es_threads = 16;
1336 num_hs_threads = 16;
1337 num_ls_threads = 16;
1338 num_ps_stack_entries = 42;
1339 num_vs_stack_entries = 42;
1340 num_gs_stack_entries = 42;
1341 num_es_stack_entries = 42;
1342 num_hs_stack_entries = 42;
1343 num_ls_stack_entries = 42;
1344 break;
1345 case CHIP_FAMILY_REDWOOD:
1346 num_ps_gprs = 93;
1347 num_vs_gprs = 46;
1348 num_temp_gprs = 4;
1349 num_gs_gprs = 31;
1350 num_es_gprs = 31;
1351 num_hs_gprs = 23;
1352 num_ls_gprs = 23;
1353 num_ps_threads = 128;
1354 num_vs_threads = 20;
1355 num_gs_threads = 20;
1356 num_es_threads = 20;
1357 num_hs_threads = 20;
1358 num_ls_threads = 20;
1359 num_ps_stack_entries = 42;
1360 num_vs_stack_entries = 42;
1361 num_gs_stack_entries = 42;
1362 num_es_stack_entries = 42;
1363 num_hs_stack_entries = 42;
1364 num_ls_stack_entries = 42;
1365 break;
1366 case CHIP_FAMILY_JUNIPER:
1367 num_ps_gprs = 93;
1368 num_vs_gprs = 46;
1369 num_temp_gprs = 4;
1370 num_gs_gprs = 31;
1371 num_es_gprs = 31;
1372 num_hs_gprs = 23;
1373 num_ls_gprs = 23;
1374 num_ps_threads = 128;
1375 num_vs_threads = 20;
1376 num_gs_threads = 20;
1377 num_es_threads = 20;
1378 num_hs_threads = 20;
1379 num_ls_threads = 20;
1380 num_ps_stack_entries = 85;
1381 num_vs_stack_entries = 85;
1382 num_gs_stack_entries = 85;
1383 num_es_stack_entries = 85;
1384 num_hs_stack_entries = 85;
1385 num_ls_stack_entries = 85;
1386 break;
1387 case CHIP_FAMILY_CYPRESS:
1388 case CHIP_FAMILY_HEMLOCK:
1389 num_ps_gprs = 93;
1390 num_vs_gprs = 46;
1391 num_temp_gprs = 4;
1392 num_gs_gprs = 31;
1393 num_es_gprs = 31;
1394 num_hs_gprs = 23;
1395 num_ls_gprs = 23;
1396 num_ps_threads = 128;
1397 num_vs_threads = 20;
1398 num_gs_threads = 20;
1399 num_es_threads = 20;
1400 num_hs_threads = 20;
1401 num_ls_threads = 20;
1402 num_ps_stack_entries = 85;
1403 num_vs_stack_entries = 85;
1404 num_gs_stack_entries = 85;
1405 num_es_stack_entries = 85;
1406 num_hs_stack_entries = 85;
1407 num_ls_stack_entries = 85;
1408 break;
1409 }
1410
1411 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR)
1412 CLEARbit(sq_config, EG_SQ_CONFIG__VC_ENABLE_bit);
1413 else
1414 SETbit(sq_config, EG_SQ_CONFIG__VC_ENABLE_bit);
1415 SETbit(sq_config, EG_SQ_CONFIG__EXPORT_SRC_C_bit);
1416
1417 SETfield(sq_config, 0,
1418 EG_SQ_CONFIG__PS_PRIO_shift,
1419 EG_SQ_CONFIG__PS_PRIO_mask);
1420 SETfield(sq_config, 1,
1421 EG_SQ_CONFIG__VS_PRIO_shift,
1422 EG_SQ_CONFIG__VS_PRIO_mask);
1423 SETfield(sq_config, 2,
1424 EG_SQ_CONFIG__GS_PRIO_shift,
1425 EG_SQ_CONFIG__GS_PRIO_mask);
1426 SETfield(sq_config, 3,
1427 EG_SQ_CONFIG__ES_PRIO_shift,
1428 EG_SQ_CONFIG__ES_PRIO_mask);
1429
1430
1431 SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs,
1432 NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1433 SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs,
1434 NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1435 SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
1436 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1437 SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs,
1438 NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1439 SETfield(sq_gpr_resource_mgmt_2, num_es_gprs,
1440 NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1441 SETfield(sq_gpr_resource_mgmt_3, num_hs_gprs,
1442 NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1443 SETfield(sq_gpr_resource_mgmt_3, num_ls_gprs,
1444 NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1445
1446 SETfield(sq_thread_resource_mgmt, num_ps_threads,
1447 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1448 SETfield(sq_thread_resource_mgmt, num_vs_threads,
1449 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1450 SETfield(sq_thread_resource_mgmt, num_gs_threads,
1451 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1452 SETfield(sq_thread_resource_mgmt, num_es_threads,
1453 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1454 SETfield(sq_thread_resource_mgmt_2, num_hs_threads,
1455 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1456 SETfield(sq_thread_resource_mgmt_2, num_ls_threads,
1457 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1458
1459 SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
1460 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1461 SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
1462 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1463 SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
1464 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1465 SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
1466 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1467 SETfield(sq_stack_resource_mgmt_3, num_hs_stack_entries,
1468 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1469 SETfield(sq_stack_resource_mgmt_3, num_ls_stack_entries,
1470 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1471
1472
1473 BEGIN_BATCH_NO_AUTOSTATE(196);
1474 //3
1475 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1476 //6
1477 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
1478 R600_OUT_BATCH(sq_config);
1479 R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
1480 R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
1481 R600_OUT_BATCH(sq_gpr_resource_mgmt_3);
1482 //7
1483 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
1484 R600_OUT_BATCH(sq_thread_resource_mgmt);
1485 R600_OUT_BATCH(sq_thread_resource_mgmt_2);
1486 R600_OUT_BATCH(sq_stack_resource_mgmt_1);
1487 R600_OUT_BATCH(sq_stack_resource_mgmt_2);
1488 R600_OUT_BATCH(sq_stack_resource_mgmt_3);
1489 //3
1490 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
1491 R600_OUT_BATCH(0x80000000);
1492 R600_OUT_BATCH(0x80000000);
1493 //3
1494 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LDS_ALLOC_PS, 0);
1495 //8
1496 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
1497 R600_OUT_BATCH(0);
1498 R600_OUT_BATCH(0);
1499 R600_OUT_BATCH(0);
1500 R600_OUT_BATCH(0);
1501 R600_OUT_BATCH(0);
1502 R600_OUT_BATCH(0);
1503 //6
1504 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 4);
1505 R600_OUT_BATCH(0);
1506 R600_OUT_BATCH(0);
1507 R600_OUT_BATCH(0);
1508 R600_OUT_BATCH(0);
1509 //3
1510 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, 0);
1511 //7
1512 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
1513 R600_OUT_BATCH(0x00000060);
1514 R600_OUT_BATCH(0);
1515 R600_OUT_BATCH(0);
1516 R600_OUT_BATCH(0x0000002a);
1517 R600_OUT_BATCH(0);
1518 //4
1519 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
1520 R600_OUT_BATCH(0);
1521 R600_OUT_BATCH(0);
1522 //3
1523 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, 0x0000aa00);
1524 //15
1525 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_CLIPRECT_RULE, 13);
1526 R600_OUT_BATCH(0x0000ffff);
1527 R600_OUT_BATCH(0x00000000);
1528 R600_OUT_BATCH(0x20002000);
1529 R600_OUT_BATCH(0x00000000);
1530 R600_OUT_BATCH(0x20002000);
1531 R600_OUT_BATCH(0x00000000);
1532 R600_OUT_BATCH(0x20002000);
1533 R600_OUT_BATCH(0x00000000);
1534 R600_OUT_BATCH(0x20002000);
1535 R600_OUT_BATCH(0xaaaaaaaa);
1536 R600_OUT_BATCH(0);
1537 R600_OUT_BATCH(0x0000000f);
1538 R600_OUT_BATCH(0x0000000f);
1539 //4
1540 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
1541 R600_OUT_BATCH(0);
1542 R600_OUT_BATCH(0x3f800000);
1543 //3
1544 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, 0);
1545 //4
1546 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
1547 R600_OUT_BATCH(0);
1548 R600_OUT_BATCH(0);
1549 //18
1550 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
1551 R600_OUT_BATCH(0);
1552 R600_OUT_BATCH(0);
1553 R600_OUT_BATCH(0x00000005);
1554 R600_OUT_BATCH(0x3f800000);
1555 R600_OUT_BATCH(0x3f800000);
1556 R600_OUT_BATCH(0x3f800000);
1557 R600_OUT_BATCH(0x3f800000);
1558 R600_OUT_BATCH(0);
1559 R600_OUT_BATCH(0);
1560 R600_OUT_BATCH(0);
1561 R600_OUT_BATCH(0);
1562 R600_OUT_BATCH(0);
1563 R600_OUT_BATCH(0);
1564 R600_OUT_BATCH(0);
1565 R600_OUT_BATCH(0);
1566 R600_OUT_BATCH(0xffffffff);
1567 //15
1568 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR_CONTROL, 13);
1569 R600_OUT_BATCH(0x00cc0010);
1570 R600_OUT_BATCH(0x00000210);
1571 R600_OUT_BATCH(0x00010000);
1572 R600_OUT_BATCH(0x00000004);
1573 R600_OUT_BATCH(0x00000100);
1574 R600_OUT_BATCH(0);
1575 R600_OUT_BATCH(0);
1576 R600_OUT_BATCH(0);
1577 R600_OUT_BATCH(0);
1578 R600_OUT_BATCH(0);
1579 R600_OUT_BATCH(0);
1580 R600_OUT_BATCH(0);
1581 R600_OUT_BATCH(0);
1582 //8
1583 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
1584 R600_OUT_BATCH(0);
1585 R600_OUT_BATCH(0);
1586 R600_OUT_BATCH(0);
1587 R600_OUT_BATCH(0);
1588 R600_OUT_BATCH(0);
1589 R600_OUT_BATCH(0);
1590 //11
1591 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 9);
1592 R600_OUT_BATCH(0x00ffffff);
1593 R600_OUT_BATCH(0);
1594 R600_OUT_BATCH(0);
1595 R600_OUT_BATCH(0);
1596 R600_OUT_BATCH(0);
1597 R600_OUT_BATCH(0);
1598 R600_OUT_BATCH(0);
1599 R600_OUT_BATCH(0);
1600 R600_OUT_BATCH(0);
1601 //4
1602 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1603 R600_OUT_BATCH(0);
1604 R600_OUT_BATCH(0);
1605 //4
1606 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1607 R600_OUT_BATCH(0);
1608 R600_OUT_BATCH(0);
1609 //19
1610 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 17);
1611 R600_OUT_BATCH(0);
1612 R600_OUT_BATCH(0);
1613 R600_OUT_BATCH(0x00000008);
1614 R600_OUT_BATCH(0);
1615 R600_OUT_BATCH(0);
1616 R600_OUT_BATCH(0);
1617 R600_OUT_BATCH(0);
1618 R600_OUT_BATCH(0);
1619 R600_OUT_BATCH(0);
1620 R600_OUT_BATCH(0);
1621 R600_OUT_BATCH(0);
1622 R600_OUT_BATCH(0);
1623 R600_OUT_BATCH(0);
1624 R600_OUT_BATCH(0);
1625 R600_OUT_BATCH(0);
1626 R600_OUT_BATCH(0);
1627 R600_OUT_BATCH(0);
1628 //3
1629 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_PRIMITIVEID_EN, 0);
1630 //3
1631 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_MULTI_PRIM_IB_RESET_EN, 0);
1632 //3
1633 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, 0);
1634 //4
1635 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1636 R600_OUT_BATCH(0);
1637 R600_OUT_BATCH(0);
1638 //3
1639 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, 0);
1640 //3
1641 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_CONFIG, 0);
1642 //3
1643 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_ID_0, 0);
1644 //3
1645 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_PS_INPUT_CNTL_0, 0);
1646 //13
1647 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_IN_CONTROL_0, 11);
1648 R600_OUT_BATCH(0x20000001);
1649 R600_OUT_BATCH(0);
1650 R600_OUT_BATCH(0);
1651 R600_OUT_BATCH(0);
1652 R600_OUT_BATCH(0);
1653 R600_OUT_BATCH(0x00100000);
1654 R600_OUT_BATCH(0);
1655 R600_OUT_BATCH(0);
1656 R600_OUT_BATCH(0);
1657 R600_OUT_BATCH(0);
1658 R600_OUT_BATCH(0);
1659
1660 END_BATCH();
1661 COMMIT_BATCH();
1662 }
1663
1664 static GLboolean eg_validate_buffers(context_t *rmesa,
1665 struct radeon_bo *src_bo,
1666 struct radeon_bo *dst_bo)
1667 {
1668 int ret;
1669
1670 radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
1671
1672 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1673 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
1674 if (ret)
1675 return GL_FALSE;
1676
1677 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1678 dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
1679 if (ret)
1680 return GL_FALSE;
1681
1682 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1683 rmesa->blit_bo,
1684 RADEON_GEM_DOMAIN_GTT, 0);
1685 if (ret)
1686 return GL_FALSE;
1687
1688 return GL_TRUE;
1689 }
1690
1691 unsigned evergreen_blit(struct gl_context *ctx,
1692 struct radeon_bo *src_bo,
1693 intptr_t src_offset,
1694 gl_format src_mesaformat,
1695 unsigned src_pitch,
1696 unsigned src_width,
1697 unsigned src_height,
1698 unsigned src_x,
1699 unsigned src_y,
1700 struct radeon_bo *dst_bo,
1701 intptr_t dst_offset,
1702 gl_format dst_mesaformat,
1703 unsigned dst_pitch,
1704 unsigned dst_width,
1705 unsigned dst_height,
1706 unsigned dst_x,
1707 unsigned dst_y,
1708 unsigned w,
1709 unsigned h,
1710 unsigned flip_y)
1711 {
1712 context_t *context = EVERGREEN_CONTEXT(ctx);
1713 int id = 0;
1714
1715 if (!evergreen_check_blit(dst_mesaformat))
1716 return GL_FALSE;
1717
1718 if (src_bo == dst_bo) {
1719 return GL_FALSE;
1720 }
1721
1722 if (src_offset % 256 || dst_offset % 256) {
1723 return GL_FALSE;
1724 }
1725
1726 if (0) {
1727 fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1728 src_width, src_height, src_pitch,
1729 _mesa_format_row_stride(src_mesaformat, src_width),
1730 _mesa_get_format_name(src_mesaformat));
1731 fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
1732 dst_width, dst_height,
1733 _mesa_format_row_stride(dst_mesaformat, dst_width),
1734 _mesa_get_format_name(dst_mesaformat));
1735 }
1736
1737 /* Flush is needed to make sure that source buffer has correct data */
1738 radeonFlush(ctx);
1739
1740 rcommonEnsureCmdBufSpace(&context->radeon, 327, __FUNCTION__);
1741
1742 /* load shaders */
1743 eg_load_shaders(context->radeon.glCtx);
1744
1745 if (!eg_validate_buffers(context, src_bo, dst_bo))
1746 return GL_FALSE;
1747
1748 /* set clear state */
1749 /* 196 */
1750 eg_set_default_state(context);
1751
1752 /* shaders */
1753 /* 34 */
1754 eg_set_shaders(context);
1755
1756 /* src */
1757 /* 21 */
1758 eg_set_tex_resource(context, src_mesaformat, src_bo,
1759 src_width, src_height, src_pitch, src_offset);
1760
1761 /* 5 */
1762 eg_set_tex_sampler(context);
1763
1764 /* dst */
1765 /* 19 */
1766 eg_set_render_target(context, dst_bo, dst_mesaformat,
1767 dst_pitch, dst_width, dst_height, dst_offset);
1768 /* scissors */
1769 /* 17 */
1770 eg_set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
1771
1772 eg_set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
1773 /* Vertex buffer setup */
1774 /* 18 */
1775 eg_set_vtx_resource(context);
1776
1777 /* draw */
1778 /* 10 */
1779 eg_draw_auto(context);
1780
1781 /* 7 */
1782 r700SyncSurf(context, dst_bo, 0,
1783 RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
1784 CB_ACTION_ENA_bit | (1 << (id + 6)));
1785
1786 radeonFlush(ctx);
1787
1788 return GL_TRUE;
1789 }