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intel: Add implementation of MapTextureImage/UnmapTextureImage.
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_chip.c
1 /*
2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/imports.h"
28 #include "main/glheader.h"
29 #include "main/simple_list.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "evergreen_chip.h"
35 #include "evergreen_off.h"
36 #include "evergreen_diff.h"
37 #include "evergreen_fragprog.h"
38 #include "evergreen_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 void evergreenCreateChip(context_t *context)
43 {
44 EVERGREEN_CHIP_CONTEXT * evergreen =
45 (EVERGREEN_CHIP_CONTEXT*) CALLOC(sizeof(EVERGREEN_CHIP_CONTEXT));
46
47 context->pChip = (void*)evergreen;
48 }
49
50 #define EVERGREEN_ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
51 do { \
52 context->evergreen_atoms.ATOM.cmd_size = (SZ); \
53 context->evergreen_atoms.ATOM.cmd = NULL; \
54 context->evergreen_atoms.ATOM.name = #ATOM; \
55 context->evergreen_atoms.ATOM.idx = 0; \
56 context->evergreen_atoms.ATOM.check = check_##CHK; \
57 context->evergreen_atoms.ATOM.dirty = GL_FALSE; \
58 context->evergreen_atoms.ATOM.emit = (EMIT); \
59 context->radeon.hw.max_state_size += (SZ); \
60 insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
61 } while (0)
62
63 static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom)
64 {
65 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
66 struct radeon_query_object *query = radeon->query.current;
67 int count;
68
69 if (!query || query->emitted_begin)
70 count = 0;
71 else
72 count = atom->cmd_size;
73 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
74 return count;
75 }
76
77 static void evergreenSendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom)
78 {
79 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
80 struct radeon_query_object *query = radeon->query.current;
81 BATCH_LOCALS(radeon);
82 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
83
84 /* clear the buffer */
85 radeon_bo_map(query->bo, GL_FALSE);
86 memset(query->bo->ptr, 0, 8 * 2 * sizeof(uint64_t)); /* 8 DBs, 2 qwords each */
87 radeon_bo_unmap(query->bo);
88
89 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
90 query->bo,
91 0, RADEON_GEM_DOMAIN_GTT);
92
93 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
94 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
95 R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
96 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
97 R600_OUT_BATCH(0x00000000);
98 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
99 END_BATCH();
100 query->emitted_begin = GL_TRUE;
101 }
102
103 static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
104 {
105 radeon->query.queryobj.cmd_size = (SZ);
106 radeon->query.queryobj.cmd = NULL;
107 radeon->query.queryobj.name = "queryobj";
108 radeon->query.queryobj.idx = 0;
109 radeon->query.queryobj.check = check_queryobj;
110 radeon->query.queryobj.dirty = GL_FALSE;
111 radeon->query.queryobj.emit = evergreenSendQueryBegin;
112 radeon->hw.max_state_size += (SZ);
113 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
114 }
115
116
117 static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
118 {
119 return atom->cmd_size;
120 }
121
122 static void evergreenSendTexState(struct gl_context *ctx, struct radeon_state_atom *atom)
123 {
124 context_t *context = EVERGREEN_CONTEXT(ctx);
125 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
126
127 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
128
129 struct radeon_bo *bo = NULL;
130 unsigned int i;
131 unsigned int nBorderSet = 0;
132 BATCH_LOCALS(&context->radeon);
133
134 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
135
136 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
137 if (ctx->Texture.Unit[i]._ReallyEnabled) {
138 radeonTexObj *t = evergreen->textures[i];
139
140 if (t) {
141 /* Tex resource */
142 if (!t->image_override) {
143 bo = t->mt->bo;
144 } else {
145 bo = t->bo;
146 }
147 if (bo)
148 {
149
150 r700SyncSurf(context, bo,
151 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
152 0, TC_ACTION_ENA_bit);
153
154 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
155 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
156
157 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
158 { /* vs texture */
159 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
160 }
161 else
162 {
163 R600_OUT_BATCH(i * EG_FETCH_RESOURCE_STRIDE);
164 }
165
166 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE0);
167 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE1);
168 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE2);
169 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE3);
170 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE4);
171 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE5);
172 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE6);
173 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE7);
174
175 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE2,
176 bo,
177 evergreen->textures[i]->SQ_TEX_RESOURCE2,
178 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
179 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE3,
180 bo,
181 evergreen->textures[i]->SQ_TEX_RESOURCE3,
182 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
183 END_BATCH();
184 COMMIT_BATCH();
185 }
186 /* Tex sampler */
187 BEGIN_BATCH_NO_AUTOSTATE(5);
188 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
189
190 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
191 { /* vs texture */
192 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * 3);
193 }
194 else
195 {
196 R600_OUT_BATCH(i * 3);
197 }
198 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER0);
199 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER1);
200 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER2);
201
202 END_BATCH();
203 COMMIT_BATCH();
204
205 /* Tex border color */
206 if(0 == nBorderSet)
207 {
208 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
209 R600_OUT_BATCH_REGSEQ(EG_TD_PS_BORDER_COLOR_RED, 4);
210 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
211 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
212 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
213 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
214 END_BATCH();
215 COMMIT_BATCH();
216
217 nBorderSet = 1;
218 }
219 }
220 }
221 }
222 }
223
224 static int check_evergreen_tx(struct gl_context *ctx, struct radeon_state_atom *atom)
225 {
226 context_t *context = EVERGREEN_CONTEXT(ctx);
227 unsigned int i, count = 0;
228 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
229
230 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
231 if (ctx->Texture.Unit[i]._ReallyEnabled) {
232 radeonTexObj *t = evergreen->textures[i];
233 if (t)
234 count++;
235 }
236 }
237 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
238 return count * 37 + 6;
239 }
240
241 static void evergreenSendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom)
242 {
243 context_t *context = EVERGREEN_CONTEXT(ctx);
244 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
245 BATCH_LOCALS(&context->radeon);
246 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
247
248 BEGIN_BATCH_NO_AUTOSTATE(19);
249 //6
250 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL, evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All);
251 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL_1, evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All);
252 //6
253 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
254 R600_OUT_BATCH(evergreen->evergreen_config.SQ_CONFIG.u32All);
255 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
256 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
257 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All);
258 //7
259 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
260 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All);
261 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All);
262 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
263 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
264 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All);
265
266 END_BATCH();
267
268 COMMIT_BATCH();
269 }
270
271 extern int evergreen_getTypeSize(GLenum type);
272 static void evergreenSetupVTXConstants(struct gl_context * ctx,
273 void * pAos,
274 StreamDesc * pStreamDesc)
275 {
276 context_t *context = EVERGREEN_CONTEXT(ctx);
277 struct radeon_aos * paos = (struct radeon_aos *)pAos;
278 BATCH_LOCALS(&context->radeon);
279
280 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
281 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
282 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
283 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
284 unsigned int uSQ_VTX_CONSTANT_WORD7_0 = 0;
285
286 if (!paos->bo)
287 return;
288
289 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) ||
290 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_PALM) ||
291 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_SUMO) ||
292 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_SUMO2))
293 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
294 else
295 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
296
297 //uSQ_VTX_CONSTANT_WORD0_0
298 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
299
300 //uSQ_VTX_CONSTANT_WORD1_0
301 uSQ_VTX_CONSTANT_WORD1_0 = paos->bo->size - paos->offset - 1;
302
303 //uSQ_VTX_CONSTANT_WORD2_0
304 SETfield(uSQ_VTX_CONSTANT_WORD2_0,
305 pStreamDesc->stride,
306 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
307 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
308 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
309 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
310 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
311 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
312
313 SETfield(uSQ_VTX_CONSTANT_WORD2_0,
314 #ifdef MESA_BIG_ENDIAN
315 SQ_ENDIAN_8IN32,
316 #else
317 SQ_ENDIAN_NONE,
318 #endif
319 SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift,
320 SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask);
321
322 if(GL_TRUE == pStreamDesc->normalize)
323 {
324 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
325 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
326 }
327 else
328 {
329 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
330 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
331 }
332 if(1 == pStreamDesc->_signed)
333 {
334 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
335 }
336
337 //uSQ_VTX_CONSTANT_WORD3_0
338 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_X,
339 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
340 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
341 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Y,
342 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
343 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
344 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Z,
345 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
346 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
347 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_W,
348 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
349 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
350
351 //uSQ_VTX_CONSTANT_WORD7_0
352 SETfield(uSQ_VTX_CONSTANT_WORD7_0, SQ_TEX_VTX_VALID_BUFFER,
353 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
354
355 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
356
357 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
358 R600_OUT_BATCH((pStreamDesc->element + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
359 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
360 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
361 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
362 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
363 R600_OUT_BATCH(0);
364 R600_OUT_BATCH(0);
365 R600_OUT_BATCH(0);
366 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD7_0);
367 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
368 paos->bo,
369 uSQ_VTX_CONSTANT_WORD0_0,
370 RADEON_GEM_DOMAIN_GTT, 0, 0);
371 END_BATCH();
372
373 COMMIT_BATCH();
374 }
375
376 static int check_evergreen_vtx(struct gl_context *ctx, struct radeon_state_atom *atom)
377 {
378 context_t *context = EVERGREEN_CONTEXT(ctx);
379 int count = context->radeon.tcl.aos_count * 12;
380
381 if (count)
382 count += 6;
383
384 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
385 return count;
386 }
387
388 static void evergreenSendVTX(struct gl_context *ctx, struct radeon_state_atom *atom)
389 {
390 context_t *context = EVERGREEN_CONTEXT(ctx);
391 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
392 unsigned int i, j = 0;
393 BATCH_LOCALS(&context->radeon);
394 (void) b_l_rmesa; /* silence unused var warning */
395
396 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
397
398 if (context->radeon.tcl.aos_count == 0)
399 return;
400
401 for(i=0; i<VERT_ATTRIB_MAX; i++) {
402 if(vp->mesa_program->Base.InputsRead & (1 << i))
403 {
404 evergreenSetupVTXConstants(ctx,
405 (void*)(&context->radeon.tcl.aos[j]),
406 &(context->stream_desc[j]));
407 j++;
408 }
409 }
410 }
411 static void evergreenSendPA(struct gl_context *ctx, struct radeon_state_atom *atom)
412 {
413 context_t *context = EVERGREEN_CONTEXT(ctx);
414 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
415 BATCH_LOCALS(&context->radeon);
416 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
417 int id = 0;
418
419 BEGIN_BATCH_NO_AUTOSTATE(3);
420 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
421 END_BATCH();
422
423 BEGIN_BATCH_NO_AUTOSTATE(22);
424 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
425 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All);
426 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All);
427
428 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 12);
429 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_OFFSET.u32All);
430 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All);
431 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All);
432 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_RULE.u32All);
433 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_TL.u32All);
434 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_BR.u32All);
435 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_TL.u32All);
436 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_BR.u32All);
437 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_TL.u32All);
438 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_BR.u32All);
439 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_TL.u32All);
440 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_BR.u32All);
441
442 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
443 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All);
444 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All);
445 END_BATCH();
446
447 BEGIN_BATCH_NO_AUTOSTATE(3);
448 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SC_EDGERULE, evergreen->PA_SC_EDGERULE.u32All);
449 END_BATCH();
450
451
452 BEGIN_BATCH_NO_AUTOSTATE(18);
453 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 4);
454 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
455 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
456 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
457 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
458
459 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
460 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
461 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
462
463 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_VPORT_XSCALE, 6);
464 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XSCALE.u32All);
465 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
466 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YSCALE.u32All);
467 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
468 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
469 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
470 END_BATCH();
471
472
473 for (id = 0; id < EVERGREEN_MAX_UCP; id++) {
474 if (evergreen->ucp[id].enabled) {
475 BEGIN_BATCH_NO_AUTOSTATE(6);
476 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_UCP_0_X + (4 * id), 4);
477 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_X.u32All);
478 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Y.u32All);
479 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Z.u32All);
480 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_W.u32All);
481 END_BATCH();
482 }
483 }
484
485 BEGIN_BATCH_NO_AUTOSTATE(42);
486 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_CLIP_CNTL, 5);
487 R600_OUT_BATCH(evergreen->PA_CL_CLIP_CNTL.u32All);
488 R600_OUT_BATCH(evergreen->PA_SU_SC_MODE_CNTL.u32All);
489 R600_OUT_BATCH(evergreen->PA_CL_VTE_CNTL.u32All);
490 R600_OUT_BATCH(evergreen->PA_CL_VS_OUT_CNTL.u32All);
491 R600_OUT_BATCH(evergreen->PA_CL_NANINF_CNTL.u32All);
492
493 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 3);
494 R600_OUT_BATCH(evergreen->PA_SU_POINT_SIZE.u32All);
495 R600_OUT_BATCH(evergreen->PA_SU_POINT_MINMAX.u32All);
496 R600_OUT_BATCH(evergreen->PA_SU_LINE_CNTL.u32All);
497
498 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
499 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_0.u32All);
500 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_1.u32All);
501
502 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
503 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
504 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_CLAMP.u32All);
505 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
506 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
507 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
508 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
509
510 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
511 R600_OUT_BATCH(evergreen->PA_SC_LINE_CNTL.u32All);
512 R600_OUT_BATCH(evergreen->PA_SC_AA_CONFIG.u32All);
513 R600_OUT_BATCH(evergreen->PA_SU_VTX_CNTL.u32All);
514 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All);
515 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All);
516 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
517 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All);
518 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_0.u32All);
519 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_1.u32All);
520 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_2.u32All);
521 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_3.u32All);
522 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_4.u32All);
523 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_5.u32All);
524 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_6.u32All);
525 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_7.u32All);
526 R600_OUT_BATCH(evergreen->PA_SC_AA_MASK.u32All);
527
528 END_BATCH();
529
530 COMMIT_BATCH();
531 }
532 static void evergreenSendTP(struct gl_context *ctx, struct radeon_state_atom *atom)
533 {
534 /*
535 context_t *context = EVERGREEN_CONTEXT(ctx);
536 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
537 BATCH_LOCALS(&context->radeon);
538 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
539
540 COMMIT_BATCH();
541 */
542 }
543
544 static void evergreenSendPSresource(struct gl_context *ctx)
545 {
546 context_t *context = EVERGREEN_CONTEXT(ctx);
547 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
548 struct radeon_bo * pbo;
549 struct radeon_bo * pbo_const;
550 /* const size reg is in units of 16 consts */
551 int const_size = ((evergreen->ps.num_consts * 4) + 15) & ~15;
552
553 BATCH_LOCALS(&context->radeon);
554 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
555
556 pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(GL_CONTEXT(context));
557
558 if (!pbo)
559 return;
560
561 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
562
563 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
564 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
565 R600_OUT_BATCH(evergreen->ps.SQ_PGM_START_PS.u32All);
566 R600_OUT_BATCH_RELOC(evergreen->ps.SQ_PGM_START_PS.u32All,
567 pbo,
568 evergreen->ps.SQ_PGM_START_PS.u32All,
569 RADEON_GEM_DOMAIN_GTT, 0, 0);
570 END_BATCH();
571
572 BEGIN_BATCH_NO_AUTOSTATE(3);
573 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LOOP_CONST_0, 0x01000FFF);
574 END_BATCH();
575
576 pbo_const = (struct radeon_bo *)(context->fp_Constbo);
577
578 if(NULL != pbo_const)
579 {
580 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
581
582 BEGIN_BATCH_NO_AUTOSTATE(3);
583 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, const_size / 16);
584 END_BATCH();
585
586 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
587 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_PS_0, 1);
588 R600_OUT_BATCH(context->fp_bo_offset >> 8);
589 R600_OUT_BATCH_RELOC(0,
590 pbo_const,
591 0,
592 RADEON_GEM_DOMAIN_GTT, 0, 0);
593 END_BATCH();
594 }
595
596 COMMIT_BATCH();
597 }
598
599 static void evergreenSendVSresource(struct gl_context *ctx, struct radeon_state_atom *atom)
600 {
601 context_t *context = EVERGREEN_CONTEXT(ctx);
602 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
603 struct radeon_bo * pbo;
604 struct radeon_bo * pbo_const;
605 /* const size reg is in units of 16 consts */
606 int const_size = ((evergreen->vs.num_consts * 4) + 15) & ~15;
607
608 BATCH_LOCALS(&context->radeon);
609 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
610
611 pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(GL_CONTEXT(context));
612
613 if (!pbo)
614 return;
615
616 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
617
618 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
619 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
620 R600_OUT_BATCH(evergreen->vs.SQ_PGM_START_VS.u32All);
621 R600_OUT_BATCH_RELOC(evergreen->vs.SQ_PGM_START_VS.u32All,
622 pbo,
623 evergreen->vs.SQ_PGM_START_VS.u32All,
624 RADEON_GEM_DOMAIN_GTT, 0, 0);
625 END_BATCH();
626
627 BEGIN_BATCH_NO_AUTOSTATE(3);
628 EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + 32*1), 0x0100000F); //consts == 1
629 //EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
630 END_BATCH();
631
632 pbo_const = (struct radeon_bo *)(context->vp_Constbo);
633
634 if(NULL != pbo_const)
635 {
636 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
637
638 BEGIN_BATCH_NO_AUTOSTATE(3);
639 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, const_size / 16);
640 END_BATCH();
641
642 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
643 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_VS_0, 1);
644 R600_OUT_BATCH(context->vp_bo_offset >> 8);
645 R600_OUT_BATCH_RELOC(0,
646 pbo_const,
647 0,
648 RADEON_GEM_DOMAIN_GTT, 0, 0);
649 END_BATCH();
650 }
651
652 COMMIT_BATCH();
653 }
654
655 static void evergreenSendSQ(struct gl_context *ctx, struct radeon_state_atom *atom)
656 {
657 context_t *context = EVERGREEN_CONTEXT(ctx);
658 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
659 BATCH_LOCALS(&context->radeon);
660 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
661
662 evergreenSendPSresource(ctx); //16 entries now
663
664 BEGIN_BATCH_NO_AUTOSTATE(77);
665
666 //34
667 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_VTX_SEMANTIC_0, 32);
668 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_0.u32All); //// // = 0x28380, // SAME
669 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_1.u32All); //// // = 0x28384, // SAME
670 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_2.u32All); //// // = 0x28388, // SAME
671 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_3.u32All); //// // = 0x2838C, // SAME
672 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_4.u32All); //// // = 0x28390, // SAME
673 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_5.u32All); //// // = 0x28394, // SAME
674 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_6.u32All); //// // = 0x28398, // SAME
675 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_7.u32All); //// // = 0x2839C, // SAME
676 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_8.u32All); //// // = 0x283A0, // SAME
677 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_9.u32All); //// // = 0x283A4, // SAME
678 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_10.u32All); //// // = 0x283A8, // SAME
679 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_11.u32All); //// // = 0x283AC, // SAME
680 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_12.u32All); //// // = 0x283B0, // SAME
681 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_13.u32All); //// // = 0x283B4, // SAME
682 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_14.u32All); //// // = 0x283B8, // SAME
683 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_15.u32All); //// // = 0x283BC, // SAME
684 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_16.u32All); //// // = 0x283C0, // SAME
685 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_17.u32All); //// // = 0x283C4, // SAME
686 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_18.u32All); //// // = 0x283C8, // SAME
687 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_19.u32All); //// // = 0x283CC, // SAME
688 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_20.u32All); //// // = 0x283D0, // SAME
689 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_21.u32All); //// // = 0x283D4, // SAME
690 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_22.u32All); //// // = 0x283D8, // SAME
691 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_23.u32All); //// // = 0x283DC, // SAME
692 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_24.u32All); //// // = 0x283E0, // SAME
693 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_25.u32All); //// // = 0x283E4, // SAME
694 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_26.u32All); //// // = 0x283E8, // SAME
695 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_27.u32All); //// // = 0x283EC, // SAME
696 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_28.u32All); //// // = 0x283F0, // SAME
697 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_29.u32All); //// // = 0x283F4, // SAME
698 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_30.u32All); //// // = 0x283F8, // SAME
699 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_31.u32All); //// // = 0x283FC, // SAME
700
701
702 //3
703 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_DYN_GPR_RESOURCE_LIMIT_1, 1);
704 R600_OUT_BATCH(evergreen->SQ_DYN_GPR_RESOURCE_LIMIT_1.u32All);//// // = 0x28838, //
705
706 //5
707 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
708 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_PS.u32All); //// // = 0x28844, // DIFF 0x28850
709 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_PS.u32All); //// // = 0x28848, //
710 R600_OUT_BATCH(evergreen->SQ_PGM_EXPORTS_PS.u32All); //// // = 0x2884C, // SAME 0x28854
711
712 //4
713 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
714 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_VS.u32All);//// // = 0x28860, // DIFF 0x28868
715 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_VS.u32All); //// // = 0x28864, //
716
717 //5
718 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_GS, 2);
719 /*
720 R600_OUT_BATCH(evergreen->SQ_PGM_START_GS.u32All); //// // = 0x28874, // SAME 0x2886C
721 */
722 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_GS.u32All); //// // = 0x28878, // DIFF 0x2887C
723 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_GS.u32All); //// // = 0x2887C, //
724
725 //5
726 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_ES, 2);
727 /*
728 R600_OUT_BATCH(evergreen->SQ_PGM_START_ES.u32All); //// // = 0x2888C, // SAME 0x28880
729 */
730 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_ES.u32All); //// // = 0x28890, // DIFF
731 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_ES.u32All); //// // = 0x28894, //
732
733 //4
734 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_FS, 1);
735 /*
736 R600_OUT_BATCH(evergreen->SQ_PGM_START_FS.u32All); //// // = 0x288A4, // SAME 0x28894
737 */
738 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_FS.u32All); //// // = 0x288A8, // DIFF 0x288A4
739
740 //3
741 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_HS, 1);
742 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_HS.u32All);//// // = 0x288C0, //
743
744 //3
745 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_LS, 1);
746 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_LS.u32All); //// // = 0x288D8, //
747
748 //3
749 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_LDS_ALLOC_PS, 1);
750 R600_OUT_BATCH(evergreen->SQ_LDS_ALLOC_PS.u32All); //// // = 0x288EC, //
751
752 //8
753 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
754 R600_OUT_BATCH(evergreen->SQ_ESGS_RING_ITEMSIZE.u32All); //// // = 0x28900, // SAME 0x288A8
755 R600_OUT_BATCH(evergreen->SQ_GSVS_RING_ITEMSIZE.u32All); //// // = 0x28904, // SAME 0x288AC
756 R600_OUT_BATCH(evergreen->SQ_ESTMP_RING_ITEMSIZE.u32All); //// // = 0x28908, // SAME 0x288B0
757 R600_OUT_BATCH(evergreen->SQ_GSTMP_RING_ITEMSIZE.u32All); //// // = 0x2890C, // SAME 0x288B4
758 R600_OUT_BATCH(evergreen->SQ_VSTMP_RING_ITEMSIZE.u32All); //// // = 0x28910, // SAME 0x288B8
759 R600_OUT_BATCH(evergreen->SQ_PSTMP_RING_ITEMSIZE.u32All); //// // = 0x28914, // SAME 0x288BC
760
761 //3
762 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 1);
763 R600_OUT_BATCH(evergreen->SQ_GS_VERT_ITEMSIZE.u32All); //// // = 0x2891C, // SAME 0x288C8
764
765 END_BATCH();
766
767 COMMIT_BATCH();
768
769 }
770 static void evergreenSendSPI(struct gl_context *ctx, struct radeon_state_atom *atom)
771 {
772 context_t *context = EVERGREEN_CONTEXT(ctx);
773 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
774 BATCH_LOCALS(&context->radeon);
775 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
776
777 BEGIN_BATCH_NO_AUTOSTATE(59);
778
779 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_VS_OUT_ID_0, 10);
780 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_0.u32All);
781 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_1.u32All);
782 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_2.u32All);
783 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_3.u32All);
784 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_4.u32All);
785 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_5.u32All);
786 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_6.u32All);
787 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_7.u32All);
788 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_8.u32All);
789 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_9.u32All);
790
791 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_INPUT_CNTL_0, 45);
792 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[0].u32All);
793 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[1].u32All);
794 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[2].u32All);
795 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[3].u32All);
796 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[4].u32All);
797 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[5].u32All);
798 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[6].u32All);
799 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[7].u32All);
800 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[8].u32All);
801 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[9].u32All);
802 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[10].u32All);
803 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[11].u32All);
804 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[12].u32All);
805 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[13].u32All);
806 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[14].u32All);
807 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[15].u32All);
808 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[16].u32All);
809 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[17].u32All);
810 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[18].u32All);
811 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[19].u32All);
812 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[20].u32All);
813 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[21].u32All);
814 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[22].u32All);
815 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[23].u32All);
816 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[24].u32All);
817 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[25].u32All);
818 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[26].u32All);
819 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[27].u32All);
820 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[28].u32All);
821 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[29].u32All);
822 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[30].u32All);
823 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[31].u32All);
824 R600_OUT_BATCH(evergreen->SPI_VS_OUT_CONFIG.u32All);
825 R600_OUT_BATCH(evergreen->SPI_THREAD_GROUPING.u32All);
826 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_0.u32All);
827 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_1.u32All);
828 R600_OUT_BATCH(evergreen->SPI_INTERP_CONTROL_0.u32All);
829 R600_OUT_BATCH(evergreen->SPI_INPUT_Z.u32All);
830 R600_OUT_BATCH(evergreen->SPI_FOG_CNTL.u32All);
831 R600_OUT_BATCH(evergreen->SPI_BARYC_CNTL.u32All);
832 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_2.u32All);
833 R600_OUT_BATCH(evergreen->SPI_COMPUTE_INPUT_CNTL.u32All);
834 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_X.u32All);
835 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Y.u32All);
836 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Z.u32All);
837
838 END_BATCH();
839
840 COMMIT_BATCH();
841 }
842 static void evergreenSendSX(struct gl_context *ctx, struct radeon_state_atom *atom)
843 {
844 context_t *context = EVERGREEN_CONTEXT(ctx);
845 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
846 BATCH_LOCALS(&context->radeon);
847 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
848
849 BEGIN_BATCH_NO_AUTOSTATE(9);
850
851 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, evergreen->SX_MISC.u32All);
852 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_TEST_CONTROL, evergreen->SX_ALPHA_TEST_CONTROL.u32All);
853 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_REF, evergreen->SX_ALPHA_REF.u32All);
854
855 END_BATCH();
856
857 COMMIT_BATCH();
858 }
859
860 static void evergreenSetDepthTarget(context_t *context)
861 {
862 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
863 struct radeon_renderbuffer *rrb;
864 unsigned int nPitchInPixel, height, offtostencil;
865
866 rrb = radeon_get_depthbuffer(&context->radeon);
867 if (!rrb)
868 {
869 return;
870 }
871
872 EVERGREEN_STATECHANGE(context, db);
873
874 evergreen->DB_DEPTH_SIZE.u32All = 0;
875
876 nPitchInPixel = rrb->pitch/rrb->cpp;
877
878 if (context->radeon.radeonScreen->driScreen->dri2.enabled)
879 {
880 height = rrb->base.Height;
881 }
882 else
883 {
884 height = context->radeon.radeonScreen->driScreen->fbHeight;
885 }
886
887 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
888 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift,
889 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask);
890 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (height/8)-1,
891 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift,
892 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask);
893 evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * height)/64 )-1;
894
895 if(4 == rrb->cpp)
896 {
897 SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_24,
898 EG_DB_Z_INFO__FORMAT_shift,
899 EG_DB_Z_INFO__FORMAT_mask);
900 }
901 else
902 {
903 SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_16,
904 EG_DB_Z_INFO__FORMAT_shift,
905 EG_DB_Z_INFO__FORMAT_mask);
906 }
907 SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
908 EG_DB_Z_INFO__ARRAY_MODE_shift,
909 EG_DB_Z_INFO__ARRAY_MODE_mask);
910
911
912 offtostencil = ((height * rrb->pitch) + 255) & ~255;
913 evergreen->DB_STENCIL_WRITE_BASE.u32All = offtostencil >> 8;
914 evergreen->DB_STENCIL_READ_BASE.u32All = offtostencil >> 8;
915
916 }
917
918 static void evergreenSendDB(struct gl_context *ctx, struct radeon_state_atom *atom)
919 {
920 context_t *context = EVERGREEN_CONTEXT(ctx);
921 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
922 struct radeon_renderbuffer *rrb;
923 BATCH_LOCALS(&context->radeon);
924 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
925
926 evergreenSetDepthTarget(context);
927
928 //8
929 BEGIN_BATCH_NO_AUTOSTATE(7);
930 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
931 R600_OUT_BATCH(evergreen->DB_RENDER_CONTROL.u32All);
932 R600_OUT_BATCH(evergreen->DB_COUNT_CONTROL.u32All);
933 R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All);
934 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All);
935 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All);
936 END_BATCH();
937
938 //4
939 BEGIN_BATCH_NO_AUTOSTATE(4);
940 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
941 R600_OUT_BATCH(evergreen->DB_STENCIL_CLEAR.u32All);
942 R600_OUT_BATCH(evergreen->DB_DEPTH_CLEAR.u32All);
943 END_BATCH();
944
945 //4
946 BEGIN_BATCH_NO_AUTOSTATE(4);
947 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_DEPTH_SIZE, 2);
948 R600_OUT_BATCH(evergreen->DB_DEPTH_SIZE.u32All);
949 R600_OUT_BATCH(evergreen->DB_DEPTH_SLICE.u32All);
950 END_BATCH();
951
952 //3
953 BEGIN_BATCH_NO_AUTOSTATE(3);
954 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, evergreen->DB_DEPTH_CONTROL.u32All);
955 END_BATCH();
956
957 //3
958 BEGIN_BATCH_NO_AUTOSTATE(3);
959 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_SHADER_CONTROL, evergreen->DB_SHADER_CONTROL.u32All);
960 END_BATCH();
961
962 //5
963 BEGIN_BATCH_NO_AUTOSTATE(5);
964 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_SRESULTS_COMPARE_STATE0, 3);
965 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE0.u32All);
966 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE1.u32All);
967 R600_OUT_BATCH(evergreen->DB_PRELOAD_CONTROL.u32All);
968 END_BATCH();
969
970 //3
971 BEGIN_BATCH_NO_AUTOSTATE(3);
972 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, evergreen->DB_ALPHA_TO_MASK.u32All);
973 END_BATCH();
974
975 rrb = radeon_get_depthbuffer(&context->radeon);
976
977 if( (rrb != NULL) && (rrb->bo != NULL) )
978 {
979
980 /* make the hw happy */
981 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
982 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All);
983 R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All,
984 rrb->bo,
985 evergreen->DB_HTILE_DATA_BASE.u32All,
986 0, RADEON_GEM_DOMAIN_VRAM, 0);
987 END_BATCH();
988
989 //5
990 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
991 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All);
992 R600_OUT_BATCH_RELOC(evergreen->DB_Z_INFO.u32All,
993 rrb->bo,
994 evergreen->DB_Z_INFO.u32All,
995 0, RADEON_GEM_DOMAIN_VRAM, 0);
996 END_BATCH();
997
998 //5
999 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_ENABLE_bit) > 0)
1000 {
1001 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1002 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_READ_BASE, evergreen->DB_Z_READ_BASE.u32All);
1003 R600_OUT_BATCH_RELOC(evergreen->DB_Z_READ_BASE.u32All,
1004 rrb->bo,
1005 evergreen->DB_Z_READ_BASE.u32All,
1006 0, RADEON_GEM_DOMAIN_VRAM, 0);
1007 END_BATCH();
1008 }
1009 //5
1010 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_WRITE_ENABLE_bit) > 0)
1011 {
1012 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1013 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_WRITE_BASE, evergreen->DB_Z_READ_BASE.u32All);
1014 R600_OUT_BATCH_RELOC(evergreen->DB_Z_WRITE_BASE.u32All,
1015 rrb->bo,
1016 evergreen->DB_Z_WRITE_BASE.u32All,
1017 0, RADEON_GEM_DOMAIN_VRAM, 0);
1018 END_BATCH();
1019 }
1020 }
1021
1022 if (ctx->DrawBuffer)
1023 {
1024 rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
1025
1026 if((rrb != NULL) && (rrb->bo != NULL))
1027 {
1028 //5
1029 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1030 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_STENCIL_INFO.u32All);
1031 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All,
1032 rrb->bo,
1033 evergreen->DB_STENCIL_INFO.u32All,
1034 0, RADEON_GEM_DOMAIN_VRAM, 0);
1035 END_BATCH();
1036
1037 //4
1038 BEGIN_BATCH_NO_AUTOSTATE(4);
1039 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
1040 R600_OUT_BATCH(evergreen->DB_STENCILREFMASK.u32All);
1041 R600_OUT_BATCH(evergreen->DB_STENCILREFMASK_BF.u32All);
1042 END_BATCH();
1043 //------------------------
1044
1045 //10
1046 if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
1047 {
1048
1049 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1050 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
1051 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
1052 rrb->bo,
1053 evergreen->DB_STENCIL_READ_BASE.u32All,
1054 0, RADEON_GEM_DOMAIN_VRAM, 0);
1055 END_BATCH();
1056
1057 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1058 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
1059 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
1060 rrb->bo,
1061 evergreen->DB_STENCIL_WRITE_BASE.u32All,
1062 0, RADEON_GEM_DOMAIN_VRAM, 0);
1063 END_BATCH();
1064 }
1065 }
1066 }
1067
1068 COMMIT_BATCH();
1069 }
1070
1071 static void evergreenSetRenderTarget(context_t *context, int id)
1072 {
1073 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1074 uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM, source_format = 1;
1075 struct radeon_renderbuffer *rrb;
1076 unsigned int nPitchInPixel, height;
1077
1078 rrb = radeon_get_colorbuffer(&context->radeon);
1079 if (!rrb || !rrb->bo) {
1080 return;
1081 }
1082
1083 EVERGREEN_STATECHANGE(context, cb);
1084
1085 /* addr */
1086 evergreen->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
1087
1088 /* pitch */
1089 nPitchInPixel = rrb->pitch/rrb->cpp;
1090
1091 if (context->radeon.radeonScreen->driScreen->dri2.enabled)
1092 {
1093 height = rrb->base.Height;
1094 }
1095 else
1096 {
1097 height = context->radeon.radeonScreen->driScreen->fbHeight;
1098 }
1099
1100 SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1,
1101 EG_CB_COLOR0_PITCH__TILE_MAX_shift,
1102 EG_CB_COLOR0_PITCH__TILE_MAX_mask);
1103
1104 /* slice */
1105 SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All,
1106 ( (nPitchInPixel * height)/64 )-1,
1107 EG_CB_COLOR0_SLICE__TILE_MAX_shift,
1108 EG_CB_COLOR0_SLICE__TILE_MAX_mask);
1109
1110 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
1111 SETbit(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All,
1112 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
1113
1114 /* CB_COLOR0_INFO */
1115 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1116 ENDIAN_NONE,
1117 EG_CB_COLOR0_INFO__ENDIAN_shift,
1118 EG_CB_COLOR0_INFO__ENDIAN_mask);
1119 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1120 ARRAY_LINEAR_GENERAL,
1121 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1122 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1123
1124 switch (rrb->base.Format) {
1125 case MESA_FORMAT_RGBA8888:
1126 format = COLOR_8_8_8_8;
1127 comp_swap = SWAP_STD_REV;
1128 number_type = NUMBER_UNORM;
1129 source_format = 1;
1130 break;
1131 case MESA_FORMAT_SIGNED_RGBA8888:
1132 format = COLOR_8_8_8_8;
1133 comp_swap = SWAP_STD_REV;
1134 number_type = NUMBER_SNORM;
1135 source_format = 1;
1136 break;
1137 case MESA_FORMAT_RGBA8888_REV:
1138 format = COLOR_8_8_8_8;
1139 comp_swap = SWAP_STD;
1140 number_type = NUMBER_UNORM;
1141 source_format = 1;
1142 break;
1143 case MESA_FORMAT_SIGNED_RGBA8888_REV:
1144 format = COLOR_8_8_8_8;
1145 comp_swap = SWAP_STD;
1146 number_type = NUMBER_SNORM;
1147 source_format = 1;
1148 break;
1149 case MESA_FORMAT_ARGB8888:
1150 case MESA_FORMAT_XRGB8888:
1151 format = COLOR_8_8_8_8;
1152 comp_swap = SWAP_ALT;
1153 number_type = NUMBER_UNORM;
1154 source_format = 1;
1155 break;
1156 case MESA_FORMAT_ARGB8888_REV:
1157 case MESA_FORMAT_XRGB8888_REV:
1158 format = COLOR_8_8_8_8;
1159 comp_swap = SWAP_ALT_REV;
1160 number_type = NUMBER_UNORM;
1161 source_format = 1;
1162 break;
1163 case MESA_FORMAT_RGB565:
1164 format = COLOR_5_6_5;
1165 comp_swap = SWAP_STD_REV;
1166 number_type = NUMBER_UNORM;
1167 source_format = 1;
1168 break;
1169 case MESA_FORMAT_RGB565_REV:
1170 format = COLOR_5_6_5;
1171 comp_swap = SWAP_STD;
1172 number_type = NUMBER_UNORM;
1173 source_format = 1;
1174 break;
1175 case MESA_FORMAT_ARGB4444:
1176 format = COLOR_4_4_4_4;
1177 comp_swap = SWAP_ALT;
1178 number_type = NUMBER_UNORM;
1179 source_format = 1;
1180 break;
1181 case MESA_FORMAT_ARGB4444_REV:
1182 format = COLOR_4_4_4_4;
1183 comp_swap = SWAP_ALT_REV;
1184 number_type = NUMBER_UNORM;
1185 source_format = 1;
1186 break;
1187 case MESA_FORMAT_ARGB1555:
1188 format = COLOR_1_5_5_5;
1189 comp_swap = SWAP_ALT;
1190 number_type = NUMBER_UNORM;
1191 source_format = 1;
1192 break;
1193 case MESA_FORMAT_ARGB1555_REV:
1194 format = COLOR_1_5_5_5;
1195 comp_swap = SWAP_ALT_REV;
1196 number_type = NUMBER_UNORM;
1197 source_format = 1;
1198 break;
1199 case MESA_FORMAT_AL88:
1200 format = COLOR_8_8;
1201 comp_swap = SWAP_STD;
1202 number_type = NUMBER_UNORM;
1203 source_format = 1;
1204 break;
1205 case MESA_FORMAT_AL88_REV:
1206 format = COLOR_8_8;
1207 comp_swap = SWAP_STD_REV;
1208 number_type = NUMBER_UNORM;
1209 source_format = 1;
1210 break;
1211 case MESA_FORMAT_RGB332:
1212 format = COLOR_3_3_2;
1213 comp_swap = SWAP_STD_REV;
1214 number_type = NUMBER_UNORM;
1215 source_format = 1;
1216 break;
1217 case MESA_FORMAT_A8:
1218 format = COLOR_8;
1219 comp_swap = SWAP_ALT_REV;
1220 number_type = NUMBER_UNORM;
1221 source_format = 1;
1222 break;
1223 case MESA_FORMAT_I8:
1224 case MESA_FORMAT_CI8:
1225 format = COLOR_8;
1226 comp_swap = SWAP_STD;
1227 number_type = NUMBER_UNORM;
1228 source_format = 1;
1229 break;
1230 case MESA_FORMAT_L8:
1231 format = COLOR_8;
1232 comp_swap = SWAP_ALT;
1233 number_type = NUMBER_UNORM;
1234 source_format = 1;
1235 break;
1236 case MESA_FORMAT_RGBA_FLOAT32:
1237 format = COLOR_32_32_32_32_FLOAT;
1238 comp_swap = SWAP_STD_REV;
1239 number_type = NUMBER_FLOAT;
1240 source_format = 0;
1241 break;
1242 case MESA_FORMAT_RGBA_FLOAT16:
1243 format = COLOR_16_16_16_16_FLOAT;
1244 comp_swap = SWAP_STD_REV;
1245 number_type = NUMBER_FLOAT;
1246 source_format = 0;
1247 break;
1248 case MESA_FORMAT_ALPHA_FLOAT32:
1249 format = COLOR_32_FLOAT;
1250 comp_swap = SWAP_ALT_REV;
1251 number_type = NUMBER_FLOAT;
1252 source_format = 0;
1253 break;
1254 case MESA_FORMAT_ALPHA_FLOAT16:
1255 format = COLOR_16_FLOAT;
1256 comp_swap = SWAP_ALT_REV;
1257 number_type = NUMBER_FLOAT;
1258 source_format = 0;
1259 break;
1260 case MESA_FORMAT_LUMINANCE_FLOAT32:
1261 format = COLOR_32_FLOAT;
1262 comp_swap = SWAP_ALT;
1263 number_type = NUMBER_FLOAT;
1264 source_format = 0;
1265 break;
1266 case MESA_FORMAT_LUMINANCE_FLOAT16:
1267 format = COLOR_16_FLOAT;
1268 comp_swap = SWAP_ALT;
1269 number_type = NUMBER_FLOAT;
1270 source_format = 0;
1271 break;
1272 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
1273 format = COLOR_32_32_FLOAT;
1274 comp_swap = SWAP_ALT_REV;
1275 number_type = NUMBER_FLOAT;
1276 source_format = 0;
1277 break;
1278 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
1279 format = COLOR_16_16_FLOAT;
1280 comp_swap = SWAP_ALT_REV;
1281 number_type = NUMBER_FLOAT;
1282 source_format = 0;
1283 break;
1284 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
1285 format = COLOR_32_FLOAT;
1286 comp_swap = SWAP_STD;
1287 number_type = NUMBER_FLOAT;
1288 source_format = 0;
1289 break;
1290 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
1291 format = COLOR_16_FLOAT;
1292 comp_swap = SWAP_STD;
1293 number_type = NUMBER_UNORM;
1294 source_format = 0;
1295 break;
1296 case MESA_FORMAT_X8_Z24:
1297 case MESA_FORMAT_S8_Z24:
1298 format = COLOR_8_24;
1299 comp_swap = SWAP_STD;
1300 number_type = NUMBER_UNORM;
1301 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1302 ARRAY_1D_TILED_THIN1,
1303 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1304 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1305 source_format = 0;
1306 break;
1307 case MESA_FORMAT_Z24_S8:
1308 format = COLOR_24_8;
1309 comp_swap = SWAP_STD;
1310 number_type = NUMBER_UNORM;
1311 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1312 ARRAY_1D_TILED_THIN1,
1313 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1314 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1315 source_format = 0;
1316 break;
1317 case MESA_FORMAT_Z16:
1318 format = COLOR_16;
1319 comp_swap = SWAP_STD;
1320 number_type = NUMBER_UNORM;
1321 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1322 ARRAY_1D_TILED_THIN1,
1323 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1324 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1325 source_format = 0;
1326 break;
1327 case MESA_FORMAT_Z32:
1328 format = COLOR_32;
1329 comp_swap = SWAP_STD;
1330 number_type = NUMBER_UNORM;
1331 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1332 ARRAY_1D_TILED_THIN1,
1333 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1334 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1335 source_format = 0;
1336 break;
1337 case MESA_FORMAT_SARGB8:
1338 format = COLOR_8_8_8_8;
1339 comp_swap = SWAP_ALT;
1340 number_type = NUMBER_SRGB;
1341 source_format = 1;
1342 break;
1343 case MESA_FORMAT_SLA8:
1344 format = COLOR_8_8;
1345 comp_swap = SWAP_ALT_REV;
1346 number_type = NUMBER_SRGB;
1347 source_format = 1;
1348 break;
1349 case MESA_FORMAT_SL8:
1350 format = COLOR_8;
1351 comp_swap = SWAP_ALT_REV;
1352 number_type = NUMBER_SRGB;
1353 source_format = 1;
1354 break;
1355 default:
1356 _mesa_problem(context->radeon.glCtx, "unexpected format in evergreenSetRenderTarget()");
1357 break;
1358 }
1359
1360 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1361 format,
1362 EG_CB_COLOR0_INFO__FORMAT_shift,
1363 EG_CB_COLOR0_INFO__FORMAT_mask);
1364 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1365 comp_swap,
1366 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1367 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1368 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1369 number_type,
1370 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
1371 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
1372 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1373 source_format,
1374 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
1375 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
1376 SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1377 EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
1378
1379 evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
1380 evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
1381 evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
1382 evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
1383
1384 evergreen->render_target[id].enabled = GL_TRUE;
1385 }
1386
1387 static void evergreenSendCB(struct gl_context *ctx, struct radeon_state_atom *atom)
1388 {
1389 context_t *context = EVERGREEN_CONTEXT(ctx);
1390 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1391 struct radeon_renderbuffer *rrb;
1392 BATCH_LOCALS(&context->radeon);
1393 int id = 0;
1394 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1395
1396 rrb = radeon_get_colorbuffer(&context->radeon);
1397 if (!rrb || !rrb->bo) {
1398 return;
1399 }
1400
1401 evergreenSetRenderTarget(context, 0);
1402
1403 if (!evergreen->render_target[id].enabled)
1404 return;
1405
1406 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1407 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
1408 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_BASE.u32All);
1409 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1410 rrb->bo,
1411 evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1412 0, RADEON_GEM_DOMAIN_VRAM, 0);
1413 END_BATCH();
1414
1415 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1416 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, evergreen->render_target[id].CB_COLOR0_INFO.u32All);
1417 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1418 rrb->bo,
1419 evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1420 0, RADEON_GEM_DOMAIN_VRAM, 0);
1421 END_BATCH();
1422
1423 BEGIN_BATCH_NO_AUTOSTATE(5);
1424 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
1425 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_PITCH.u32All);
1426 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_SLICE.u32All);
1427 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_VIEW.u32All);
1428 END_BATCH();
1429
1430 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1431 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 1);
1432 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All);
1433 R600_OUT_BATCH_RELOC(0,
1434 rrb->bo,
1435 0,
1436 0, RADEON_GEM_DOMAIN_VRAM, 0);
1437 END_BATCH();
1438
1439 BEGIN_BATCH_NO_AUTOSTATE(3);
1440 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_DIM, 1);
1441 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_DIM.u32All);
1442 /*
1443 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
1444 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
1445 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
1446 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
1447 */
1448 END_BATCH();
1449
1450 BEGIN_BATCH_NO_AUTOSTATE(4);
1451 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_TARGET_MASK, 2);
1452 R600_OUT_BATCH(evergreen->CB_TARGET_MASK.u32All);
1453 R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All);
1454 END_BATCH();
1455
1456 BEGIN_BATCH_NO_AUTOSTATE(6);
1457 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 4);
1458 R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All);
1459 R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All);
1460 R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All);
1461 R600_OUT_BATCH(evergreen->CB_BLEND_ALPHA.u32All);
1462 END_BATCH();
1463
1464 BEGIN_BATCH_NO_AUTOSTATE(6);
1465 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All);
1466 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All);
1467 END_BATCH();
1468
1469 COMMIT_BATCH();
1470 }
1471
1472 static void evergreenSendVGT(struct gl_context *ctx, struct radeon_state_atom *atom)
1473 {
1474 context_t *context = EVERGREEN_CONTEXT(ctx);
1475 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1476 BATCH_LOCALS(&context->radeon);
1477 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1478
1479 /* moved to draw:
1480 VGT_DRAW_INITIATOR
1481 VGT_INDEX_TYPE
1482 VGT_PRIMITIVE_TYPE
1483 */
1484 BEGIN_BATCH_NO_AUTOSTATE(5);
1485 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 3);
1486 R600_OUT_BATCH(evergreen->VGT_MAX_VTX_INDX.u32All);
1487 R600_OUT_BATCH(evergreen->VGT_MIN_VTX_INDX.u32All);
1488 R600_OUT_BATCH(evergreen->VGT_INDX_OFFSET.u32All);
1489 END_BATCH();
1490
1491 BEGIN_BATCH_NO_AUTOSTATE(6);
1492 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_OUTPUT_PATH_CNTL, evergreen->VGT_OUTPUT_PATH_CNTL.u32All);
1493
1494 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_GS_MODE, evergreen->VGT_GS_MODE.u32All);
1495 END_BATCH();
1496
1497 BEGIN_BATCH_NO_AUTOSTATE(3);
1498 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVEID_EN, 1);
1499 R600_OUT_BATCH(evergreen->VGT_PRIMITIVEID_EN.u32All);
1500 END_BATCH();
1501
1502 BEGIN_BATCH_NO_AUTOSTATE(4);
1503 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1504 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_0.u32All);
1505 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_1.u32All);
1506 END_BATCH();
1507
1508 BEGIN_BATCH_NO_AUTOSTATE(4);
1509 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1510 R600_OUT_BATCH(evergreen->VGT_REUSE_OFF.u32All);
1511 R600_OUT_BATCH(evergreen->VGT_VTX_CNT_EN.u32All);
1512 END_BATCH();
1513
1514 BEGIN_BATCH_NO_AUTOSTATE(3);
1515 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, evergreen->VGT_SHADER_STAGES_EN.u32All);
1516 END_BATCH();
1517
1518 BEGIN_BATCH_NO_AUTOSTATE(4);
1519 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1520 R600_OUT_BATCH(evergreen->VGT_STRMOUT_CONFIG.u32All);
1521 R600_OUT_BATCH(evergreen->VGT_STRMOUT_BUFFER_CONFIG.u32All);
1522 END_BATCH();
1523
1524 COMMIT_BATCH();
1525 }
1526
1527 void evergreenInitAtoms(context_t *context)
1528 {
1529 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1530 context->radeon.hw.max_state_size = 10 + 5 + 14 + 3; /* start 3d, idle, cb/db flush, 3 for time stamp */
1531
1532 /* Setup the atom linked list */
1533 make_empty_list(&context->radeon.hw.atomlist);
1534 context->radeon.hw.atomlist.name = "atom-list";
1535
1536 EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
1537 EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (VERT_ATTRIB_MAX * 12), evergreenSendVTX);
1538 EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA);
1539 EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP);
1540 EVERGREEN_ALLOC_STATE(sq, always, 86, evergreenSendSQ); /* 85 */
1541 EVERGREEN_ALLOC_STATE(vs, always, 16, evergreenSendVSresource);
1542 EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI);
1543 EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX);
1544 EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */
1545 EVERGREEN_ALLOC_STATE(db, always, 69, evergreenSendDB);
1546 EVERGREEN_ALLOC_STATE(cb, always, 37, evergreenSendCB);
1547 EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
1548
1549 evergreen_init_query_stateobj(&context->radeon, 6 * 2);
1550
1551 context->radeon.hw.is_dirty = GL_TRUE;
1552 context->radeon.hw.all_dirty = GL_TRUE;
1553 }