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r600: silence various compiler warnings
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_chip.c
1 /*
2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/imports.h"
28 #include "main/glheader.h"
29 #include "main/simple_list.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "evergreen_chip.h"
35 #include "evergreen_off.h"
36 #include "evergreen_diff.h"
37 #include "evergreen_fragprog.h"
38 #include "evergreen_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 void evergreenCreateChip(context_t *context)
43 {
44 EVERGREEN_CHIP_CONTEXT * evergreen =
45 (EVERGREEN_CHIP_CONTEXT*) CALLOC(sizeof(EVERGREEN_CHIP_CONTEXT));
46
47 context->pChip = (void*)evergreen;
48 }
49
50 #define EVERGREEN_ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
51 do { \
52 context->evergreen_atoms.ATOM.cmd_size = (SZ); \
53 context->evergreen_atoms.ATOM.cmd = NULL; \
54 context->evergreen_atoms.ATOM.name = #ATOM; \
55 context->evergreen_atoms.ATOM.idx = 0; \
56 context->evergreen_atoms.ATOM.check = check_##CHK; \
57 context->evergreen_atoms.ATOM.dirty = GL_FALSE; \
58 context->evergreen_atoms.ATOM.emit = (EMIT); \
59 context->radeon.hw.max_state_size += (SZ); \
60 insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
61 } while (0)
62
63 static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom)
64 {
65 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
66 struct radeon_query_object *query = radeon->query.current;
67 int count;
68
69 if (!query || query->emitted_begin)
70 count = 0;
71 else
72 count = atom->cmd_size;
73 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
74 return count;
75 }
76
77 static void evergreenSendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom)
78 {
79 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
80 struct radeon_query_object *query = radeon->query.current;
81 BATCH_LOCALS(radeon);
82 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
83
84 /* clear the buffer */
85 radeon_bo_map(query->bo, GL_FALSE);
86 memset(query->bo->ptr, 0, 8 * 2 * sizeof(uint64_t)); /* 8 DBs, 2 qwords each */
87 radeon_bo_unmap(query->bo);
88
89 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
90 query->bo,
91 0, RADEON_GEM_DOMAIN_GTT);
92
93 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
94 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
95 R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
96 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
97 R600_OUT_BATCH(0x00000000);
98 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
99 END_BATCH();
100 query->emitted_begin = GL_TRUE;
101 }
102
103 static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
104 {
105 radeon->query.queryobj.cmd_size = (SZ);
106 radeon->query.queryobj.cmd = NULL;
107 radeon->query.queryobj.name = "queryobj";
108 radeon->query.queryobj.idx = 0;
109 radeon->query.queryobj.check = check_queryobj;
110 radeon->query.queryobj.dirty = GL_FALSE;
111 radeon->query.queryobj.emit = evergreenSendQueryBegin;
112 radeon->hw.max_state_size += (SZ);
113 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
114 }
115
116
117 static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
118 {
119 return atom->cmd_size;
120 }
121
122 static void evergreenSendTexState(struct gl_context *ctx, struct radeon_state_atom *atom)
123 {
124 context_t *context = EVERGREEN_CONTEXT(ctx);
125 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
126
127 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
128
129 struct radeon_bo *bo = NULL;
130 unsigned int i;
131 unsigned int nBorderSet = 0;
132 BATCH_LOCALS(&context->radeon);
133
134 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
135
136 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
137 if (ctx->Texture.Unit[i]._ReallyEnabled) {
138 radeonTexObj *t = evergreen->textures[i];
139
140 if (t) {
141 /* Tex resource */
142 if (!t->image_override) {
143 bo = t->mt->bo;
144 } else {
145 bo = t->bo;
146 }
147 if (bo)
148 {
149
150 r700SyncSurf(context, bo,
151 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
152 0, TC_ACTION_ENA_bit);
153
154 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
155 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
156
157 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
158 { /* vs texture */
159 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
160 }
161 else
162 {
163 R600_OUT_BATCH(i * EG_FETCH_RESOURCE_STRIDE);
164 }
165
166 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE0);
167 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE1);
168 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE2);
169 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE3);
170 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE4);
171 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE5);
172 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE6);
173 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE7);
174
175 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE2,
176 bo,
177 evergreen->textures[i]->SQ_TEX_RESOURCE2,
178 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
179 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE3,
180 bo,
181 evergreen->textures[i]->SQ_TEX_RESOURCE3,
182 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
183 END_BATCH();
184 COMMIT_BATCH();
185 }
186 /* Tex sampler */
187 BEGIN_BATCH_NO_AUTOSTATE(5);
188 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
189
190 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
191 { /* vs texture */
192 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * 3);
193 }
194 else
195 {
196 R600_OUT_BATCH(i * 3);
197 }
198 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER0);
199 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER1);
200 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER2);
201
202 END_BATCH();
203 COMMIT_BATCH();
204
205 /* Tex border color */
206 if(0 == nBorderSet)
207 {
208 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
209 R600_OUT_BATCH_REGSEQ(EG_TD_PS_BORDER_COLOR_RED, 4);
210 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
211 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
212 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
213 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
214 END_BATCH();
215 COMMIT_BATCH();
216
217 nBorderSet = 1;
218 }
219 }
220 }
221 }
222 }
223
224 static int check_evergreen_tx(struct gl_context *ctx, struct radeon_state_atom *atom)
225 {
226 context_t *context = EVERGREEN_CONTEXT(ctx);
227 unsigned int i, count = 0;
228 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
229
230 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
231 if (ctx->Texture.Unit[i]._ReallyEnabled) {
232 radeonTexObj *t = evergreen->textures[i];
233 if (t)
234 count++;
235 }
236 }
237 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
238 return count * 37 + 6;
239 }
240
241 static void evergreenSendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom)
242 {
243 context_t *context = EVERGREEN_CONTEXT(ctx);
244 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
245 BATCH_LOCALS(&context->radeon);
246 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
247
248 BEGIN_BATCH_NO_AUTOSTATE(19);
249 //6
250 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL, evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All);
251 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL_1, evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All);
252 //6
253 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
254 R600_OUT_BATCH(evergreen->evergreen_config.SQ_CONFIG.u32All);
255 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
256 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
257 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All);
258 //7
259 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
260 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All);
261 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All);
262 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
263 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
264 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All);
265
266 END_BATCH();
267
268 COMMIT_BATCH();
269 }
270
271 extern int evergreen_getTypeSize(GLenum type);
272 static void evergreenSetupVTXConstants(struct gl_context * ctx,
273 void * pAos,
274 StreamDesc * pStreamDesc)
275 {
276 context_t *context = EVERGREEN_CONTEXT(ctx);
277 struct radeon_aos * paos = (struct radeon_aos *)pAos;
278 BATCH_LOCALS(&context->radeon);
279
280 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
281 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
282 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
283 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
284 unsigned int uSQ_VTX_CONSTANT_WORD7_0 = 0;
285
286 if (!paos->bo)
287 return;
288
289 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) ||
290 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_PALM))
291 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
292 else
293 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
294
295 //uSQ_VTX_CONSTANT_WORD0_0
296 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
297
298 //uSQ_VTX_CONSTANT_WORD1_0
299 uSQ_VTX_CONSTANT_WORD1_0 = paos->bo->size - paos->offset - 1;
300
301 //uSQ_VTX_CONSTANT_WORD2_0
302 SETfield(uSQ_VTX_CONSTANT_WORD2_0,
303 pStreamDesc->stride,
304 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
305 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
306 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
307 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
308 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
309 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
310 if(GL_TRUE == pStreamDesc->normalize)
311 {
312 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
313 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
314 }
315 else
316 {
317 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
318 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
319 }
320 if(1 == pStreamDesc->_signed)
321 {
322 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
323 }
324
325 //uSQ_VTX_CONSTANT_WORD3_0
326 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_X,
327 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
328 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
329 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Y,
330 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
331 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
332 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Z,
333 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
334 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
335 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_W,
336 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
337 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
338
339 //uSQ_VTX_CONSTANT_WORD7_0
340 SETfield(uSQ_VTX_CONSTANT_WORD7_0, SQ_TEX_VTX_VALID_BUFFER,
341 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
342
343 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
344
345 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
346 R600_OUT_BATCH((pStreamDesc->element + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
347 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
348 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
349 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
350 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
351 R600_OUT_BATCH(0);
352 R600_OUT_BATCH(0);
353 R600_OUT_BATCH(0);
354 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD7_0);
355 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
356 paos->bo,
357 uSQ_VTX_CONSTANT_WORD0_0,
358 RADEON_GEM_DOMAIN_GTT, 0, 0);
359 END_BATCH();
360
361 COMMIT_BATCH();
362 }
363
364 static int check_evergreen_vtx(struct gl_context *ctx, struct radeon_state_atom *atom)
365 {
366 context_t *context = EVERGREEN_CONTEXT(ctx);
367 int count = context->radeon.tcl.aos_count * 12;
368
369 if (count)
370 count += 6;
371
372 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
373 return count;
374 }
375
376 static void evergreenSendVTX(struct gl_context *ctx, struct radeon_state_atom *atom)
377 {
378 context_t *context = EVERGREEN_CONTEXT(ctx);
379 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
380 unsigned int i, j = 0;
381 BATCH_LOCALS(&context->radeon);
382 (void) b_l_rmesa; /* silence unused var warning */
383
384 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
385
386 if (context->radeon.tcl.aos_count == 0)
387 return;
388
389 for(i=0; i<VERT_ATTRIB_MAX; i++) {
390 if(vp->mesa_program->Base.InputsRead & (1 << i))
391 {
392 evergreenSetupVTXConstants(ctx,
393 (void*)(&context->radeon.tcl.aos[j]),
394 &(context->stream_desc[j]));
395 j++;
396 }
397 }
398 }
399 static void evergreenSendPA(struct gl_context *ctx, struct radeon_state_atom *atom)
400 {
401 context_t *context = EVERGREEN_CONTEXT(ctx);
402 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
403 BATCH_LOCALS(&context->radeon);
404 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
405 int id = 0;
406
407 BEGIN_BATCH_NO_AUTOSTATE(3);
408 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
409 END_BATCH();
410
411 BEGIN_BATCH_NO_AUTOSTATE(22);
412 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
413 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All);
414 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All);
415
416 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 12);
417 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_OFFSET.u32All);
418 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All);
419 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All);
420 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_RULE.u32All);
421 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_TL.u32All);
422 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_BR.u32All);
423 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_TL.u32All);
424 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_BR.u32All);
425 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_TL.u32All);
426 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_BR.u32All);
427 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_TL.u32All);
428 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_BR.u32All);
429
430 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
431 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All);
432 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All);
433 END_BATCH();
434
435 BEGIN_BATCH_NO_AUTOSTATE(3);
436 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SC_EDGERULE, evergreen->PA_SC_EDGERULE.u32All);
437 END_BATCH();
438
439
440 BEGIN_BATCH_NO_AUTOSTATE(18);
441 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 4);
442 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
443 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
444 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
445 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
446
447 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
448 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
449 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
450
451 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_VPORT_XSCALE, 6);
452 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XSCALE.u32All);
453 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
454 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YSCALE.u32All);
455 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
456 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
457 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
458 END_BATCH();
459
460
461 for (id = 0; id < EVERGREEN_MAX_UCP; id++) {
462 if (evergreen->ucp[id].enabled) {
463 BEGIN_BATCH_NO_AUTOSTATE(6);
464 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_UCP_0_X + (4 * id), 4);
465 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_X.u32All);
466 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Y.u32All);
467 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Z.u32All);
468 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_W.u32All);
469 END_BATCH();
470 }
471 }
472
473 BEGIN_BATCH_NO_AUTOSTATE(42);
474 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_CLIP_CNTL, 5);
475 R600_OUT_BATCH(evergreen->PA_CL_CLIP_CNTL.u32All);
476 R600_OUT_BATCH(evergreen->PA_SU_SC_MODE_CNTL.u32All);
477 R600_OUT_BATCH(evergreen->PA_CL_VTE_CNTL.u32All);
478 R600_OUT_BATCH(evergreen->PA_CL_VS_OUT_CNTL.u32All);
479 R600_OUT_BATCH(evergreen->PA_CL_NANINF_CNTL.u32All);
480
481 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 3);
482 R600_OUT_BATCH(evergreen->PA_SU_POINT_SIZE.u32All);
483 R600_OUT_BATCH(evergreen->PA_SU_POINT_MINMAX.u32All);
484 R600_OUT_BATCH(evergreen->PA_SU_LINE_CNTL.u32All);
485
486 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
487 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_0.u32All);
488 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_1.u32All);
489
490 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
491 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
492 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_CLAMP.u32All);
493 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
494 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
495 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
496 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
497
498 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
499 R600_OUT_BATCH(evergreen->PA_SC_LINE_CNTL.u32All);
500 R600_OUT_BATCH(evergreen->PA_SC_AA_CONFIG.u32All);
501 R600_OUT_BATCH(evergreen->PA_SU_VTX_CNTL.u32All);
502 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All);
503 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All);
504 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
505 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All);
506 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_0.u32All);
507 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_1.u32All);
508 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_2.u32All);
509 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_3.u32All);
510 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_4.u32All);
511 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_5.u32All);
512 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_6.u32All);
513 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_7.u32All);
514 R600_OUT_BATCH(evergreen->PA_SC_AA_MASK.u32All);
515
516 END_BATCH();
517
518 COMMIT_BATCH();
519 }
520 static void evergreenSendTP(struct gl_context *ctx, struct radeon_state_atom *atom)
521 {
522 /*
523 context_t *context = EVERGREEN_CONTEXT(ctx);
524 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
525 BATCH_LOCALS(&context->radeon);
526 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
527
528 COMMIT_BATCH();
529 */
530 }
531
532 static void evergreenSendPSresource(struct gl_context *ctx)
533 {
534 context_t *context = EVERGREEN_CONTEXT(ctx);
535 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
536 struct radeon_bo * pbo;
537 struct radeon_bo * pbo_const;
538 /* const size reg is in units of 16 consts */
539 int const_size = ((evergreen->ps.num_consts * 4) + 15) & ~15;
540
541 BATCH_LOCALS(&context->radeon);
542 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
543
544 pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(GL_CONTEXT(context));
545
546 if (!pbo)
547 return;
548
549 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
550
551 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
552 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
553 R600_OUT_BATCH(evergreen->ps.SQ_PGM_START_PS.u32All);
554 R600_OUT_BATCH_RELOC(evergreen->ps.SQ_PGM_START_PS.u32All,
555 pbo,
556 evergreen->ps.SQ_PGM_START_PS.u32All,
557 RADEON_GEM_DOMAIN_GTT, 0, 0);
558 END_BATCH();
559
560 BEGIN_BATCH_NO_AUTOSTATE(3);
561 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LOOP_CONST_0, 0x01000FFF);
562 END_BATCH();
563
564 pbo_const = (struct radeon_bo *)(context->fp_Constbo);
565
566 if(NULL != pbo_const)
567 {
568 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
569
570 BEGIN_BATCH_NO_AUTOSTATE(3);
571 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, const_size / 16);
572 END_BATCH();
573
574 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
575 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_PS_0, 1);
576 R600_OUT_BATCH(context->fp_bo_offset >> 8);
577 R600_OUT_BATCH_RELOC(0,
578 pbo_const,
579 0,
580 RADEON_GEM_DOMAIN_GTT, 0, 0);
581 END_BATCH();
582 }
583
584 COMMIT_BATCH();
585 }
586
587 static void evergreenSendVSresource(struct gl_context *ctx, struct radeon_state_atom *atom)
588 {
589 context_t *context = EVERGREEN_CONTEXT(ctx);
590 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
591 struct radeon_bo * pbo;
592 struct radeon_bo * pbo_const;
593 /* const size reg is in units of 16 consts */
594 int const_size = ((evergreen->vs.num_consts * 4) + 15) & ~15;
595
596 BATCH_LOCALS(&context->radeon);
597 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
598
599 pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(GL_CONTEXT(context));
600
601 if (!pbo)
602 return;
603
604 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
605
606 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
607 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
608 R600_OUT_BATCH(evergreen->vs.SQ_PGM_START_VS.u32All);
609 R600_OUT_BATCH_RELOC(evergreen->vs.SQ_PGM_START_VS.u32All,
610 pbo,
611 evergreen->vs.SQ_PGM_START_VS.u32All,
612 RADEON_GEM_DOMAIN_GTT, 0, 0);
613 END_BATCH();
614
615 BEGIN_BATCH_NO_AUTOSTATE(3);
616 EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + 32*1), 0x0100000F); //consts == 1
617 //EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
618 END_BATCH();
619
620 pbo_const = (struct radeon_bo *)(context->vp_Constbo);
621
622 if(NULL != pbo_const)
623 {
624 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
625
626 BEGIN_BATCH_NO_AUTOSTATE(3);
627 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, const_size / 16);
628 END_BATCH();
629
630 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
631 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_VS_0, 1);
632 R600_OUT_BATCH(context->vp_bo_offset >> 8);
633 R600_OUT_BATCH_RELOC(0,
634 pbo_const,
635 0,
636 RADEON_GEM_DOMAIN_GTT, 0, 0);
637 END_BATCH();
638 }
639
640 COMMIT_BATCH();
641 }
642
643 static void evergreenSendSQ(struct gl_context *ctx, struct radeon_state_atom *atom)
644 {
645 context_t *context = EVERGREEN_CONTEXT(ctx);
646 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
647 BATCH_LOCALS(&context->radeon);
648 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
649
650 evergreenSendPSresource(ctx); //16 entries now
651
652 BEGIN_BATCH_NO_AUTOSTATE(77);
653
654 //34
655 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_VTX_SEMANTIC_0, 32);
656 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_0.u32All); //// // = 0x28380, // SAME
657 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_1.u32All); //// // = 0x28384, // SAME
658 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_2.u32All); //// // = 0x28388, // SAME
659 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_3.u32All); //// // = 0x2838C, // SAME
660 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_4.u32All); //// // = 0x28390, // SAME
661 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_5.u32All); //// // = 0x28394, // SAME
662 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_6.u32All); //// // = 0x28398, // SAME
663 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_7.u32All); //// // = 0x2839C, // SAME
664 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_8.u32All); //// // = 0x283A0, // SAME
665 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_9.u32All); //// // = 0x283A4, // SAME
666 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_10.u32All); //// // = 0x283A8, // SAME
667 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_11.u32All); //// // = 0x283AC, // SAME
668 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_12.u32All); //// // = 0x283B0, // SAME
669 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_13.u32All); //// // = 0x283B4, // SAME
670 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_14.u32All); //// // = 0x283B8, // SAME
671 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_15.u32All); //// // = 0x283BC, // SAME
672 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_16.u32All); //// // = 0x283C0, // SAME
673 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_17.u32All); //// // = 0x283C4, // SAME
674 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_18.u32All); //// // = 0x283C8, // SAME
675 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_19.u32All); //// // = 0x283CC, // SAME
676 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_20.u32All); //// // = 0x283D0, // SAME
677 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_21.u32All); //// // = 0x283D4, // SAME
678 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_22.u32All); //// // = 0x283D8, // SAME
679 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_23.u32All); //// // = 0x283DC, // SAME
680 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_24.u32All); //// // = 0x283E0, // SAME
681 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_25.u32All); //// // = 0x283E4, // SAME
682 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_26.u32All); //// // = 0x283E8, // SAME
683 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_27.u32All); //// // = 0x283EC, // SAME
684 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_28.u32All); //// // = 0x283F0, // SAME
685 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_29.u32All); //// // = 0x283F4, // SAME
686 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_30.u32All); //// // = 0x283F8, // SAME
687 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_31.u32All); //// // = 0x283FC, // SAME
688
689
690 //3
691 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_DYN_GPR_RESOURCE_LIMIT_1, 1);
692 R600_OUT_BATCH(evergreen->SQ_DYN_GPR_RESOURCE_LIMIT_1.u32All);//// // = 0x28838, //
693
694 //5
695 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
696 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_PS.u32All); //// // = 0x28844, // DIFF 0x28850
697 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_PS.u32All); //// // = 0x28848, //
698 R600_OUT_BATCH(evergreen->SQ_PGM_EXPORTS_PS.u32All); //// // = 0x2884C, // SAME 0x28854
699
700 //4
701 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
702 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_VS.u32All);//// // = 0x28860, // DIFF 0x28868
703 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_VS.u32All); //// // = 0x28864, //
704
705 //5
706 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_GS, 2);
707 /*
708 R600_OUT_BATCH(evergreen->SQ_PGM_START_GS.u32All); //// // = 0x28874, // SAME 0x2886C
709 */
710 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_GS.u32All); //// // = 0x28878, // DIFF 0x2887C
711 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_GS.u32All); //// // = 0x2887C, //
712
713 //5
714 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_ES, 2);
715 /*
716 R600_OUT_BATCH(evergreen->SQ_PGM_START_ES.u32All); //// // = 0x2888C, // SAME 0x28880
717 */
718 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_ES.u32All); //// // = 0x28890, // DIFF
719 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_ES.u32All); //// // = 0x28894, //
720
721 //4
722 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_FS, 1);
723 /*
724 R600_OUT_BATCH(evergreen->SQ_PGM_START_FS.u32All); //// // = 0x288A4, // SAME 0x28894
725 */
726 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_FS.u32All); //// // = 0x288A8, // DIFF 0x288A4
727
728 //3
729 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_HS, 1);
730 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_HS.u32All);//// // = 0x288C0, //
731
732 //3
733 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_LS, 1);
734 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_LS.u32All); //// // = 0x288D8, //
735
736 //3
737 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_LDS_ALLOC_PS, 1);
738 R600_OUT_BATCH(evergreen->SQ_LDS_ALLOC_PS.u32All); //// // = 0x288EC, //
739
740 //8
741 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
742 R600_OUT_BATCH(evergreen->SQ_ESGS_RING_ITEMSIZE.u32All); //// // = 0x28900, // SAME 0x288A8
743 R600_OUT_BATCH(evergreen->SQ_GSVS_RING_ITEMSIZE.u32All); //// // = 0x28904, // SAME 0x288AC
744 R600_OUT_BATCH(evergreen->SQ_ESTMP_RING_ITEMSIZE.u32All); //// // = 0x28908, // SAME 0x288B0
745 R600_OUT_BATCH(evergreen->SQ_GSTMP_RING_ITEMSIZE.u32All); //// // = 0x2890C, // SAME 0x288B4
746 R600_OUT_BATCH(evergreen->SQ_VSTMP_RING_ITEMSIZE.u32All); //// // = 0x28910, // SAME 0x288B8
747 R600_OUT_BATCH(evergreen->SQ_PSTMP_RING_ITEMSIZE.u32All); //// // = 0x28914, // SAME 0x288BC
748
749 //3
750 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 1);
751 R600_OUT_BATCH(evergreen->SQ_GS_VERT_ITEMSIZE.u32All); //// // = 0x2891C, // SAME 0x288C8
752
753 END_BATCH();
754
755 COMMIT_BATCH();
756
757 }
758 static void evergreenSendSPI(struct gl_context *ctx, struct radeon_state_atom *atom)
759 {
760 context_t *context = EVERGREEN_CONTEXT(ctx);
761 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
762 BATCH_LOCALS(&context->radeon);
763 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
764
765 BEGIN_BATCH_NO_AUTOSTATE(59);
766
767 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_VS_OUT_ID_0, 10);
768 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_0.u32All);
769 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_1.u32All);
770 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_2.u32All);
771 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_3.u32All);
772 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_4.u32All);
773 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_5.u32All);
774 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_6.u32All);
775 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_7.u32All);
776 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_8.u32All);
777 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_9.u32All);
778
779 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_INPUT_CNTL_0, 45);
780 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[0].u32All);
781 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[1].u32All);
782 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[2].u32All);
783 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[3].u32All);
784 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[4].u32All);
785 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[5].u32All);
786 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[6].u32All);
787 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[7].u32All);
788 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[8].u32All);
789 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[9].u32All);
790 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[10].u32All);
791 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[11].u32All);
792 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[12].u32All);
793 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[13].u32All);
794 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[14].u32All);
795 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[15].u32All);
796 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[16].u32All);
797 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[17].u32All);
798 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[18].u32All);
799 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[19].u32All);
800 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[20].u32All);
801 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[21].u32All);
802 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[22].u32All);
803 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[23].u32All);
804 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[24].u32All);
805 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[25].u32All);
806 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[26].u32All);
807 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[27].u32All);
808 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[28].u32All);
809 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[29].u32All);
810 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[30].u32All);
811 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[31].u32All);
812 R600_OUT_BATCH(evergreen->SPI_VS_OUT_CONFIG.u32All);
813 R600_OUT_BATCH(evergreen->SPI_THREAD_GROUPING.u32All);
814 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_0.u32All);
815 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_1.u32All);
816 R600_OUT_BATCH(evergreen->SPI_INTERP_CONTROL_0.u32All);
817 R600_OUT_BATCH(evergreen->SPI_INPUT_Z.u32All);
818 R600_OUT_BATCH(evergreen->SPI_FOG_CNTL.u32All);
819 R600_OUT_BATCH(evergreen->SPI_BARYC_CNTL.u32All);
820 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_2.u32All);
821 R600_OUT_BATCH(evergreen->SPI_COMPUTE_INPUT_CNTL.u32All);
822 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_X.u32All);
823 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Y.u32All);
824 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Z.u32All);
825
826 END_BATCH();
827
828 COMMIT_BATCH();
829 }
830 static void evergreenSendSX(struct gl_context *ctx, struct radeon_state_atom *atom)
831 {
832 context_t *context = EVERGREEN_CONTEXT(ctx);
833 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
834 BATCH_LOCALS(&context->radeon);
835 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
836
837 BEGIN_BATCH_NO_AUTOSTATE(9);
838
839 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, evergreen->SX_MISC.u32All);
840 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_TEST_CONTROL, evergreen->SX_ALPHA_TEST_CONTROL.u32All);
841 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_REF, evergreen->SX_ALPHA_REF.u32All);
842
843 END_BATCH();
844
845 COMMIT_BATCH();
846 }
847
848 static void evergreenSetDepthTarget(context_t *context)
849 {
850 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
851 struct radeon_renderbuffer *rrb;
852 unsigned int nPitchInPixel, height, offtostencil;
853
854 rrb = radeon_get_depthbuffer(&context->radeon);
855 if (!rrb)
856 {
857 return;
858 }
859
860 EVERGREEN_STATECHANGE(context, db);
861
862 evergreen->DB_DEPTH_SIZE.u32All = 0;
863
864 nPitchInPixel = rrb->pitch/rrb->cpp;
865
866 if (context->radeon.radeonScreen->driScreen->dri2.enabled)
867 {
868 height = rrb->base.Height;
869 }
870 else
871 {
872 height = context->radeon.radeonScreen->driScreen->fbHeight;
873 }
874
875 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
876 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift,
877 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask);
878 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (height/8)-1,
879 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift,
880 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask);
881 evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * height)/64 )-1;
882
883 if(4 == rrb->cpp)
884 {
885 SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_24,
886 EG_DB_Z_INFO__FORMAT_shift,
887 EG_DB_Z_INFO__FORMAT_mask);
888 }
889 else
890 {
891 SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_16,
892 EG_DB_Z_INFO__FORMAT_shift,
893 EG_DB_Z_INFO__FORMAT_mask);
894 }
895 SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
896 EG_DB_Z_INFO__ARRAY_MODE_shift,
897 EG_DB_Z_INFO__ARRAY_MODE_mask);
898
899
900 offtostencil = ((height * rrb->pitch) + 255) & ~255;
901 evergreen->DB_STENCIL_WRITE_BASE.u32All = offtostencil >> 8;
902 evergreen->DB_STENCIL_READ_BASE.u32All = offtostencil >> 8;
903
904 }
905
906 static void evergreenSendDB(struct gl_context *ctx, struct radeon_state_atom *atom)
907 {
908 context_t *context = EVERGREEN_CONTEXT(ctx);
909 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
910 struct radeon_renderbuffer *rrb;
911 BATCH_LOCALS(&context->radeon);
912 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
913
914 evergreenSetDepthTarget(context);
915
916 //8
917 BEGIN_BATCH_NO_AUTOSTATE(7);
918 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
919 R600_OUT_BATCH(evergreen->DB_RENDER_CONTROL.u32All);
920 R600_OUT_BATCH(evergreen->DB_COUNT_CONTROL.u32All);
921 R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All);
922 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All);
923 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All);
924 END_BATCH();
925
926 //4
927 BEGIN_BATCH_NO_AUTOSTATE(4);
928 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
929 R600_OUT_BATCH(evergreen->DB_STENCIL_CLEAR.u32All);
930 R600_OUT_BATCH(evergreen->DB_DEPTH_CLEAR.u32All);
931 END_BATCH();
932
933 //4
934 BEGIN_BATCH_NO_AUTOSTATE(4);
935 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_DEPTH_SIZE, 2);
936 R600_OUT_BATCH(evergreen->DB_DEPTH_SIZE.u32All);
937 R600_OUT_BATCH(evergreen->DB_DEPTH_SLICE.u32All);
938 END_BATCH();
939
940 //3
941 BEGIN_BATCH_NO_AUTOSTATE(3);
942 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, evergreen->DB_DEPTH_CONTROL.u32All);
943 END_BATCH();
944
945 //3
946 BEGIN_BATCH_NO_AUTOSTATE(3);
947 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_SHADER_CONTROL, evergreen->DB_SHADER_CONTROL.u32All);
948 END_BATCH();
949
950 //5
951 BEGIN_BATCH_NO_AUTOSTATE(5);
952 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_SRESULTS_COMPARE_STATE0, 3);
953 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE0.u32All);
954 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE1.u32All);
955 R600_OUT_BATCH(evergreen->DB_PRELOAD_CONTROL.u32All);
956 END_BATCH();
957
958 //3
959 BEGIN_BATCH_NO_AUTOSTATE(3);
960 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, evergreen->DB_ALPHA_TO_MASK.u32All);
961 END_BATCH();
962
963 rrb = radeon_get_depthbuffer(&context->radeon);
964
965 if( (rrb != NULL) && (rrb->bo != NULL) )
966 {
967
968 /* make the hw happy */
969 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
970 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All);
971 R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All,
972 rrb->bo,
973 evergreen->DB_HTILE_DATA_BASE.u32All,
974 0, RADEON_GEM_DOMAIN_VRAM, 0);
975 END_BATCH();
976
977 //5
978 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
979 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All);
980 R600_OUT_BATCH_RELOC(evergreen->DB_Z_INFO.u32All,
981 rrb->bo,
982 evergreen->DB_Z_INFO.u32All,
983 0, RADEON_GEM_DOMAIN_VRAM, 0);
984 END_BATCH();
985
986 //5
987 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_ENABLE_bit) > 0)
988 {
989 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
990 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_READ_BASE, evergreen->DB_Z_READ_BASE.u32All);
991 R600_OUT_BATCH_RELOC(evergreen->DB_Z_READ_BASE.u32All,
992 rrb->bo,
993 evergreen->DB_Z_READ_BASE.u32All,
994 0, RADEON_GEM_DOMAIN_VRAM, 0);
995 END_BATCH();
996 }
997 //5
998 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_WRITE_ENABLE_bit) > 0)
999 {
1000 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1001 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_WRITE_BASE, evergreen->DB_Z_READ_BASE.u32All);
1002 R600_OUT_BATCH_RELOC(evergreen->DB_Z_WRITE_BASE.u32All,
1003 rrb->bo,
1004 evergreen->DB_Z_WRITE_BASE.u32All,
1005 0, RADEON_GEM_DOMAIN_VRAM, 0);
1006 END_BATCH();
1007 }
1008 }
1009
1010 if (ctx->DrawBuffer)
1011 {
1012 rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
1013
1014 if((rrb != NULL) && (rrb->bo != NULL))
1015 {
1016 //5
1017 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1018 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_STENCIL_INFO.u32All);
1019 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All,
1020 rrb->bo,
1021 evergreen->DB_STENCIL_INFO.u32All,
1022 0, RADEON_GEM_DOMAIN_VRAM, 0);
1023 END_BATCH();
1024
1025 //4
1026 BEGIN_BATCH_NO_AUTOSTATE(4);
1027 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
1028 R600_OUT_BATCH(evergreen->DB_STENCILREFMASK.u32All);
1029 R600_OUT_BATCH(evergreen->DB_STENCILREFMASK_BF.u32All);
1030 END_BATCH();
1031 //------------------------
1032
1033 //10
1034 if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
1035 {
1036
1037 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1038 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
1039 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
1040 rrb->bo,
1041 evergreen->DB_STENCIL_READ_BASE.u32All,
1042 0, RADEON_GEM_DOMAIN_VRAM, 0);
1043 END_BATCH();
1044
1045 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1046 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
1047 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
1048 rrb->bo,
1049 evergreen->DB_STENCIL_WRITE_BASE.u32All,
1050 0, RADEON_GEM_DOMAIN_VRAM, 0);
1051 END_BATCH();
1052 }
1053 }
1054 }
1055
1056 COMMIT_BATCH();
1057 }
1058
1059 static void evergreenSetRenderTarget(context_t *context, int id)
1060 {
1061 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1062 uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM, source_format = 1;
1063 struct radeon_renderbuffer *rrb;
1064 unsigned int nPitchInPixel, height;
1065
1066 rrb = radeon_get_colorbuffer(&context->radeon);
1067 if (!rrb || !rrb->bo) {
1068 return;
1069 }
1070
1071 EVERGREEN_STATECHANGE(context, cb);
1072
1073 /* addr */
1074 evergreen->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
1075
1076 /* pitch */
1077 nPitchInPixel = rrb->pitch/rrb->cpp;
1078
1079 if (context->radeon.radeonScreen->driScreen->dri2.enabled)
1080 {
1081 height = rrb->base.Height;
1082 }
1083 else
1084 {
1085 height = context->radeon.radeonScreen->driScreen->fbHeight;
1086 }
1087
1088 SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1,
1089 EG_CB_COLOR0_PITCH__TILE_MAX_shift,
1090 EG_CB_COLOR0_PITCH__TILE_MAX_mask);
1091
1092 /* slice */
1093 SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All,
1094 ( (nPitchInPixel * height)/64 )-1,
1095 EG_CB_COLOR0_SLICE__TILE_MAX_shift,
1096 EG_CB_COLOR0_SLICE__TILE_MAX_mask);
1097
1098 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
1099 SETbit(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All,
1100 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
1101
1102 /* CB_COLOR0_INFO */
1103 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1104 ENDIAN_NONE,
1105 EG_CB_COLOR0_INFO__ENDIAN_shift,
1106 EG_CB_COLOR0_INFO__ENDIAN_mask);
1107 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1108 ARRAY_LINEAR_GENERAL,
1109 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1110 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1111
1112 switch (rrb->base.Format) {
1113 case MESA_FORMAT_RGBA8888:
1114 format = COLOR_8_8_8_8;
1115 comp_swap = SWAP_STD_REV;
1116 number_type = NUMBER_UNORM;
1117 source_format = 1;
1118 break;
1119 case MESA_FORMAT_SIGNED_RGBA8888:
1120 format = COLOR_8_8_8_8;
1121 comp_swap = SWAP_STD_REV;
1122 number_type = NUMBER_SNORM;
1123 source_format = 1;
1124 break;
1125 case MESA_FORMAT_RGBA8888_REV:
1126 format = COLOR_8_8_8_8;
1127 comp_swap = SWAP_STD;
1128 number_type = NUMBER_UNORM;
1129 source_format = 1;
1130 break;
1131 case MESA_FORMAT_SIGNED_RGBA8888_REV:
1132 format = COLOR_8_8_8_8;
1133 comp_swap = SWAP_STD;
1134 number_type = NUMBER_SNORM;
1135 source_format = 1;
1136 break;
1137 case MESA_FORMAT_ARGB8888:
1138 case MESA_FORMAT_XRGB8888:
1139 format = COLOR_8_8_8_8;
1140 comp_swap = SWAP_ALT;
1141 number_type = NUMBER_UNORM;
1142 source_format = 1;
1143 break;
1144 case MESA_FORMAT_ARGB8888_REV:
1145 case MESA_FORMAT_XRGB8888_REV:
1146 format = COLOR_8_8_8_8;
1147 comp_swap = SWAP_ALT_REV;
1148 number_type = NUMBER_UNORM;
1149 source_format = 1;
1150 break;
1151 case MESA_FORMAT_RGB565:
1152 format = COLOR_5_6_5;
1153 comp_swap = SWAP_STD_REV;
1154 number_type = NUMBER_UNORM;
1155 source_format = 1;
1156 break;
1157 case MESA_FORMAT_RGB565_REV:
1158 format = COLOR_5_6_5;
1159 comp_swap = SWAP_STD;
1160 number_type = NUMBER_UNORM;
1161 source_format = 1;
1162 break;
1163 case MESA_FORMAT_ARGB4444:
1164 format = COLOR_4_4_4_4;
1165 comp_swap = SWAP_ALT;
1166 number_type = NUMBER_UNORM;
1167 source_format = 1;
1168 break;
1169 case MESA_FORMAT_ARGB4444_REV:
1170 format = COLOR_4_4_4_4;
1171 comp_swap = SWAP_ALT_REV;
1172 number_type = NUMBER_UNORM;
1173 source_format = 1;
1174 break;
1175 case MESA_FORMAT_ARGB1555:
1176 format = COLOR_1_5_5_5;
1177 comp_swap = SWAP_ALT;
1178 number_type = NUMBER_UNORM;
1179 source_format = 1;
1180 break;
1181 case MESA_FORMAT_ARGB1555_REV:
1182 format = COLOR_1_5_5_5;
1183 comp_swap = SWAP_ALT_REV;
1184 number_type = NUMBER_UNORM;
1185 source_format = 1;
1186 break;
1187 case MESA_FORMAT_AL88:
1188 format = COLOR_8_8;
1189 comp_swap = SWAP_STD;
1190 number_type = NUMBER_UNORM;
1191 source_format = 1;
1192 break;
1193 case MESA_FORMAT_AL88_REV:
1194 format = COLOR_8_8;
1195 comp_swap = SWAP_STD_REV;
1196 number_type = NUMBER_UNORM;
1197 source_format = 1;
1198 break;
1199 case MESA_FORMAT_RGB332:
1200 format = COLOR_3_3_2;
1201 comp_swap = SWAP_STD_REV;
1202 number_type = NUMBER_UNORM;
1203 source_format = 1;
1204 break;
1205 case MESA_FORMAT_A8:
1206 format = COLOR_8;
1207 comp_swap = SWAP_ALT_REV;
1208 number_type = NUMBER_UNORM;
1209 source_format = 1;
1210 break;
1211 case MESA_FORMAT_I8:
1212 case MESA_FORMAT_CI8:
1213 format = COLOR_8;
1214 comp_swap = SWAP_STD;
1215 number_type = NUMBER_UNORM;
1216 source_format = 1;
1217 break;
1218 case MESA_FORMAT_L8:
1219 format = COLOR_8;
1220 comp_swap = SWAP_ALT;
1221 number_type = NUMBER_UNORM;
1222 source_format = 1;
1223 break;
1224 case MESA_FORMAT_RGBA_FLOAT32:
1225 format = COLOR_32_32_32_32_FLOAT;
1226 comp_swap = SWAP_STD_REV;
1227 number_type = NUMBER_FLOAT;
1228 source_format = 0;
1229 break;
1230 case MESA_FORMAT_RGBA_FLOAT16:
1231 format = COLOR_16_16_16_16_FLOAT;
1232 comp_swap = SWAP_STD_REV;
1233 number_type = NUMBER_FLOAT;
1234 source_format = 0;
1235 break;
1236 case MESA_FORMAT_ALPHA_FLOAT32:
1237 format = COLOR_32_FLOAT;
1238 comp_swap = SWAP_ALT_REV;
1239 number_type = NUMBER_FLOAT;
1240 source_format = 0;
1241 break;
1242 case MESA_FORMAT_ALPHA_FLOAT16:
1243 format = COLOR_16_FLOAT;
1244 comp_swap = SWAP_ALT_REV;
1245 number_type = NUMBER_FLOAT;
1246 source_format = 0;
1247 break;
1248 case MESA_FORMAT_LUMINANCE_FLOAT32:
1249 format = COLOR_32_FLOAT;
1250 comp_swap = SWAP_ALT;
1251 number_type = NUMBER_FLOAT;
1252 source_format = 0;
1253 break;
1254 case MESA_FORMAT_LUMINANCE_FLOAT16:
1255 format = COLOR_16_FLOAT;
1256 comp_swap = SWAP_ALT;
1257 number_type = NUMBER_FLOAT;
1258 source_format = 0;
1259 break;
1260 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
1261 format = COLOR_32_32_FLOAT;
1262 comp_swap = SWAP_ALT_REV;
1263 number_type = NUMBER_FLOAT;
1264 source_format = 0;
1265 break;
1266 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
1267 format = COLOR_16_16_FLOAT;
1268 comp_swap = SWAP_ALT_REV;
1269 number_type = NUMBER_FLOAT;
1270 source_format = 0;
1271 break;
1272 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
1273 format = COLOR_32_FLOAT;
1274 comp_swap = SWAP_STD;
1275 number_type = NUMBER_FLOAT;
1276 source_format = 0;
1277 break;
1278 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
1279 format = COLOR_16_FLOAT;
1280 comp_swap = SWAP_STD;
1281 number_type = NUMBER_UNORM;
1282 source_format = 0;
1283 break;
1284 case MESA_FORMAT_X8_Z24:
1285 case MESA_FORMAT_S8_Z24:
1286 format = COLOR_8_24;
1287 comp_swap = SWAP_STD;
1288 number_type = NUMBER_UNORM;
1289 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1290 ARRAY_1D_TILED_THIN1,
1291 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1292 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1293 source_format = 0;
1294 break;
1295 case MESA_FORMAT_Z24_S8:
1296 format = COLOR_24_8;
1297 comp_swap = SWAP_STD;
1298 number_type = NUMBER_UNORM;
1299 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1300 ARRAY_1D_TILED_THIN1,
1301 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1302 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1303 source_format = 0;
1304 break;
1305 case MESA_FORMAT_Z16:
1306 format = COLOR_16;
1307 comp_swap = SWAP_STD;
1308 number_type = NUMBER_UNORM;
1309 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1310 ARRAY_1D_TILED_THIN1,
1311 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1312 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1313 source_format = 0;
1314 break;
1315 case MESA_FORMAT_Z32:
1316 format = COLOR_32;
1317 comp_swap = SWAP_STD;
1318 number_type = NUMBER_UNORM;
1319 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1320 ARRAY_1D_TILED_THIN1,
1321 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1322 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1323 source_format = 0;
1324 break;
1325 case MESA_FORMAT_SARGB8:
1326 format = COLOR_8_8_8_8;
1327 comp_swap = SWAP_ALT;
1328 number_type = NUMBER_SRGB;
1329 source_format = 1;
1330 break;
1331 case MESA_FORMAT_SLA8:
1332 format = COLOR_8_8;
1333 comp_swap = SWAP_ALT_REV;
1334 number_type = NUMBER_SRGB;
1335 source_format = 1;
1336 break;
1337 case MESA_FORMAT_SL8:
1338 format = COLOR_8;
1339 comp_swap = SWAP_ALT_REV;
1340 number_type = NUMBER_SRGB;
1341 source_format = 1;
1342 break;
1343 default:
1344 _mesa_problem(context->radeon.glCtx, "unexpected format in evergreenSetRenderTarget()");
1345 break;
1346 }
1347
1348 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1349 format,
1350 EG_CB_COLOR0_INFO__FORMAT_shift,
1351 EG_CB_COLOR0_INFO__FORMAT_mask);
1352 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1353 comp_swap,
1354 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1355 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1356 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1357 number_type,
1358 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
1359 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
1360 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1361 source_format,
1362 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
1363 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
1364 SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1365 EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
1366
1367 evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
1368 evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
1369 evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
1370 evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
1371
1372 evergreen->render_target[id].enabled = GL_TRUE;
1373 }
1374
1375 static void evergreenSendCB(struct gl_context *ctx, struct radeon_state_atom *atom)
1376 {
1377 context_t *context = EVERGREEN_CONTEXT(ctx);
1378 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1379 struct radeon_renderbuffer *rrb;
1380 BATCH_LOCALS(&context->radeon);
1381 int id = 0;
1382 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1383
1384 rrb = radeon_get_colorbuffer(&context->radeon);
1385 if (!rrb || !rrb->bo) {
1386 return;
1387 }
1388
1389 evergreenSetRenderTarget(context, 0);
1390
1391 if (!evergreen->render_target[id].enabled)
1392 return;
1393
1394 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1395 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
1396 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_BASE.u32All);
1397 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1398 rrb->bo,
1399 evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1400 0, RADEON_GEM_DOMAIN_VRAM, 0);
1401 END_BATCH();
1402
1403 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1404 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, evergreen->render_target[id].CB_COLOR0_INFO.u32All);
1405 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1406 rrb->bo,
1407 evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1408 0, RADEON_GEM_DOMAIN_VRAM, 0);
1409 END_BATCH();
1410
1411 BEGIN_BATCH_NO_AUTOSTATE(5);
1412 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
1413 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_PITCH.u32All);
1414 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_SLICE.u32All);
1415 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_VIEW.u32All);
1416 END_BATCH();
1417
1418 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1419 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 1);
1420 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All);
1421 R600_OUT_BATCH_RELOC(0,
1422 rrb->bo,
1423 0,
1424 0, RADEON_GEM_DOMAIN_VRAM, 0);
1425 END_BATCH();
1426
1427 BEGIN_BATCH_NO_AUTOSTATE(3);
1428 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_DIM, 1);
1429 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_DIM.u32All);
1430 /*
1431 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
1432 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
1433 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
1434 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
1435 */
1436 END_BATCH();
1437
1438 BEGIN_BATCH_NO_AUTOSTATE(4);
1439 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_TARGET_MASK, 2);
1440 R600_OUT_BATCH(evergreen->CB_TARGET_MASK.u32All);
1441 R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All);
1442 END_BATCH();
1443
1444 BEGIN_BATCH_NO_AUTOSTATE(6);
1445 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 4);
1446 R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All);
1447 R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All);
1448 R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All);
1449 R600_OUT_BATCH(evergreen->CB_BLEND_ALPHA.u32All);
1450 END_BATCH();
1451
1452 BEGIN_BATCH_NO_AUTOSTATE(6);
1453 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All);
1454 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All);
1455 END_BATCH();
1456
1457 COMMIT_BATCH();
1458 }
1459
1460 static void evergreenSendVGT(struct gl_context *ctx, struct radeon_state_atom *atom)
1461 {
1462 context_t *context = EVERGREEN_CONTEXT(ctx);
1463 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1464 BATCH_LOCALS(&context->radeon);
1465 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1466
1467 /* moved to draw:
1468 VGT_DRAW_INITIATOR
1469 VGT_INDEX_TYPE
1470 VGT_PRIMITIVE_TYPE
1471 */
1472 BEGIN_BATCH_NO_AUTOSTATE(5);
1473 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 3);
1474 R600_OUT_BATCH(evergreen->VGT_MAX_VTX_INDX.u32All);
1475 R600_OUT_BATCH(evergreen->VGT_MIN_VTX_INDX.u32All);
1476 R600_OUT_BATCH(evergreen->VGT_INDX_OFFSET.u32All);
1477 END_BATCH();
1478
1479 BEGIN_BATCH_NO_AUTOSTATE(6);
1480 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_OUTPUT_PATH_CNTL, evergreen->VGT_OUTPUT_PATH_CNTL.u32All);
1481
1482 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_GS_MODE, evergreen->VGT_GS_MODE.u32All);
1483 END_BATCH();
1484
1485 BEGIN_BATCH_NO_AUTOSTATE(3);
1486 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVEID_EN, 1);
1487 R600_OUT_BATCH(evergreen->VGT_PRIMITIVEID_EN.u32All);
1488 END_BATCH();
1489
1490 BEGIN_BATCH_NO_AUTOSTATE(4);
1491 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1492 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_0.u32All);
1493 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_1.u32All);
1494 END_BATCH();
1495
1496 BEGIN_BATCH_NO_AUTOSTATE(4);
1497 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1498 R600_OUT_BATCH(evergreen->VGT_REUSE_OFF.u32All);
1499 R600_OUT_BATCH(evergreen->VGT_VTX_CNT_EN.u32All);
1500 END_BATCH();
1501
1502 BEGIN_BATCH_NO_AUTOSTATE(3);
1503 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, evergreen->VGT_SHADER_STAGES_EN.u32All);
1504 END_BATCH();
1505
1506 BEGIN_BATCH_NO_AUTOSTATE(4);
1507 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1508 R600_OUT_BATCH(evergreen->VGT_STRMOUT_CONFIG.u32All);
1509 R600_OUT_BATCH(evergreen->VGT_STRMOUT_BUFFER_CONFIG.u32All);
1510 END_BATCH();
1511
1512 COMMIT_BATCH();
1513 }
1514
1515 void evergreenInitAtoms(context_t *context)
1516 {
1517 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1518 context->radeon.hw.max_state_size = 10 + 5 + 14 + 3; /* start 3d, idle, cb/db flush, 3 for time stamp */
1519
1520 /* Setup the atom linked list */
1521 make_empty_list(&context->radeon.hw.atomlist);
1522 context->radeon.hw.atomlist.name = "atom-list";
1523
1524 EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
1525 EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (VERT_ATTRIB_MAX * 12), evergreenSendVTX);
1526 EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA);
1527 EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP);
1528 EVERGREEN_ALLOC_STATE(sq, always, 86, evergreenSendSQ); /* 85 */
1529 EVERGREEN_ALLOC_STATE(vs, always, 16, evergreenSendVSresource);
1530 EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI);
1531 EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX);
1532 EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */
1533 EVERGREEN_ALLOC_STATE(db, always, 69, evergreenSendDB);
1534 EVERGREEN_ALLOC_STATE(cb, always, 37, evergreenSendCB);
1535 EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
1536
1537 evergreen_init_query_stateobj(&context->radeon, 6 * 2);
1538
1539 context->radeon.hw.is_dirty = GL_TRUE;
1540 context->radeon.hw.all_dirty = GL_TRUE;
1541 }