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Merge remote branch 'origin/master' into lp-setup-llvm
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_chip.c
1 /*
2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/imports.h"
28 #include "main/glheader.h"
29 #include "main/simple_list.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "evergreen_chip.h"
35 #include "evergreen_off.h"
36 #include "evergreen_diff.h"
37 #include "evergreen_fragprog.h"
38 #include "evergreen_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 void evergreenCreateChip(context_t *context)
43 {
44 EVERGREEN_CHIP_CONTEXT * evergreen =
45 (EVERGREEN_CHIP_CONTEXT*) CALLOC(sizeof(EVERGREEN_CHIP_CONTEXT));
46
47 context->pChip = (void*)evergreen;
48 }
49
50 #define EVERGREEN_ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
51 do { \
52 context->evergreen_atoms.ATOM.cmd_size = (SZ); \
53 context->evergreen_atoms.ATOM.cmd = NULL; \
54 context->evergreen_atoms.ATOM.name = #ATOM; \
55 context->evergreen_atoms.ATOM.idx = 0; \
56 context->evergreen_atoms.ATOM.check = check_##CHK; \
57 context->evergreen_atoms.ATOM.dirty = GL_FALSE; \
58 context->evergreen_atoms.ATOM.emit = (EMIT); \
59 context->radeon.hw.max_state_size += (SZ); \
60 insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
61 } while (0)
62
63 static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom)
64 {
65 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
66 struct radeon_query_object *query = radeon->query.current;
67 int count;
68
69 if (!query || query->emitted_begin)
70 count = 0;
71 else
72 count = atom->cmd_size;
73 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
74 return count;
75 }
76
77 static void evergreenSendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom)
78 {
79 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
80 struct radeon_query_object *query = radeon->query.current;
81 BATCH_LOCALS(radeon);
82 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
83
84 /* clear the buffer */
85 radeon_bo_map(query->bo, GL_FALSE);
86 memset(query->bo->ptr, 0, 8 * 2 * sizeof(uint64_t)); /* 8 DBs, 2 qwords each */
87 radeon_bo_unmap(query->bo);
88
89 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
90 query->bo,
91 0, RADEON_GEM_DOMAIN_GTT);
92
93 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
94 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
95 R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
96 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
97 R600_OUT_BATCH(0x00000000);
98 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
99 END_BATCH();
100 query->emitted_begin = GL_TRUE;
101 }
102
103 static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
104 {
105 radeon->query.queryobj.cmd_size = (SZ);
106 radeon->query.queryobj.cmd = NULL;
107 radeon->query.queryobj.name = "queryobj";
108 radeon->query.queryobj.idx = 0;
109 radeon->query.queryobj.check = check_queryobj;
110 radeon->query.queryobj.dirty = GL_FALSE;
111 radeon->query.queryobj.emit = evergreenSendQueryBegin;
112 radeon->hw.max_state_size += (SZ);
113 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
114 }
115
116
117 static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
118 {
119 return atom->cmd_size;
120 }
121
122 static void evergreenSendTexState(struct gl_context *ctx, struct radeon_state_atom *atom)
123 {
124 context_t *context = EVERGREEN_CONTEXT(ctx);
125 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
126
127 struct evergreen_vertex_program *vp = context->selected_vp;
128
129 struct radeon_bo *bo = NULL;
130 unsigned int i;
131 unsigned int nBorderSet = 0;
132 BATCH_LOCALS(&context->radeon);
133
134 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
135
136 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
137 if (ctx->Texture.Unit[i]._ReallyEnabled) {
138 radeonTexObj *t = evergreen->textures[i];
139
140 if (t) {
141 /* Tex resource */
142 if (!t->image_override) {
143 bo = t->mt->bo;
144 } else {
145 bo = t->bo;
146 }
147 if (bo)
148 {
149
150 r700SyncSurf(context, bo,
151 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
152 0, TC_ACTION_ENA_bit);
153
154 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
155 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
156
157 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
158 { /* vs texture */
159 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
160 }
161 else
162 {
163 R600_OUT_BATCH(i * EG_FETCH_RESOURCE_STRIDE);
164 }
165
166 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE0);
167 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE1);
168 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE2);
169 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE3);
170 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE4);
171 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE5);
172 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE6);
173 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE7);
174
175 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE2,
176 bo,
177 evergreen->textures[i]->SQ_TEX_RESOURCE2,
178 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
179 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE3,
180 bo,
181 evergreen->textures[i]->SQ_TEX_RESOURCE3,
182 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
183 END_BATCH();
184 COMMIT_BATCH();
185 }
186 /* Tex sampler */
187 BEGIN_BATCH_NO_AUTOSTATE(5);
188 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
189
190 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
191 { /* vs texture */
192 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * 3);
193 }
194 else
195 {
196 R600_OUT_BATCH(i * 3);
197 }
198 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER0);
199 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER1);
200 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER2);
201
202 END_BATCH();
203 COMMIT_BATCH();
204
205 /* Tex border color */
206 if(0 == nBorderSet)
207 {
208 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
209 R600_OUT_BATCH_REGSEQ(EG_TD_PS_BORDER_COLOR_RED, 4);
210 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
211 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
212 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
213 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
214 END_BATCH();
215 COMMIT_BATCH();
216
217 nBorderSet = 1;
218 }
219 }
220 }
221 }
222 }
223
224 static int check_evergreen_tx(struct gl_context *ctx, struct radeon_state_atom *atom)
225 {
226 context_t *context = EVERGREEN_CONTEXT(ctx);
227 unsigned int i, count = 0;
228 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
229
230 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
231 if (ctx->Texture.Unit[i]._ReallyEnabled) {
232 radeonTexObj *t = evergreen->textures[i];
233 if (t)
234 count++;
235 }
236 }
237 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
238 return count * 37 + 6;
239 }
240
241 static void evergreenSendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom)
242 {
243 context_t *context = EVERGREEN_CONTEXT(ctx);
244 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
245 BATCH_LOCALS(&context->radeon);
246 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
247
248 BEGIN_BATCH_NO_AUTOSTATE(19);
249 //6
250 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL, evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All);
251 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL_1, evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All);
252 //6
253 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
254 R600_OUT_BATCH(evergreen->evergreen_config.SQ_CONFIG.u32All);
255 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
256 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
257 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All);
258 //7
259 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
260 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All);
261 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All);
262 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
263 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
264 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All);
265
266 END_BATCH();
267
268 COMMIT_BATCH();
269 }
270
271 extern int evergreen_getTypeSize(GLenum type);
272 static void evergreenSetupVTXConstants(struct gl_context * ctx,
273 void * pAos,
274 StreamDesc * pStreamDesc)
275 {
276 context_t *context = EVERGREEN_CONTEXT(ctx);
277 struct radeon_aos * paos = (struct radeon_aos *)pAos;
278 BATCH_LOCALS(&context->radeon);
279
280 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
281 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
282 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
283 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
284 unsigned int uSQ_VTX_CONSTANT_WORD7_0 = 0;
285
286 if (!paos->bo)
287 return;
288
289 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
290
291 //uSQ_VTX_CONSTANT_WORD0_0
292 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
293
294 //uSQ_VTX_CONSTANT_WORD1_0
295 uSQ_VTX_CONSTANT_WORD1_0 = paos->bo->size - paos->offset - 1;
296
297 //uSQ_VTX_CONSTANT_WORD2_0
298 SETfield(uSQ_VTX_CONSTANT_WORD2_0,
299 pStreamDesc->stride,
300 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
301 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
302 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
303 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
304 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
305 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
306 if(GL_TRUE == pStreamDesc->normalize)
307 {
308 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
309 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
310 }
311 else
312 {
313 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
314 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
315 }
316 if(1 == pStreamDesc->_signed)
317 {
318 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
319 }
320
321 //uSQ_VTX_CONSTANT_WORD3_0
322 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_X,
323 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
324 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
325 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Y,
326 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
327 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
328 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Z,
329 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
330 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
331 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_W,
332 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
333 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
334
335 //uSQ_VTX_CONSTANT_WORD7_0
336 SETfield(uSQ_VTX_CONSTANT_WORD7_0, SQ_TEX_VTX_VALID_BUFFER,
337 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
338
339 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
340
341 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
342 R600_OUT_BATCH((pStreamDesc->element + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
343 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
344 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
345 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
346 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
347 R600_OUT_BATCH(0);
348 R600_OUT_BATCH(0);
349 R600_OUT_BATCH(0);
350 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD7_0);
351 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
352 paos->bo,
353 uSQ_VTX_CONSTANT_WORD0_0,
354 RADEON_GEM_DOMAIN_GTT, 0, 0);
355 END_BATCH();
356
357 COMMIT_BATCH();
358 }
359
360 static int check_evergreen_vtx(struct gl_context *ctx, struct radeon_state_atom *atom)
361 {
362 context_t *context = EVERGREEN_CONTEXT(ctx);
363 int count = context->radeon.tcl.aos_count * 12;
364
365 if (count)
366 count += 6;
367
368 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
369 return count;
370 }
371
372 static void evergreenSendVTX(struct gl_context *ctx, struct radeon_state_atom *atom)
373 {
374 context_t *context = EVERGREEN_CONTEXT(ctx);
375 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
376 unsigned int i, j = 0;
377 BATCH_LOCALS(&context->radeon);
378 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
379
380 if (context->radeon.tcl.aos_count == 0)
381 return;
382
383 for(i=0; i<VERT_ATTRIB_MAX; i++) {
384 if(vp->mesa_program->Base.InputsRead & (1 << i))
385 {
386 evergreenSetupVTXConstants(ctx,
387 (void*)(&context->radeon.tcl.aos[j]),
388 &(context->stream_desc[j]));
389 j++;
390 }
391 }
392 }
393 static void evergreenSendPA(struct gl_context *ctx, struct radeon_state_atom *atom)
394 {
395 context_t *context = EVERGREEN_CONTEXT(ctx);
396 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
397 BATCH_LOCALS(&context->radeon);
398 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
399 int id = 0;
400
401 BEGIN_BATCH_NO_AUTOSTATE(3);
402 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
403 END_BATCH();
404
405 BEGIN_BATCH_NO_AUTOSTATE(22);
406 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
407 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All);
408 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All);
409
410 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 12);
411 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_OFFSET.u32All);
412 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All);
413 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All);
414 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_RULE.u32All);
415 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_TL.u32All);
416 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_BR.u32All);
417 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_TL.u32All);
418 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_BR.u32All);
419 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_TL.u32All);
420 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_BR.u32All);
421 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_TL.u32All);
422 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_BR.u32All);
423
424 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
425 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All);
426 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All);
427 END_BATCH();
428
429 BEGIN_BATCH_NO_AUTOSTATE(3);
430 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SC_EDGERULE, evergreen->PA_SC_EDGERULE.u32All);
431 END_BATCH();
432
433
434 BEGIN_BATCH_NO_AUTOSTATE(18);
435 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 4);
436 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
437 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
438 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
439 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
440
441 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
442 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
443 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
444
445 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_VPORT_XSCALE, 6);
446 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XSCALE.u32All);
447 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
448 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YSCALE.u32All);
449 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
450 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
451 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
452 END_BATCH();
453
454
455 for (id = 0; id < EVERGREEN_MAX_UCP; id++) {
456 if (evergreen->ucp[id].enabled) {
457 BEGIN_BATCH_NO_AUTOSTATE(6);
458 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_UCP_0_X + (4 * id), 4);
459 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_X.u32All);
460 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Y.u32All);
461 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Z.u32All);
462 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_W.u32All);
463 END_BATCH();
464 }
465 }
466
467 BEGIN_BATCH_NO_AUTOSTATE(42);
468 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_CLIP_CNTL, 5);
469 R600_OUT_BATCH(evergreen->PA_CL_CLIP_CNTL.u32All);
470 R600_OUT_BATCH(evergreen->PA_SU_SC_MODE_CNTL.u32All);
471 R600_OUT_BATCH(evergreen->PA_CL_VTE_CNTL.u32All);
472 R600_OUT_BATCH(evergreen->PA_CL_VS_OUT_CNTL.u32All);
473 R600_OUT_BATCH(evergreen->PA_CL_NANINF_CNTL.u32All);
474
475 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 3);
476 R600_OUT_BATCH(evergreen->PA_SU_POINT_SIZE.u32All);
477 R600_OUT_BATCH(evergreen->PA_SU_POINT_MINMAX.u32All);
478 R600_OUT_BATCH(evergreen->PA_SU_LINE_CNTL.u32All);
479
480 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
481 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_0.u32All);
482 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_1.u32All);
483
484 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
485 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
486 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_CLAMP.u32All);
487 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
488 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
489 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
490 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
491
492 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
493 R600_OUT_BATCH(evergreen->PA_SC_LINE_CNTL.u32All);
494 R600_OUT_BATCH(evergreen->PA_SC_AA_CONFIG.u32All);
495 R600_OUT_BATCH(evergreen->PA_SU_VTX_CNTL.u32All);
496 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All);
497 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All);
498 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
499 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All);
500 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_0.u32All);
501 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_1.u32All);
502 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_2.u32All);
503 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_3.u32All);
504 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_4.u32All);
505 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_5.u32All);
506 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_6.u32All);
507 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_7.u32All);
508 R600_OUT_BATCH(evergreen->PA_SC_AA_MASK.u32All);
509
510 END_BATCH();
511
512 COMMIT_BATCH();
513 }
514 static void evergreenSendTP(struct gl_context *ctx, struct radeon_state_atom *atom)
515 {
516 /*
517 context_t *context = EVERGREEN_CONTEXT(ctx);
518 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
519 BATCH_LOCALS(&context->radeon);
520 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
521
522 COMMIT_BATCH();
523 */
524 }
525
526 static void evergreenSendPSresource(struct gl_context *ctx)
527 {
528 context_t *context = EVERGREEN_CONTEXT(ctx);
529 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
530 struct radeon_bo * pbo;
531 struct radeon_bo * pbo_const;
532 /* const size reg is in units of 16 consts */
533 int const_size = ((evergreen->ps.num_consts * 4) + 15) & ~15;
534
535 BATCH_LOCALS(&context->radeon);
536 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
537
538 pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(GL_CONTEXT(context));
539
540 if (!pbo)
541 return;
542
543 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
544
545 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
546 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
547 R600_OUT_BATCH(evergreen->ps.SQ_PGM_START_PS.u32All);
548 R600_OUT_BATCH_RELOC(evergreen->ps.SQ_PGM_START_PS.u32All,
549 pbo,
550 evergreen->ps.SQ_PGM_START_PS.u32All,
551 RADEON_GEM_DOMAIN_GTT, 0, 0);
552 END_BATCH();
553
554 BEGIN_BATCH_NO_AUTOSTATE(3);
555 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LOOP_CONST_0, 0x01000FFF);
556 END_BATCH();
557
558 pbo_const = (struct radeon_bo *)(context->fp_Constbo);
559
560 if(NULL != pbo_const)
561 {
562 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
563
564 BEGIN_BATCH_NO_AUTOSTATE(3);
565 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, const_size / 16);
566 END_BATCH();
567
568 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
569 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_PS_0, 1);
570 R600_OUT_BATCH(context->fp_bo_offset >> 8);
571 R600_OUT_BATCH_RELOC(0,
572 pbo_const,
573 0,
574 RADEON_GEM_DOMAIN_GTT, 0, 0);
575 END_BATCH();
576 }
577
578 COMMIT_BATCH();
579 }
580
581 static void evergreenSendVSresource(struct gl_context *ctx, struct radeon_state_atom *atom)
582 {
583 context_t *context = EVERGREEN_CONTEXT(ctx);
584 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
585 struct radeon_bo * pbo;
586 struct radeon_bo * pbo_const;
587 /* const size reg is in units of 16 consts */
588 int const_size = ((evergreen->vs.num_consts * 4) + 15) & ~15;
589
590 BATCH_LOCALS(&context->radeon);
591 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
592
593 pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(GL_CONTEXT(context));
594
595 if (!pbo)
596 return;
597
598 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
599
600 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
601 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
602 R600_OUT_BATCH(evergreen->vs.SQ_PGM_START_VS.u32All);
603 R600_OUT_BATCH_RELOC(evergreen->vs.SQ_PGM_START_VS.u32All,
604 pbo,
605 evergreen->vs.SQ_PGM_START_VS.u32All,
606 RADEON_GEM_DOMAIN_GTT, 0, 0);
607 END_BATCH();
608
609 BEGIN_BATCH_NO_AUTOSTATE(3);
610 EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + 32*1), 0x0100000F); //consts == 1
611 //EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
612 END_BATCH();
613
614 pbo_const = (struct radeon_bo *)(context->vp_Constbo);
615
616 if(NULL != pbo_const)
617 {
618 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
619
620 BEGIN_BATCH_NO_AUTOSTATE(3);
621 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, const_size / 16);
622 END_BATCH();
623
624 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
625 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_VS_0, 1);
626 R600_OUT_BATCH(context->vp_bo_offset >> 8);
627 R600_OUT_BATCH_RELOC(0,
628 pbo_const,
629 0,
630 RADEON_GEM_DOMAIN_GTT, 0, 0);
631 END_BATCH();
632 }
633
634 COMMIT_BATCH();
635 }
636
637 static void evergreenSendSQ(struct gl_context *ctx, struct radeon_state_atom *atom)
638 {
639 context_t *context = EVERGREEN_CONTEXT(ctx);
640 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
641 BATCH_LOCALS(&context->radeon);
642 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
643
644 evergreenSendPSresource(ctx); //16 entries now
645
646 BEGIN_BATCH_NO_AUTOSTATE(77);
647
648 //34
649 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_VTX_SEMANTIC_0, 32);
650 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_0.u32All); //// // = 0x28380, // SAME
651 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_1.u32All); //// // = 0x28384, // SAME
652 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_2.u32All); //// // = 0x28388, // SAME
653 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_3.u32All); //// // = 0x2838C, // SAME
654 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_4.u32All); //// // = 0x28390, // SAME
655 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_5.u32All); //// // = 0x28394, // SAME
656 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_6.u32All); //// // = 0x28398, // SAME
657 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_7.u32All); //// // = 0x2839C, // SAME
658 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_8.u32All); //// // = 0x283A0, // SAME
659 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_9.u32All); //// // = 0x283A4, // SAME
660 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_10.u32All); //// // = 0x283A8, // SAME
661 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_11.u32All); //// // = 0x283AC, // SAME
662 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_12.u32All); //// // = 0x283B0, // SAME
663 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_13.u32All); //// // = 0x283B4, // SAME
664 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_14.u32All); //// // = 0x283B8, // SAME
665 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_15.u32All); //// // = 0x283BC, // SAME
666 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_16.u32All); //// // = 0x283C0, // SAME
667 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_17.u32All); //// // = 0x283C4, // SAME
668 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_18.u32All); //// // = 0x283C8, // SAME
669 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_19.u32All); //// // = 0x283CC, // SAME
670 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_20.u32All); //// // = 0x283D0, // SAME
671 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_21.u32All); //// // = 0x283D4, // SAME
672 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_22.u32All); //// // = 0x283D8, // SAME
673 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_23.u32All); //// // = 0x283DC, // SAME
674 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_24.u32All); //// // = 0x283E0, // SAME
675 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_25.u32All); //// // = 0x283E4, // SAME
676 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_26.u32All); //// // = 0x283E8, // SAME
677 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_27.u32All); //// // = 0x283EC, // SAME
678 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_28.u32All); //// // = 0x283F0, // SAME
679 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_29.u32All); //// // = 0x283F4, // SAME
680 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_30.u32All); //// // = 0x283F8, // SAME
681 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_31.u32All); //// // = 0x283FC, // SAME
682
683
684 //3
685 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_DYN_GPR_RESOURCE_LIMIT_1, 1);
686 R600_OUT_BATCH(evergreen->SQ_DYN_GPR_RESOURCE_LIMIT_1.u32All);//// // = 0x28838, //
687
688 //5
689 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
690 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_PS.u32All); //// // = 0x28844, // DIFF 0x28850
691 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_PS.u32All); //// // = 0x28848, //
692 R600_OUT_BATCH(evergreen->SQ_PGM_EXPORTS_PS.u32All); //// // = 0x2884C, // SAME 0x28854
693
694 //4
695 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
696 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_VS.u32All);//// // = 0x28860, // DIFF 0x28868
697 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_VS.u32All); //// // = 0x28864, //
698
699 //5
700 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_GS, 2);
701 /*
702 R600_OUT_BATCH(evergreen->SQ_PGM_START_GS.u32All); //// // = 0x28874, // SAME 0x2886C
703 */
704 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_GS.u32All); //// // = 0x28878, // DIFF 0x2887C
705 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_GS.u32All); //// // = 0x2887C, //
706
707 //5
708 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_ES, 2);
709 /*
710 R600_OUT_BATCH(evergreen->SQ_PGM_START_ES.u32All); //// // = 0x2888C, // SAME 0x28880
711 */
712 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_ES.u32All); //// // = 0x28890, // DIFF
713 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_ES.u32All); //// // = 0x28894, //
714
715 //4
716 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_FS, 1);
717 /*
718 R600_OUT_BATCH(evergreen->SQ_PGM_START_FS.u32All); //// // = 0x288A4, // SAME 0x28894
719 */
720 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_FS.u32All); //// // = 0x288A8, // DIFF 0x288A4
721
722 //3
723 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_HS, 1);
724 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_HS.u32All);//// // = 0x288C0, //
725
726 //3
727 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_LS, 1);
728 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_LS.u32All); //// // = 0x288D8, //
729
730 //3
731 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_LDS_ALLOC_PS, 1);
732 R600_OUT_BATCH(evergreen->SQ_LDS_ALLOC_PS.u32All); //// // = 0x288EC, //
733
734 //8
735 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
736 R600_OUT_BATCH(evergreen->SQ_ESGS_RING_ITEMSIZE.u32All); //// // = 0x28900, // SAME 0x288A8
737 R600_OUT_BATCH(evergreen->SQ_GSVS_RING_ITEMSIZE.u32All); //// // = 0x28904, // SAME 0x288AC
738 R600_OUT_BATCH(evergreen->SQ_ESTMP_RING_ITEMSIZE.u32All); //// // = 0x28908, // SAME 0x288B0
739 R600_OUT_BATCH(evergreen->SQ_GSTMP_RING_ITEMSIZE.u32All); //// // = 0x2890C, // SAME 0x288B4
740 R600_OUT_BATCH(evergreen->SQ_VSTMP_RING_ITEMSIZE.u32All); //// // = 0x28910, // SAME 0x288B8
741 R600_OUT_BATCH(evergreen->SQ_PSTMP_RING_ITEMSIZE.u32All); //// // = 0x28914, // SAME 0x288BC
742
743 //3
744 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 1);
745 R600_OUT_BATCH(evergreen->SQ_GS_VERT_ITEMSIZE.u32All); //// // = 0x2891C, // SAME 0x288C8
746
747 END_BATCH();
748
749 COMMIT_BATCH();
750
751 }
752 static void evergreenSendSPI(struct gl_context *ctx, struct radeon_state_atom *atom)
753 {
754 context_t *context = EVERGREEN_CONTEXT(ctx);
755 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
756 BATCH_LOCALS(&context->radeon);
757 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
758
759 BEGIN_BATCH_NO_AUTOSTATE(59);
760
761 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_VS_OUT_ID_0, 10);
762 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_0.u32All);
763 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_1.u32All);
764 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_2.u32All);
765 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_3.u32All);
766 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_4.u32All);
767 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_5.u32All);
768 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_6.u32All);
769 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_7.u32All);
770 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_8.u32All);
771 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_9.u32All);
772
773 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_INPUT_CNTL_0, 45);
774 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[0].u32All);
775 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[1].u32All);
776 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[2].u32All);
777 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[3].u32All);
778 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[4].u32All);
779 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[5].u32All);
780 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[6].u32All);
781 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[7].u32All);
782 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[8].u32All);
783 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[9].u32All);
784 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[10].u32All);
785 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[11].u32All);
786 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[12].u32All);
787 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[13].u32All);
788 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[14].u32All);
789 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[15].u32All);
790 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[16].u32All);
791 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[17].u32All);
792 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[18].u32All);
793 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[19].u32All);
794 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[20].u32All);
795 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[21].u32All);
796 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[22].u32All);
797 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[23].u32All);
798 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[24].u32All);
799 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[25].u32All);
800 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[26].u32All);
801 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[27].u32All);
802 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[28].u32All);
803 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[29].u32All);
804 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[30].u32All);
805 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[31].u32All);
806 R600_OUT_BATCH(evergreen->SPI_VS_OUT_CONFIG.u32All);
807 R600_OUT_BATCH(evergreen->SPI_THREAD_GROUPING.u32All);
808 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_0.u32All);
809 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_1.u32All);
810 R600_OUT_BATCH(evergreen->SPI_INTERP_CONTROL_0.u32All);
811 R600_OUT_BATCH(evergreen->SPI_INPUT_Z.u32All);
812 R600_OUT_BATCH(evergreen->SPI_FOG_CNTL.u32All);
813 R600_OUT_BATCH(evergreen->SPI_BARYC_CNTL.u32All);
814 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_2.u32All);
815 R600_OUT_BATCH(evergreen->SPI_COMPUTE_INPUT_CNTL.u32All);
816 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_X.u32All);
817 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Y.u32All);
818 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Z.u32All);
819
820 END_BATCH();
821
822 COMMIT_BATCH();
823 }
824 static void evergreenSendSX(struct gl_context *ctx, struct radeon_state_atom *atom)
825 {
826 context_t *context = EVERGREEN_CONTEXT(ctx);
827 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
828 BATCH_LOCALS(&context->radeon);
829 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
830
831 BEGIN_BATCH_NO_AUTOSTATE(9);
832
833 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, evergreen->SX_MISC.u32All);
834 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_TEST_CONTROL, evergreen->SX_ALPHA_TEST_CONTROL.u32All);
835 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_REF, evergreen->SX_ALPHA_REF.u32All);
836
837 END_BATCH();
838
839 COMMIT_BATCH();
840 }
841
842 static void evergreenSetDepthTarget(context_t *context)
843 {
844 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
845 struct radeon_renderbuffer *rrb;
846 unsigned int nPitchInPixel, height, offtostencil;
847
848 rrb = radeon_get_depthbuffer(&context->radeon);
849 if (!rrb)
850 {
851 return;
852 }
853
854 EVERGREEN_STATECHANGE(context, db);
855
856 evergreen->DB_DEPTH_SIZE.u32All = 0;
857
858 nPitchInPixel = rrb->pitch/rrb->cpp;
859
860 if (context->radeon.radeonScreen->driScreen->dri2.enabled)
861 {
862 height = rrb->base.Height;
863 }
864 else
865 {
866 height = context->radeon.radeonScreen->driScreen->fbHeight;
867 }
868
869 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
870 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift,
871 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask);
872 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (height/8)-1,
873 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift,
874 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask);
875 evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * height)/64 )-1;
876
877 if(4 == rrb->cpp)
878 {
879 SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_24,
880 EG_DB_Z_INFO__FORMAT_shift,
881 EG_DB_Z_INFO__FORMAT_mask);
882 }
883 else
884 {
885 SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_16,
886 EG_DB_Z_INFO__FORMAT_shift,
887 EG_DB_Z_INFO__FORMAT_mask);
888 }
889 SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
890 EG_DB_Z_INFO__ARRAY_MODE_shift,
891 EG_DB_Z_INFO__ARRAY_MODE_mask);
892
893
894 offtostencil = ((height * rrb->pitch) + 255) & ~255;
895 evergreen->DB_STENCIL_WRITE_BASE.u32All = offtostencil >> 8;
896 evergreen->DB_STENCIL_READ_BASE.u32All = offtostencil >> 8;
897
898 }
899
900 static void evergreenSendDB(struct gl_context *ctx, struct radeon_state_atom *atom)
901 {
902 context_t *context = EVERGREEN_CONTEXT(ctx);
903 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
904 struct radeon_renderbuffer *rrb;
905 BATCH_LOCALS(&context->radeon);
906 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
907
908 evergreenSetDepthTarget(context);
909
910 //8
911 BEGIN_BATCH_NO_AUTOSTATE(7);
912 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
913 R600_OUT_BATCH(evergreen->DB_RENDER_CONTROL.u32All);
914 R600_OUT_BATCH(evergreen->DB_COUNT_CONTROL.u32All);
915 R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All);
916 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All);
917 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All);
918 END_BATCH();
919
920 //4
921 BEGIN_BATCH_NO_AUTOSTATE(4);
922 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
923 R600_OUT_BATCH(evergreen->DB_STENCIL_CLEAR.u32All);
924 R600_OUT_BATCH(evergreen->DB_DEPTH_CLEAR.u32All);
925 END_BATCH();
926
927 //4
928 BEGIN_BATCH_NO_AUTOSTATE(4);
929 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_DEPTH_SIZE, 2);
930 R600_OUT_BATCH(evergreen->DB_DEPTH_SIZE.u32All);
931 R600_OUT_BATCH(evergreen->DB_DEPTH_SLICE.u32All);
932 END_BATCH();
933
934 //3
935 BEGIN_BATCH_NO_AUTOSTATE(3);
936 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, evergreen->DB_DEPTH_CONTROL.u32All);
937 END_BATCH();
938
939 //3
940 BEGIN_BATCH_NO_AUTOSTATE(3);
941 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_SHADER_CONTROL, evergreen->DB_SHADER_CONTROL.u32All);
942 END_BATCH();
943
944 //5
945 BEGIN_BATCH_NO_AUTOSTATE(5);
946 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_SRESULTS_COMPARE_STATE0, 3);
947 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE0.u32All);
948 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE1.u32All);
949 R600_OUT_BATCH(evergreen->DB_PRELOAD_CONTROL.u32All);
950 END_BATCH();
951
952 //3
953 BEGIN_BATCH_NO_AUTOSTATE(3);
954 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, evergreen->DB_ALPHA_TO_MASK.u32All);
955 END_BATCH();
956
957 rrb = radeon_get_depthbuffer(&context->radeon);
958
959 if( (rrb != NULL) && (rrb->bo != NULL) )
960 {
961
962 /* make the hw happy */
963 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
964 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All);
965 R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All,
966 rrb->bo,
967 evergreen->DB_HTILE_DATA_BASE.u32All,
968 0, RADEON_GEM_DOMAIN_VRAM, 0);
969 END_BATCH();
970
971 //5
972 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
973 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All);
974 R600_OUT_BATCH_RELOC(evergreen->DB_Z_INFO.u32All,
975 rrb->bo,
976 evergreen->DB_Z_INFO.u32All,
977 0, RADEON_GEM_DOMAIN_VRAM, 0);
978 END_BATCH();
979
980 //5
981 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_ENABLE_bit) > 0)
982 {
983 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
984 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_READ_BASE, evergreen->DB_Z_READ_BASE.u32All);
985 R600_OUT_BATCH_RELOC(evergreen->DB_Z_READ_BASE.u32All,
986 rrb->bo,
987 evergreen->DB_Z_READ_BASE.u32All,
988 0, RADEON_GEM_DOMAIN_VRAM, 0);
989 END_BATCH();
990 }
991 //5
992 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_WRITE_ENABLE_bit) > 0)
993 {
994 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
995 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_WRITE_BASE, evergreen->DB_Z_READ_BASE.u32All);
996 R600_OUT_BATCH_RELOC(evergreen->DB_Z_WRITE_BASE.u32All,
997 rrb->bo,
998 evergreen->DB_Z_WRITE_BASE.u32All,
999 0, RADEON_GEM_DOMAIN_VRAM, 0);
1000 END_BATCH();
1001 }
1002 }
1003
1004 if (ctx->DrawBuffer)
1005 {
1006 rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
1007
1008 if((rrb != NULL) && (rrb->bo != NULL))
1009 {
1010 //5
1011 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1012 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_STENCIL_INFO.u32All);
1013 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All,
1014 rrb->bo,
1015 evergreen->DB_STENCIL_INFO.u32All,
1016 0, RADEON_GEM_DOMAIN_VRAM, 0);
1017 END_BATCH();
1018
1019 //4
1020 BEGIN_BATCH_NO_AUTOSTATE(4);
1021 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
1022 R600_OUT_BATCH(evergreen->DB_STENCILREFMASK.u32All);
1023 R600_OUT_BATCH(evergreen->DB_STENCILREFMASK_BF.u32All);
1024 END_BATCH();
1025 //------------------------
1026
1027 //10
1028 if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
1029 {
1030
1031 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1032 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
1033 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
1034 rrb->bo,
1035 evergreen->DB_STENCIL_READ_BASE.u32All,
1036 0, RADEON_GEM_DOMAIN_VRAM, 0);
1037 END_BATCH();
1038
1039 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1040 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
1041 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
1042 rrb->bo,
1043 evergreen->DB_STENCIL_WRITE_BASE.u32All,
1044 0, RADEON_GEM_DOMAIN_VRAM, 0);
1045 END_BATCH();
1046 }
1047 }
1048 }
1049
1050 COMMIT_BATCH();
1051 }
1052
1053 static void evergreenSetRenderTarget(context_t *context, int id)
1054 {
1055 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1056 uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM, source_format = 1;
1057 struct radeon_renderbuffer *rrb;
1058 unsigned int nPitchInPixel, height;
1059
1060 rrb = radeon_get_colorbuffer(&context->radeon);
1061 if (!rrb || !rrb->bo) {
1062 return;
1063 }
1064
1065 EVERGREEN_STATECHANGE(context, cb);
1066
1067 /* addr */
1068 evergreen->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
1069
1070 /* pitch */
1071 nPitchInPixel = rrb->pitch/rrb->cpp;
1072
1073 if (context->radeon.radeonScreen->driScreen->dri2.enabled)
1074 {
1075 height = rrb->base.Height;
1076 }
1077 else
1078 {
1079 height = context->radeon.radeonScreen->driScreen->fbHeight;
1080 }
1081
1082 SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1,
1083 EG_CB_COLOR0_PITCH__TILE_MAX_shift,
1084 EG_CB_COLOR0_PITCH__TILE_MAX_mask);
1085
1086 /* slice */
1087 SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All,
1088 ( (nPitchInPixel * height)/64 )-1,
1089 EG_CB_COLOR0_SLICE__TILE_MAX_shift,
1090 EG_CB_COLOR0_SLICE__TILE_MAX_mask);
1091
1092 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
1093 SETbit(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All,
1094 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
1095
1096 /* CB_COLOR0_INFO */
1097 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1098 ENDIAN_NONE,
1099 EG_CB_COLOR0_INFO__ENDIAN_shift,
1100 EG_CB_COLOR0_INFO__ENDIAN_mask);
1101 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1102 ARRAY_LINEAR_GENERAL,
1103 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1104 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1105
1106 switch (rrb->base.Format) {
1107 case MESA_FORMAT_RGBA8888:
1108 format = COLOR_8_8_8_8;
1109 comp_swap = SWAP_STD_REV;
1110 number_type = NUMBER_UNORM;
1111 source_format = 1;
1112 break;
1113 case MESA_FORMAT_SIGNED_RGBA8888:
1114 format = COLOR_8_8_8_8;
1115 comp_swap = SWAP_STD_REV;
1116 number_type = NUMBER_SNORM;
1117 source_format = 1;
1118 break;
1119 case MESA_FORMAT_RGBA8888_REV:
1120 format = COLOR_8_8_8_8;
1121 comp_swap = SWAP_STD;
1122 number_type = NUMBER_UNORM;
1123 source_format = 1;
1124 break;
1125 case MESA_FORMAT_SIGNED_RGBA8888_REV:
1126 format = COLOR_8_8_8_8;
1127 comp_swap = SWAP_STD;
1128 number_type = NUMBER_SNORM;
1129 source_format = 1;
1130 break;
1131 case MESA_FORMAT_ARGB8888:
1132 case MESA_FORMAT_XRGB8888:
1133 format = COLOR_8_8_8_8;
1134 comp_swap = SWAP_ALT;
1135 number_type = NUMBER_UNORM;
1136 source_format = 1;
1137 break;
1138 case MESA_FORMAT_ARGB8888_REV:
1139 case MESA_FORMAT_XRGB8888_REV:
1140 format = COLOR_8_8_8_8;
1141 comp_swap = SWAP_ALT_REV;
1142 number_type = NUMBER_UNORM;
1143 source_format = 1;
1144 break;
1145 case MESA_FORMAT_RGB565:
1146 format = COLOR_5_6_5;
1147 comp_swap = SWAP_STD_REV;
1148 number_type = NUMBER_UNORM;
1149 source_format = 1;
1150 break;
1151 case MESA_FORMAT_RGB565_REV:
1152 format = COLOR_5_6_5;
1153 comp_swap = SWAP_STD;
1154 number_type = NUMBER_UNORM;
1155 source_format = 1;
1156 break;
1157 case MESA_FORMAT_ARGB4444:
1158 format = COLOR_4_4_4_4;
1159 comp_swap = SWAP_ALT;
1160 number_type = NUMBER_UNORM;
1161 source_format = 1;
1162 break;
1163 case MESA_FORMAT_ARGB4444_REV:
1164 format = COLOR_4_4_4_4;
1165 comp_swap = SWAP_ALT_REV;
1166 number_type = NUMBER_UNORM;
1167 source_format = 1;
1168 break;
1169 case MESA_FORMAT_ARGB1555:
1170 format = COLOR_1_5_5_5;
1171 comp_swap = SWAP_ALT;
1172 number_type = NUMBER_UNORM;
1173 source_format = 1;
1174 break;
1175 case MESA_FORMAT_ARGB1555_REV:
1176 format = COLOR_1_5_5_5;
1177 comp_swap = SWAP_ALT_REV;
1178 number_type = NUMBER_UNORM;
1179 source_format = 1;
1180 break;
1181 case MESA_FORMAT_AL88:
1182 format = COLOR_8_8;
1183 comp_swap = SWAP_STD;
1184 number_type = NUMBER_UNORM;
1185 source_format = 1;
1186 break;
1187 case MESA_FORMAT_AL88_REV:
1188 format = COLOR_8_8;
1189 comp_swap = SWAP_STD_REV;
1190 number_type = NUMBER_UNORM;
1191 source_format = 1;
1192 break;
1193 case MESA_FORMAT_RGB332:
1194 format = COLOR_3_3_2;
1195 comp_swap = SWAP_STD_REV;
1196 number_type = NUMBER_UNORM;
1197 source_format = 1;
1198 break;
1199 case MESA_FORMAT_A8:
1200 format = COLOR_8;
1201 comp_swap = SWAP_ALT_REV;
1202 number_type = NUMBER_UNORM;
1203 source_format = 1;
1204 break;
1205 case MESA_FORMAT_I8:
1206 case MESA_FORMAT_CI8:
1207 format = COLOR_8;
1208 comp_swap = SWAP_STD;
1209 number_type = NUMBER_UNORM;
1210 source_format = 1;
1211 break;
1212 case MESA_FORMAT_L8:
1213 format = COLOR_8;
1214 comp_swap = SWAP_ALT;
1215 number_type = NUMBER_UNORM;
1216 source_format = 1;
1217 break;
1218 case MESA_FORMAT_RGBA_FLOAT32:
1219 format = COLOR_32_32_32_32_FLOAT;
1220 comp_swap = SWAP_STD_REV;
1221 number_type = NUMBER_FLOAT;
1222 source_format = 0;
1223 break;
1224 case MESA_FORMAT_RGBA_FLOAT16:
1225 format = COLOR_16_16_16_16_FLOAT;
1226 comp_swap = SWAP_STD_REV;
1227 number_type = NUMBER_FLOAT;
1228 source_format = 0;
1229 break;
1230 case MESA_FORMAT_ALPHA_FLOAT32:
1231 format = COLOR_32_FLOAT;
1232 comp_swap = SWAP_ALT_REV;
1233 number_type = NUMBER_FLOAT;
1234 source_format = 0;
1235 break;
1236 case MESA_FORMAT_ALPHA_FLOAT16:
1237 format = COLOR_16_FLOAT;
1238 comp_swap = SWAP_ALT_REV;
1239 number_type = NUMBER_FLOAT;
1240 source_format = 0;
1241 break;
1242 case MESA_FORMAT_LUMINANCE_FLOAT32:
1243 format = COLOR_32_FLOAT;
1244 comp_swap = SWAP_ALT;
1245 number_type = NUMBER_FLOAT;
1246 source_format = 0;
1247 break;
1248 case MESA_FORMAT_LUMINANCE_FLOAT16:
1249 format = COLOR_16_FLOAT;
1250 comp_swap = SWAP_ALT;
1251 number_type = NUMBER_FLOAT;
1252 source_format = 0;
1253 break;
1254 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
1255 format = COLOR_32_32_FLOAT;
1256 comp_swap = SWAP_ALT_REV;
1257 number_type = NUMBER_FLOAT;
1258 source_format = 0;
1259 break;
1260 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
1261 format = COLOR_16_16_FLOAT;
1262 comp_swap = SWAP_ALT_REV;
1263 number_type = NUMBER_FLOAT;
1264 source_format = 0;
1265 break;
1266 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
1267 format = COLOR_32_FLOAT;
1268 comp_swap = SWAP_STD;
1269 number_type = NUMBER_FLOAT;
1270 source_format = 0;
1271 break;
1272 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
1273 format = COLOR_16_FLOAT;
1274 comp_swap = SWAP_STD;
1275 number_type = NUMBER_UNORM;
1276 source_format = 0;
1277 break;
1278 case MESA_FORMAT_X8_Z24:
1279 case MESA_FORMAT_S8_Z24:
1280 format = COLOR_8_24;
1281 comp_swap = SWAP_STD;
1282 number_type = NUMBER_UNORM;
1283 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1284 ARRAY_1D_TILED_THIN1,
1285 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1286 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1287 source_format = 0;
1288 break;
1289 case MESA_FORMAT_Z24_S8:
1290 format = COLOR_24_8;
1291 comp_swap = SWAP_STD;
1292 number_type = NUMBER_UNORM;
1293 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1294 ARRAY_1D_TILED_THIN1,
1295 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1296 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1297 source_format = 0;
1298 break;
1299 case MESA_FORMAT_Z16:
1300 format = COLOR_16;
1301 comp_swap = SWAP_STD;
1302 number_type = NUMBER_UNORM;
1303 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1304 ARRAY_1D_TILED_THIN1,
1305 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1306 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1307 source_format = 0;
1308 break;
1309 case MESA_FORMAT_Z32:
1310 format = COLOR_32;
1311 comp_swap = SWAP_STD;
1312 number_type = NUMBER_UNORM;
1313 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1314 ARRAY_1D_TILED_THIN1,
1315 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1316 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1317 source_format = 0;
1318 break;
1319 case MESA_FORMAT_SARGB8:
1320 format = COLOR_8_8_8_8;
1321 comp_swap = SWAP_ALT;
1322 number_type = NUMBER_SRGB;
1323 source_format = 1;
1324 break;
1325 case MESA_FORMAT_SLA8:
1326 format = COLOR_8_8;
1327 comp_swap = SWAP_ALT_REV;
1328 number_type = NUMBER_SRGB;
1329 source_format = 1;
1330 break;
1331 case MESA_FORMAT_SL8:
1332 format = COLOR_8;
1333 comp_swap = SWAP_ALT_REV;
1334 number_type = NUMBER_SRGB;
1335 source_format = 1;
1336 break;
1337 default:
1338 _mesa_problem(context->radeon.glCtx, "unexpected format in evergreenSetRenderTarget()");
1339 break;
1340 }
1341
1342 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1343 format,
1344 EG_CB_COLOR0_INFO__FORMAT_shift,
1345 EG_CB_COLOR0_INFO__FORMAT_mask);
1346 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1347 comp_swap,
1348 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1349 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1350 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1351 number_type,
1352 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
1353 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
1354 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1355 source_format,
1356 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
1357 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
1358 SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1359 EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
1360
1361 evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
1362 evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
1363 evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
1364 evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
1365
1366 evergreen->render_target[id].enabled = GL_TRUE;
1367 }
1368
1369 static void evergreenSendCB(struct gl_context *ctx, struct radeon_state_atom *atom)
1370 {
1371 context_t *context = EVERGREEN_CONTEXT(ctx);
1372 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1373 struct radeon_renderbuffer *rrb;
1374 BATCH_LOCALS(&context->radeon);
1375 int id = 0;
1376 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1377
1378 rrb = radeon_get_colorbuffer(&context->radeon);
1379 if (!rrb || !rrb->bo) {
1380 return;
1381 }
1382
1383 evergreenSetRenderTarget(context, 0);
1384
1385 if (!evergreen->render_target[id].enabled)
1386 return;
1387
1388 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1389 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
1390 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_BASE.u32All);
1391 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1392 rrb->bo,
1393 evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1394 0, RADEON_GEM_DOMAIN_VRAM, 0);
1395 END_BATCH();
1396
1397 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1398 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, evergreen->render_target[id].CB_COLOR0_INFO.u32All);
1399 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1400 rrb->bo,
1401 evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1402 0, RADEON_GEM_DOMAIN_VRAM, 0);
1403 END_BATCH();
1404
1405 BEGIN_BATCH_NO_AUTOSTATE(5);
1406 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
1407 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_PITCH.u32All);
1408 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_SLICE.u32All);
1409 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_VIEW.u32All);
1410 END_BATCH();
1411
1412 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1413 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 1);
1414 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All);
1415 R600_OUT_BATCH_RELOC(0,
1416 rrb->bo,
1417 0,
1418 0, RADEON_GEM_DOMAIN_VRAM, 0);
1419 END_BATCH();
1420
1421 BEGIN_BATCH_NO_AUTOSTATE(3);
1422 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_DIM, 1);
1423 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_DIM.u32All);
1424 /*
1425 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
1426 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
1427 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
1428 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
1429 */
1430 END_BATCH();
1431
1432 BEGIN_BATCH_NO_AUTOSTATE(4);
1433 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_TARGET_MASK, 2);
1434 R600_OUT_BATCH(evergreen->CB_TARGET_MASK.u32All);
1435 R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All);
1436 END_BATCH();
1437
1438 BEGIN_BATCH_NO_AUTOSTATE(6);
1439 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 4);
1440 R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All);
1441 R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All);
1442 R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All);
1443 R600_OUT_BATCH(evergreen->CB_BLEND_ALPHA.u32All);
1444 END_BATCH();
1445
1446 BEGIN_BATCH_NO_AUTOSTATE(6);
1447 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All);
1448 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All);
1449 END_BATCH();
1450
1451 COMMIT_BATCH();
1452 }
1453
1454 static void evergreenSendVGT(struct gl_context *ctx, struct radeon_state_atom *atom)
1455 {
1456 context_t *context = EVERGREEN_CONTEXT(ctx);
1457 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1458 BATCH_LOCALS(&context->radeon);
1459 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1460
1461 /* moved to draw:
1462 VGT_DRAW_INITIATOR
1463 VGT_INDEX_TYPE
1464 VGT_PRIMITIVE_TYPE
1465 */
1466 BEGIN_BATCH_NO_AUTOSTATE(5);
1467 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 3);
1468 R600_OUT_BATCH(evergreen->VGT_MAX_VTX_INDX.u32All);
1469 R600_OUT_BATCH(evergreen->VGT_MIN_VTX_INDX.u32All);
1470 R600_OUT_BATCH(evergreen->VGT_INDX_OFFSET.u32All);
1471 END_BATCH();
1472
1473 BEGIN_BATCH_NO_AUTOSTATE(6);
1474 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_OUTPUT_PATH_CNTL, evergreen->VGT_OUTPUT_PATH_CNTL.u32All);
1475
1476 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_GS_MODE, evergreen->VGT_GS_MODE.u32All);
1477 END_BATCH();
1478
1479 BEGIN_BATCH_NO_AUTOSTATE(3);
1480 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVEID_EN, 1);
1481 R600_OUT_BATCH(evergreen->VGT_PRIMITIVEID_EN.u32All);
1482 END_BATCH();
1483
1484 BEGIN_BATCH_NO_AUTOSTATE(4);
1485 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1486 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_0.u32All);
1487 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_1.u32All);
1488 END_BATCH();
1489
1490 BEGIN_BATCH_NO_AUTOSTATE(4);
1491 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1492 R600_OUT_BATCH(evergreen->VGT_REUSE_OFF.u32All);
1493 R600_OUT_BATCH(evergreen->VGT_VTX_CNT_EN.u32All);
1494 END_BATCH();
1495
1496 BEGIN_BATCH_NO_AUTOSTATE(3);
1497 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, evergreen->VGT_SHADER_STAGES_EN.u32All);
1498 END_BATCH();
1499
1500 BEGIN_BATCH_NO_AUTOSTATE(4);
1501 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1502 R600_OUT_BATCH(evergreen->VGT_STRMOUT_CONFIG.u32All);
1503 R600_OUT_BATCH(evergreen->VGT_STRMOUT_BUFFER_CONFIG.u32All);
1504 END_BATCH();
1505
1506 COMMIT_BATCH();
1507 }
1508
1509 void evergreenInitAtoms(context_t *context)
1510 {
1511 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1512 context->radeon.hw.max_state_size = 10 + 5 + 14 + 3; /* start 3d, idle, cb/db flush, 3 for time stamp */
1513
1514 /* Setup the atom linked list */
1515 make_empty_list(&context->radeon.hw.atomlist);
1516 context->radeon.hw.atomlist.name = "atom-list";
1517
1518 EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
1519 EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (VERT_ATTRIB_MAX * 12), evergreenSendVTX);
1520 EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA);
1521 EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP);
1522 EVERGREEN_ALLOC_STATE(sq, always, 86, evergreenSendSQ); /* 85 */
1523 EVERGREEN_ALLOC_STATE(vs, always, 16, evergreenSendVSresource);
1524 EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI);
1525 EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX);
1526 EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */
1527 EVERGREEN_ALLOC_STATE(db, always, 69, evergreenSendDB);
1528 EVERGREEN_ALLOC_STATE(cb, always, 37, evergreenSendCB);
1529 EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
1530
1531 evergreen_init_query_stateobj(&context->radeon, 6 * 2);
1532
1533 context->radeon.hw.is_dirty = GL_TRUE;
1534 context->radeon.hw.all_dirty = GL_TRUE;
1535 }