projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
evergreen : initial support driver code.
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_chip.c
1 /*
2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/imports.h"
28 #include "main/glheader.h"
29 #include "main/simple_list.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "evergreen_tex.h"
35 #include "evergreen_chip.h"
36 #include "evergreen_off.h"
37 #include "evergreen_diff.h"
38 #include "evergreen_fragprog.h"
39 #include "evergreen_vertprog.h"
40
41 #include "radeon_mipmap_tree.h"
42
43 void evergreenCreateChip(context_t *context)
44 {
45 EVERGREEN_CHIP_CONTEXT * evergreen =
46 (EVERGREEN_CHIP_CONTEXT*) CALLOC(sizeof(EVERGREEN_CHIP_CONTEXT));
47
48 context->pChip = (void*)evergreen;
49 }
50
51 #define EVERGREEN_ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
52 do { \
53 context->evergreen_atoms.ATOM.cmd_size = (SZ); \
54 context->evergreen_atoms.ATOM.cmd = NULL; \
55 context->evergreen_atoms.ATOM.name = #ATOM; \
56 context->evergreen_atoms.ATOM.idx = 0; \
57 context->evergreen_atoms.ATOM.check = check_##CHK; \
58 context->evergreen_atoms.ATOM.dirty = GL_FALSE; \
59 context->evergreen_atoms.ATOM.emit = (EMIT); \
60 context->radeon.hw.max_state_size += (SZ); \
61 insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
62 } while (0)
63
64 /*
65 static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
66 {
67 radeon->query.queryobj.cmd_size = (SZ);
68 radeon->query.queryobj.cmd = NULL;
69 radeon->query.queryobj.name = "queryobj";
70 radeon->query.queryobj.idx = 0;
71 radeon->query.queryobj.check = check_queryobj;
72 radeon->query.queryobj.dirty = GL_FALSE;
73 radeon->query.queryobj.emit = r700SendQueryBegin;
74 radeon->hw.max_state_size += (SZ);
75 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
76 }
77 */
78
79 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
80 {
81 return atom->cmd_size;
82 }
83
84 static void evergreenSendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
85 {
86 context_t *context = EVERGREEN_CONTEXT(ctx);
87 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
88
89 struct evergreen_vertex_program *vp = context->selected_vp;
90
91 struct radeon_bo *bo = NULL;
92 unsigned int i;
93 unsigned int nBorderSet = 0;
94 BATCH_LOCALS(&context->radeon);
95
96 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
97
98 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
99 if (ctx->Texture.Unit[i]._ReallyEnabled) {
100 radeonTexObj *t = evergreen->textures[i];
101
102 if (t) {
103 /* Tex resource */
104 if (!t->image_override) {
105 bo = t->mt->bo;
106 } else {
107 bo = t->bo;
108 }
109 if (bo)
110 {
111 radeon_bo_unmap(bo);
112
113 r700SyncSurf(context, bo,
114 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
115 0, TC_ACTION_ENA_bit);
116
117 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
118 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
119
120 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
121 { /* vs texture */
122 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
123 }
124 else
125 {
126 R600_OUT_BATCH(i * EG_FETCH_RESOURCE_STRIDE);
127 }
128
129 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE0);
130 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE1);
131 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE2);
132 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE3);
133 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE4);
134 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE5);
135 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE6);
136 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE7);
137
138 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE2,
139 bo,
140 evergreen->textures[i]->SQ_TEX_RESOURCE2,
141 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
142 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE3,
143 bo,
144 evergreen->textures[i]->SQ_TEX_RESOURCE3,
145 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
146 END_BATCH();
147 COMMIT_BATCH();
148 }
149 /* Tex sampler */
150 BEGIN_BATCH_NO_AUTOSTATE(5);
151 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
152
153 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
154 { /* vs texture */
155 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * 3);
156 }
157 else
158 {
159 R600_OUT_BATCH(i * 3);
160 }
161 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER0);
162 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER1);
163 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER2);
164
165 END_BATCH();
166 COMMIT_BATCH();
167
168 /* Tex border color */
169 if(0 == nBorderSet)
170 {
171 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
172 R600_OUT_BATCH_REGSEQ(EG_TD_PS_BORDER_COLOR_RED, 4);
173 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
174 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
175 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
176 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
177 END_BATCH();
178 COMMIT_BATCH();
179
180 nBorderSet = 1;
181 }
182 }
183 }
184 }
185 }
186
187 static int check_evergreen_tx(GLcontext *ctx, struct radeon_state_atom *atom)
188 {
189 context_t *context = EVERGREEN_CONTEXT(ctx);
190 unsigned int i, count = 0;
191 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
192
193 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
194 if (ctx->Texture.Unit[i]._ReallyEnabled) {
195 radeonTexObj *t = evergreen->textures[i];
196 if (t)
197 count++;
198 }
199 }
200 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
201 return count * 37 + 6;
202 }
203
204 static void evergreenSendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
205 {
206 context_t *context = EVERGREEN_CONTEXT(ctx);
207 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
208 BATCH_LOCALS(&context->radeon);
209 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
210
211 BEGIN_BATCH_NO_AUTOSTATE(19);
212 //6
213 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL, evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All);
214 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL_1, evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All);
215 //6
216 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
217 R600_OUT_BATCH(evergreen->evergreen_config.SQ_CONFIG.u32All);
218 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
219 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
220 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All);
221 //7
222 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
223 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All);
224 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All);
225 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
226 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
227 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All);
228
229 END_BATCH();
230
231 COMMIT_BATCH();
232 }
233
234 extern int evergreen_getTypeSize(GLenum type);
235 static void evergreenSetupVTXConstants(GLcontext * ctx,
236 void * pAos,
237 StreamDesc * pStreamDesc)
238 {
239 context_t *context = EVERGREEN_CONTEXT(ctx);
240 struct radeon_aos * paos = (struct radeon_aos *)pAos;
241 unsigned int nVBsize;
242 BATCH_LOCALS(&context->radeon);
243
244 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
245 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
246 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
247 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
248 unsigned int uSQ_VTX_CONSTANT_WORD7_0 = 0;
249
250 if (!paos->bo)
251 return;
252
253 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
254
255 if(0 == pStreamDesc->stride)
256 {
257 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
258 }
259 else
260 {
261 nVBsize = (paos->count - 1) * pStreamDesc->stride
262 + pStreamDesc->size * getTypeSize(pStreamDesc->type);
263 }
264
265 //uSQ_VTX_CONSTANT_WORD0_0
266 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
267
268 //uSQ_VTX_CONSTANT_WORD1_0
269 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize;
270
271 //uSQ_VTX_CONSTANT_WORD2_0
272 SETfield(uSQ_VTX_CONSTANT_WORD2_0,
273 pStreamDesc->stride,
274 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
275 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
276 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
277 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
278 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
279 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
280 if(GL_TRUE == pStreamDesc->normalize)
281 {
282 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
283 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
284 }
285 else
286 {
287 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
288 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
289 }
290 if(1 == pStreamDesc->_signed)
291 {
292 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
293 }
294
295 //uSQ_VTX_CONSTANT_WORD3_0
296 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_X,
297 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
298 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
299 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Y,
300 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
301 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
302 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Z,
303 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
304 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
305 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_W,
306 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
307 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
308
309 //uSQ_VTX_CONSTANT_WORD7_0
310 SETfield(uSQ_VTX_CONSTANT_WORD7_0, SQ_TEX_VTX_VALID_BUFFER,
311 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
312
313 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
314
315 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
316 R600_OUT_BATCH((pStreamDesc->element + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
317 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
318 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
319 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
320 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
321 R600_OUT_BATCH(0);
322 R600_OUT_BATCH(0);
323 R600_OUT_BATCH(0);
324 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD7_0);
325 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
326 paos->bo,
327 uSQ_VTX_CONSTANT_WORD0_0,
328 RADEON_GEM_DOMAIN_GTT, 0, 0);
329 END_BATCH();
330
331 COMMIT_BATCH();
332 }
333
334 static int check_evergreen_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
335 {
336 context_t *context = EVERGREEN_CONTEXT(ctx);
337 int count = context->radeon.tcl.aos_count * 12;
338
339 if (count)
340 count += 6;
341
342 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
343 return count;
344 }
345
346 static void evergreenSendVTX(GLcontext *ctx, struct radeon_state_atom *atom)
347 {
348 context_t *context = EVERGREEN_CONTEXT(ctx);
349 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
350 unsigned int i, j = 0;
351 BATCH_LOCALS(&context->radeon);
352 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
353
354 if (context->radeon.tcl.aos_count == 0)
355 return;
356
357 BEGIN_BATCH_NO_AUTOSTATE(6);
358 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
359 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
360 R600_OUT_BATCH(0);
361
362 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
363 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
364 R600_OUT_BATCH(0);
365 END_BATCH();
366 COMMIT_BATCH();
367
368 for(i=0; i<VERT_ATTRIB_MAX; i++) {
369 if(vp->mesa_program->Base.InputsRead & (1 << i))
370 {
371 evergreenSetupVTXConstants(ctx,
372 (void*)(&context->radeon.tcl.aos[j]),
373 &(context->stream_desc[j]));
374 j++;
375 }
376 }
377 }
378 static void evergreenSendPA(GLcontext *ctx, struct radeon_state_atom *atom)
379 {
380 context_t *context = EVERGREEN_CONTEXT(ctx);
381 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
382 BATCH_LOCALS(&context->radeon);
383 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
384 int id = 0;
385
386 BEGIN_BATCH_NO_AUTOSTATE(3);
387 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
388 END_BATCH();
389
390 BEGIN_BATCH_NO_AUTOSTATE(22);
391 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
392 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All);
393 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All);
394
395 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 12);
396 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_OFFSET.u32All);
397 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All);
398 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All);
399 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_RULE.u32All);
400 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_TL.u32All);
401 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_BR.u32All);
402 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_TL.u32All);
403 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_BR.u32All);
404 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_TL.u32All);
405 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_BR.u32All);
406 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_TL.u32All);
407 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_BR.u32All);
408
409 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
410 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All);
411 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All);
412 END_BATCH();
413
414 BEGIN_BATCH_NO_AUTOSTATE(3);
415 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SC_EDGERULE, evergreen->PA_SC_EDGERULE.u32All);
416 END_BATCH();
417
418
419 BEGIN_BATCH_NO_AUTOSTATE(18);
420 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 4);
421 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
422 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
423 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
424 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
425
426 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
427 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
428 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
429
430 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_VPORT_XSCALE, 6);
431 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XSCALE.u32All);
432 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
433 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YSCALE.u32All);
434 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
435 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
436 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
437 END_BATCH();
438
439
440 for (id = 0; id < EVERGREEN_MAX_UCP; id++) {
441 if (evergreen->ucp[id].enabled) {
442 BEGIN_BATCH_NO_AUTOSTATE(6);
443 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_UCP_0_X + (4 * id), 4);
444 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_X.u32All);
445 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Y.u32All);
446 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Z.u32All);
447 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_W.u32All);
448 END_BATCH();
449 }
450 }
451
452 BEGIN_BATCH_NO_AUTOSTATE(42);
453 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_CLIP_CNTL, 5);
454 R600_OUT_BATCH(evergreen->PA_CL_CLIP_CNTL.u32All);
455 R600_OUT_BATCH(evergreen->PA_SU_SC_MODE_CNTL.u32All);
456 R600_OUT_BATCH(evergreen->PA_CL_VTE_CNTL.u32All);
457 R600_OUT_BATCH(evergreen->PA_CL_VS_OUT_CNTL.u32All);
458 R600_OUT_BATCH(evergreen->PA_CL_NANINF_CNTL.u32All);
459
460 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 3);
461 R600_OUT_BATCH(evergreen->PA_SU_POINT_SIZE.u32All);
462 R600_OUT_BATCH(evergreen->PA_SU_POINT_MINMAX.u32All);
463 R600_OUT_BATCH(evergreen->PA_SU_LINE_CNTL.u32All);
464
465 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
466 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_0.u32All);
467 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_1.u32All);
468
469 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
470 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
471 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_CLAMP.u32All);
472 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
473 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
474 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
475 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
476
477 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
478 R600_OUT_BATCH(evergreen->PA_SC_LINE_CNTL.u32All);
479 R600_OUT_BATCH(evergreen->PA_SC_AA_CONFIG.u32All);
480 R600_OUT_BATCH(evergreen->PA_SU_VTX_CNTL.u32All);
481 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All);
482 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All);
483 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
484 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All);
485 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_0.u32All);
486 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_1.u32All);
487 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_2.u32All);
488 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_3.u32All);
489 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_4.u32All);
490 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_5.u32All);
491 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_6.u32All);
492 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_7.u32All);
493 R600_OUT_BATCH(evergreen->PA_SC_AA_MASK.u32All);
494
495 END_BATCH();
496
497 COMMIT_BATCH();
498 }
499 static void evergreenSendTP(GLcontext *ctx, struct radeon_state_atom *atom)
500 {
501 /*
502 context_t *context = EVERGREEN_CONTEXT(ctx);
503 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
504 BATCH_LOCALS(&context->radeon);
505 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
506
507 COMMIT_BATCH();
508 */
509 }
510
511 static void evergreenSendPSresource(GLcontext *ctx)
512 {
513 context_t *context = EVERGREEN_CONTEXT(ctx);
514 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
515 struct radeon_bo * pbo;
516
517 struct radeon_bo * pbo_const;
518
519 BATCH_LOCALS(&context->radeon);
520 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
521
522 pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(GL_CONTEXT(context));
523
524 if (!pbo)
525 return;
526
527 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
528
529 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
530 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
531 R600_OUT_BATCH(evergreen->ps.SQ_PGM_START_PS.u32All);
532 R600_OUT_BATCH_RELOC(evergreen->ps.SQ_PGM_START_PS.u32All,
533 pbo,
534 evergreen->ps.SQ_PGM_START_PS.u32All,
535 RADEON_GEM_DOMAIN_GTT, 0, 0);
536 END_BATCH();
537
538 BEGIN_BATCH_NO_AUTOSTATE(3);
539 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LOOP_CONST_0, 0x01000FFF);
540 END_BATCH();
541
542 pbo_const = (struct radeon_bo *)(context->fp_Constbo);
543
544 if(NULL != pbo_const)
545 {
546 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
547
548 BEGIN_BATCH_NO_AUTOSTATE(3);
549
550 if(evergreen->ps.num_consts < 4)
551 {
552 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, 1);
553 }
554 else
555 {
556 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, (evergreen->ps.num_consts * 4)/16 );
557 }
558
559 END_BATCH();
560
561 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
562 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_PS_0, 1);
563 R600_OUT_BATCH(context->fp_bo_offset >> 8);
564 R600_OUT_BATCH_RELOC(0,
565 pbo_const,
566 0,
567 RADEON_GEM_DOMAIN_GTT, 0, 0);
568 END_BATCH();
569 }
570
571 COMMIT_BATCH();
572 }
573
574 static void evergreenSendVSresource(GLcontext *ctx, struct radeon_state_atom *atom)
575 {
576 context_t *context = EVERGREEN_CONTEXT(ctx);
577 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
578 struct radeon_bo * pbo;
579
580 struct radeon_bo * pbo_const;
581
582 BATCH_LOCALS(&context->radeon);
583 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
584
585 pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(GL_CONTEXT(context));
586
587 if (!pbo)
588 return;
589
590 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
591
592 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
593 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
594 R600_OUT_BATCH(evergreen->vs.SQ_PGM_START_VS.u32All);
595 R600_OUT_BATCH_RELOC(evergreen->vs.SQ_PGM_START_VS.u32All,
596 pbo,
597 evergreen->vs.SQ_PGM_START_VS.u32All,
598 RADEON_GEM_DOMAIN_GTT, 0, 0);
599 END_BATCH();
600
601 BEGIN_BATCH_NO_AUTOSTATE(3);
602 EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + 32*1), 0x0100000F); //consts == 1
603 //EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
604 END_BATCH();
605
606 pbo_const = (struct radeon_bo *)(context->vp_Constbo);
607
608 if(NULL != pbo_const)
609 {
610 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
611
612 BEGIN_BATCH_NO_AUTOSTATE(3);
613
614 if(evergreen->vs.num_consts < 4)
615 {
616 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, 1);
617 }
618 else
619 {
620 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, (evergreen->vs.num_consts * 4)/16 );
621 }
622
623 END_BATCH();
624
625 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
626 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_VS_0, 1);
627 R600_OUT_BATCH(context->vp_bo_offset >> 8);
628 R600_OUT_BATCH_RELOC(0,
629 pbo_const,
630 0,
631 RADEON_GEM_DOMAIN_GTT, 0, 0);
632 END_BATCH();
633 }
634
635 COMMIT_BATCH();
636 }
637
638 static void evergreenSendSQ(GLcontext *ctx, struct radeon_state_atom *atom)
639 {
640 context_t *context = EVERGREEN_CONTEXT(ctx);
641 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
642 BATCH_LOCALS(&context->radeon);
643 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
644
645 evergreenSendPSresource(ctx); //16 entries now
646
647 BEGIN_BATCH_NO_AUTOSTATE(77);
648
649 //34
650 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_VTX_SEMANTIC_0, 32);
651 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_0.u32All); //// // = 0x28380, // SAME
652 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_1.u32All); //// // = 0x28384, // SAME
653 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_2.u32All); //// // = 0x28388, // SAME
654 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_3.u32All); //// // = 0x2838C, // SAME
655 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_4.u32All); //// // = 0x28390, // SAME
656 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_5.u32All); //// // = 0x28394, // SAME
657 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_6.u32All); //// // = 0x28398, // SAME
658 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_7.u32All); //// // = 0x2839C, // SAME
659 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_8.u32All); //// // = 0x283A0, // SAME
660 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_9.u32All); //// // = 0x283A4, // SAME
661 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_10.u32All); //// // = 0x283A8, // SAME
662 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_11.u32All); //// // = 0x283AC, // SAME
663 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_12.u32All); //// // = 0x283B0, // SAME
664 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_13.u32All); //// // = 0x283B4, // SAME
665 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_14.u32All); //// // = 0x283B8, // SAME
666 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_15.u32All); //// // = 0x283BC, // SAME
667 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_16.u32All); //// // = 0x283C0, // SAME
668 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_17.u32All); //// // = 0x283C4, // SAME
669 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_18.u32All); //// // = 0x283C8, // SAME
670 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_19.u32All); //// // = 0x283CC, // SAME
671 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_20.u32All); //// // = 0x283D0, // SAME
672 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_21.u32All); //// // = 0x283D4, // SAME
673 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_22.u32All); //// // = 0x283D8, // SAME
674 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_23.u32All); //// // = 0x283DC, // SAME
675 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_24.u32All); //// // = 0x283E0, // SAME
676 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_25.u32All); //// // = 0x283E4, // SAME
677 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_26.u32All); //// // = 0x283E8, // SAME
678 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_27.u32All); //// // = 0x283EC, // SAME
679 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_28.u32All); //// // = 0x283F0, // SAME
680 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_29.u32All); //// // = 0x283F4, // SAME
681 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_30.u32All); //// // = 0x283F8, // SAME
682 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_31.u32All); //// // = 0x283FC, // SAME
683
684
685 //3
686 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_DYN_GPR_RESOURCE_LIMIT_1, 1);
687 R600_OUT_BATCH(evergreen->SQ_DYN_GPR_RESOURCE_LIMIT_1.u32All);//// // = 0x28838, //
688
689 //5
690 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
691 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_PS.u32All); //// // = 0x28844, // DIFF 0x28850
692 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_PS.u32All); //// // = 0x28848, //
693 R600_OUT_BATCH(evergreen->SQ_PGM_EXPORTS_PS.u32All); //// // = 0x2884C, // SAME 0x28854
694
695 //4
696 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
697 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_VS.u32All);//// // = 0x28860, // DIFF 0x28868
698 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_VS.u32All); //// // = 0x28864, //
699
700 //5
701 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_GS, 2);
702 /*
703 R600_OUT_BATCH(evergreen->SQ_PGM_START_GS.u32All); //// // = 0x28874, // SAME 0x2886C
704 */
705 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_GS.u32All); //// // = 0x28878, // DIFF 0x2887C
706 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_GS.u32All); //// // = 0x2887C, //
707
708 //5
709 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_ES, 2);
710 /*
711 R600_OUT_BATCH(evergreen->SQ_PGM_START_ES.u32All); //// // = 0x2888C, // SAME 0x28880
712 */
713 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_ES.u32All); //// // = 0x28890, // DIFF
714 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_ES.u32All); //// // = 0x28894, //
715
716 //4
717 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_FS, 1);
718 /*
719 R600_OUT_BATCH(evergreen->SQ_PGM_START_FS.u32All); //// // = 0x288A4, // SAME 0x28894
720 */
721 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_FS.u32All); //// // = 0x288A8, // DIFF 0x288A4
722
723 //3
724 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_HS, 1);
725 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_HS.u32All);//// // = 0x288C0, //
726
727 //3
728 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_LS, 1);
729 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_LS.u32All); //// // = 0x288D8, //
730
731 //3
732 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_LDS_ALLOC_PS, 1);
733 R600_OUT_BATCH(evergreen->SQ_LDS_ALLOC_PS.u32All); //// // = 0x288EC, //
734
735 //8
736 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
737 R600_OUT_BATCH(evergreen->SQ_ESGS_RING_ITEMSIZE.u32All); //// // = 0x28900, // SAME 0x288A8
738 R600_OUT_BATCH(evergreen->SQ_GSVS_RING_ITEMSIZE.u32All); //// // = 0x28904, // SAME 0x288AC
739 R600_OUT_BATCH(evergreen->SQ_ESTMP_RING_ITEMSIZE.u32All); //// // = 0x28908, // SAME 0x288B0
740 R600_OUT_BATCH(evergreen->SQ_GSTMP_RING_ITEMSIZE.u32All); //// // = 0x2890C, // SAME 0x288B4
741 R600_OUT_BATCH(evergreen->SQ_VSTMP_RING_ITEMSIZE.u32All); //// // = 0x28910, // SAME 0x288B8
742 R600_OUT_BATCH(evergreen->SQ_PSTMP_RING_ITEMSIZE.u32All); //// // = 0x28914, // SAME 0x288BC
743
744 //3
745 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 1);
746 R600_OUT_BATCH(evergreen->SQ_GS_VERT_ITEMSIZE.u32All); //// // = 0x2891C, // SAME 0x288C8
747
748 END_BATCH();
749
750 COMMIT_BATCH();
751
752 }
753 static void evergreenSendSPI(GLcontext *ctx, struct radeon_state_atom *atom)
754 {
755 context_t *context = EVERGREEN_CONTEXT(ctx);
756 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
757 BATCH_LOCALS(&context->radeon);
758 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
759
760 BEGIN_BATCH_NO_AUTOSTATE(59);
761
762 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_VS_OUT_ID_0, 10);
763 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_0.u32All);
764 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_1.u32All);
765 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_2.u32All);
766 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_3.u32All);
767 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_4.u32All);
768 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_5.u32All);
769 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_6.u32All);
770 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_7.u32All);
771 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_8.u32All);
772 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_9.u32All);
773
774 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_INPUT_CNTL_0, 45);
775 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[0].u32All);
776 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[1].u32All);
777 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[2].u32All);
778 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[3].u32All);
779 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[4].u32All);
780 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[5].u32All);
781 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[6].u32All);
782 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[7].u32All);
783 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[8].u32All);
784 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[9].u32All);
785 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[10].u32All);
786 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[11].u32All);
787 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[12].u32All);
788 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[13].u32All);
789 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[14].u32All);
790 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[15].u32All);
791 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[16].u32All);
792 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[17].u32All);
793 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[18].u32All);
794 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[19].u32All);
795 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[20].u32All);
796 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[21].u32All);
797 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[22].u32All);
798 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[23].u32All);
799 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[24].u32All);
800 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[25].u32All);
801 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[26].u32All);
802 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[27].u32All);
803 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[28].u32All);
804 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[29].u32All);
805 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[30].u32All);
806 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[31].u32All);
807 R600_OUT_BATCH(evergreen->SPI_VS_OUT_CONFIG.u32All);
808 R600_OUT_BATCH(evergreen->SPI_THREAD_GROUPING.u32All);
809 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_0.u32All);
810 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_1.u32All);
811 R600_OUT_BATCH(evergreen->SPI_INTERP_CONTROL_0.u32All);
812 R600_OUT_BATCH(evergreen->SPI_INPUT_Z.u32All);
813 R600_OUT_BATCH(evergreen->SPI_FOG_CNTL.u32All);
814 R600_OUT_BATCH(evergreen->SPI_BARYC_CNTL.u32All);
815 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_2.u32All);
816 R600_OUT_BATCH(evergreen->SPI_COMPUTE_INPUT_CNTL.u32All);
817 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_X.u32All);
818 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Y.u32All);
819 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Z.u32All);
820
821 END_BATCH();
822
823 COMMIT_BATCH();
824 }
825 static void evergreenSendSX(GLcontext *ctx, struct radeon_state_atom *atom)
826 {
827 context_t *context = EVERGREEN_CONTEXT(ctx);
828 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
829 BATCH_LOCALS(&context->radeon);
830 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
831
832 BEGIN_BATCH_NO_AUTOSTATE(9);
833
834 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, evergreen->SX_MISC.u32All);
835 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_TEST_CONTROL, evergreen->SX_ALPHA_TEST_CONTROL.u32All);
836 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_REF, evergreen->SX_ALPHA_REF.u32All);
837
838 END_BATCH();
839
840 COMMIT_BATCH();
841 }
842
843 static void evergreenSetDepthTarget(context_t *context)
844 {
845 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
846 struct radeon_renderbuffer *rrb;
847 unsigned int nPitchInPixel;
848
849 rrb = radeon_get_depthbuffer(&context->radeon);
850 if (!rrb)
851 {
852 return;
853 }
854
855 EVERGREEN_STATECHANGE(context, db);
856
857 evergreen->DB_DEPTH_SIZE.u32All = 0;
858
859 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
860 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift,
861 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask);
862 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (context->radeon.radeonScreen->driScreen->fbHeight/8)-1,
863 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift,
864 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask);
865 evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1;
866
867 if(4 == rrb->cpp)
868 {
869 SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_8_24,
870 EG_DB_Z_INFO__FORMAT_shift,
871 EG_DB_Z_INFO__FORMAT_mask);
872 }
873 else
874 {
875 SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_16,
876 EG_DB_Z_INFO__FORMAT_shift,
877 EG_DB_Z_INFO__FORMAT_mask);
878 }
879 SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
880 EG_DB_Z_INFO__ARRAY_MODE_shift,
881 EG_DB_Z_INFO__ARRAY_MODE_mask);
882 }
883
884 static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom)
885 {
886 context_t *context = EVERGREEN_CONTEXT(ctx);
887 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
888 struct radeon_renderbuffer *rrb;
889 BATCH_LOCALS(&context->radeon);
890 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
891
892 evergreenSetDepthTarget(context);
893
894 //8
895 BEGIN_BATCH_NO_AUTOSTATE(7);
896 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
897 R600_OUT_BATCH(evergreen->DB_RENDER_CONTROL.u32All);
898 R600_OUT_BATCH(evergreen->DB_COUNT_CONTROL.u32All);
899 R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All);
900 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All);
901 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All);
902 /*
903 R600_OUT_BATCH(evergreen->DB_HTILE_DATA_BASE.u32All);
904 */
905 END_BATCH();
906
907 //4
908 BEGIN_BATCH_NO_AUTOSTATE(4);
909 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
910 R600_OUT_BATCH(evergreen->DB_STENCIL_CLEAR.u32All);
911 R600_OUT_BATCH(evergreen->DB_DEPTH_CLEAR.u32All);
912 END_BATCH();
913
914 //4
915 BEGIN_BATCH_NO_AUTOSTATE(4);
916 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_DEPTH_SIZE, 2);
917 R600_OUT_BATCH(evergreen->DB_DEPTH_SIZE.u32All);
918 R600_OUT_BATCH(evergreen->DB_DEPTH_SLICE.u32All);
919 END_BATCH();
920
921 //3
922 BEGIN_BATCH_NO_AUTOSTATE(3);
923 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, evergreen->DB_DEPTH_CONTROL.u32All);
924 END_BATCH();
925
926 //3
927 BEGIN_BATCH_NO_AUTOSTATE(3);
928 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_SHADER_CONTROL, evergreen->DB_SHADER_CONTROL.u32All);
929 END_BATCH();
930
931 //5
932 BEGIN_BATCH_NO_AUTOSTATE(5);
933 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_SRESULTS_COMPARE_STATE0, 3);
934 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE0.u32All);
935 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE1.u32All);
936 R600_OUT_BATCH(evergreen->DB_PRELOAD_CONTROL.u32All);
937 END_BATCH();
938
939 //3
940 BEGIN_BATCH_NO_AUTOSTATE(3);
941 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, evergreen->DB_ALPHA_TO_MASK.u32All);
942 END_BATCH();
943
944 rrb = radeon_get_depthbuffer(&context->radeon);
945 if( (rrb != NULL) && (rrb->bo != NULL) )
946 {
947 //5
948 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
949 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All);
950 R600_OUT_BATCH_RELOC(evergreen->DB_Z_INFO.u32All,
951 rrb->bo,
952 evergreen->DB_Z_INFO.u32All,
953 0, RADEON_GEM_DOMAIN_VRAM, 0);
954 END_BATCH();
955
956 //5
957 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_ENABLE_bit) > 0)
958 {
959 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
960 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_READ_BASE, evergreen->DB_Z_READ_BASE.u32All);
961 R600_OUT_BATCH_RELOC(evergreen->DB_Z_READ_BASE.u32All,
962 rrb->bo,
963 evergreen->DB_Z_READ_BASE.u32All,
964 0, RADEON_GEM_DOMAIN_VRAM, 0);
965 END_BATCH();
966 }
967 //5
968 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_WRITE_ENABLE_bit) > 0)
969 {
970 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
971 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_WRITE_BASE, evergreen->DB_Z_READ_BASE.u32All);
972 R600_OUT_BATCH_RELOC(evergreen->DB_Z_WRITE_BASE.u32All,
973 rrb->bo,
974 evergreen->DB_Z_WRITE_BASE.u32All,
975 0, RADEON_GEM_DOMAIN_VRAM, 0);
976 END_BATCH();
977 }
978 }
979 /*
980 if (ctx->DrawBuffer)
981 {
982 rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
983
984 if((rrb != NULL) && (rrb->bo != NULL))
985 {
986 //5
987 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
988 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_Z_INFO.u32All);
989 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All,
990 rrb->bo,
991 evergreen->DB_STENCIL_INFO.u32All,
992 0, RADEON_GEM_DOMAIN_VRAM, 0);
993 END_BATCH();
994
995 //10
996 if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
997 {
998 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
999 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
1000 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
1001 rrb->bo,
1002 evergreen->DB_STENCIL_READ_BASE.u32All,
1003 0, RADEON_GEM_DOMAIN_VRAM, 0);
1004 END_BATCH();
1005
1006 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1007 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
1008 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
1009 rrb->bo,
1010 evergreen->DB_STENCIL_WRITE_BASE.u32All,
1011 0, RADEON_GEM_DOMAIN_VRAM, 0);
1012 END_BATCH();
1013 }
1014 }
1015 }
1016 */
1017 COMMIT_BATCH();
1018 }
1019
1020 static void evergreenSetRenderTarget(context_t *context, int id)
1021 {
1022 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1023
1024 struct radeon_renderbuffer *rrb;
1025 unsigned int nPitchInPixel;
1026
1027 rrb = radeon_get_colorbuffer(&context->radeon);
1028 if (!rrb || !rrb->bo) {
1029 return;
1030 }
1031
1032 EVERGREEN_STATECHANGE(context, cb);
1033
1034 /* addr */
1035 evergreen->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
1036
1037 /* pitch */
1038 nPitchInPixel = rrb->pitch/rrb->cpp;
1039
1040 SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1,
1041 EG_CB_COLOR0_PITCH__TILE_MAX_shift,
1042 EG_CB_COLOR0_PITCH__TILE_MAX_mask);
1043
1044 /* skice */
1045 SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All,
1046 //( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1047 ( (nPitchInPixel * 240)/64 )-1,
1048 EG_CB_COLOR0_SLICE__TILE_MAX_shift,
1049 EG_CB_COLOR0_SLICE__TILE_MAX_mask);
1050
1051 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
1052 SETbit(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All,
1053 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
1054
1055 /* CB_COLOR0_INFO */
1056 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1057 ENDIAN_NONE,
1058 EG_CB_COLOR0_INFO__ENDIAN_shift,
1059 EG_CB_COLOR0_INFO__ENDIAN_mask);
1060 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1061 ARRAY_LINEAR_GENERAL,
1062 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1063 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1064 if(4 == rrb->cpp)
1065 {
1066 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1067 COLOR_8_8_8_8,
1068 EG_CB_COLOR0_INFO__FORMAT_shift,
1069 EG_CB_COLOR0_INFO__FORMAT_mask);
1070 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1071 SWAP_ALT, //SWAP_STD
1072 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1073 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1074 }
1075 else
1076 {
1077 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1078 COLOR_5_6_5,
1079 EG_CB_COLOR0_INFO__FORMAT_shift,
1080 EG_CB_COLOR0_INFO__FORMAT_mask);
1081 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1082 SWAP_ALT_REV,
1083 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1084 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1085 }
1086 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1087 1,
1088 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
1089 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
1090 SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1091 EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
1092 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1093 NUMBER_UNORM,
1094 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
1095 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
1096
1097 evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
1098 evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
1099 evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
1100 evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
1101
1102 evergreen->render_target[id].enabled = GL_TRUE;
1103 }
1104
1105 static void evergreenSendCB(GLcontext *ctx, struct radeon_state_atom *atom)
1106 {
1107 context_t *context = EVERGREEN_CONTEXT(ctx);
1108 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1109 struct radeon_renderbuffer *rrb;
1110 BATCH_LOCALS(&context->radeon);
1111 int id = 0;
1112 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1113
1114 rrb = radeon_get_colorbuffer(&context->radeon);
1115 if (!rrb || !rrb->bo) {
1116 return;
1117 }
1118
1119 evergreenSetRenderTarget(context, 0);
1120
1121 if (!evergreen->render_target[id].enabled)
1122 return;
1123
1124 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1125 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
1126 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_BASE.u32All);
1127 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1128 rrb->bo,
1129 evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1130 0, RADEON_GEM_DOMAIN_VRAM, 0);
1131 END_BATCH();
1132
1133 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1134 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, evergreen->render_target[id].CB_COLOR0_INFO.u32All);
1135 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1136 rrb->bo,
1137 evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1138 0, RADEON_GEM_DOMAIN_VRAM, 0);
1139 END_BATCH();
1140
1141 BEGIN_BATCH_NO_AUTOSTATE(5);
1142 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
1143 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_PITCH.u32All);
1144 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_SLICE.u32All);
1145 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_VIEW.u32All);
1146 END_BATCH();
1147
1148 BEGIN_BATCH_NO_AUTOSTATE(4);
1149 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2);
1150 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All);
1151 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_DIM.u32All);
1152 /*
1153 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
1154 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
1155 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
1156 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
1157 */
1158 END_BATCH();
1159
1160 BEGIN_BATCH_NO_AUTOSTATE(4);
1161 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_TARGET_MASK, 2);
1162 R600_OUT_BATCH(evergreen->CB_TARGET_MASK.u32All);
1163 R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All);
1164 END_BATCH();
1165
1166 BEGIN_BATCH_NO_AUTOSTATE(5);
1167 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 3);
1168 R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All);
1169 R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All);
1170 R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All);
1171 END_BATCH();
1172
1173 BEGIN_BATCH_NO_AUTOSTATE(9);
1174 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND_ALPHA, evergreen->CB_BLEND_ALPHA.u32All);
1175 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All);
1176 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All);
1177 END_BATCH();
1178
1179 COMMIT_BATCH();
1180 }
1181 static void evergreenSendCP(GLcontext *ctx, struct radeon_state_atom *atom)
1182 {
1183 context_t *context = EVERGREEN_CONTEXT(ctx);
1184 BATCH_LOCALS(&context->radeon);
1185 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1186
1187 //first to send
1188 //r700Start3D
1189 BEGIN_BATCH_NO_AUTOSTATE(3);
1190 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); //IT_CONTEXT_CONTROL 0x28
1191 R600_OUT_BATCH(0x80000000);
1192 R600_OUT_BATCH(0x80000000);
1193 END_BATCH();
1194
1195 COMMIT_BATCH();
1196 }
1197 static void evergreenSendVGT(GLcontext *ctx, struct radeon_state_atom *atom)
1198 {
1199 context_t *context = EVERGREEN_CONTEXT(ctx);
1200 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1201 BATCH_LOCALS(&context->radeon);
1202 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1203
1204 /* moved to draw:
1205 VGT_DRAW_INITIATOR
1206 VGT_INDEX_TYPE
1207 VGT_PRIMITIVE_TYPE
1208 */
1209 BEGIN_BATCH_NO_AUTOSTATE(5);
1210 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 3);
1211 R600_OUT_BATCH(evergreen->VGT_MAX_VTX_INDX.u32All);
1212 R600_OUT_BATCH(evergreen->VGT_MIN_VTX_INDX.u32All);
1213 R600_OUT_BATCH(evergreen->VGT_INDX_OFFSET.u32All);
1214 END_BATCH();
1215
1216 BEGIN_BATCH_NO_AUTOSTATE(6);
1217 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_OUTPUT_PATH_CNTL, evergreen->VGT_OUTPUT_PATH_CNTL.u32All);
1218
1219 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_GS_MODE, evergreen->VGT_GS_MODE.u32All);
1220 END_BATCH();
1221
1222 BEGIN_BATCH_NO_AUTOSTATE(3);
1223 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVEID_EN, 1);
1224 R600_OUT_BATCH(evergreen->VGT_PRIMITIVEID_EN.u32All);
1225 END_BATCH();
1226
1227 BEGIN_BATCH_NO_AUTOSTATE(4);
1228 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1229 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_0.u32All);
1230 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_1.u32All);
1231 END_BATCH();
1232
1233 BEGIN_BATCH_NO_AUTOSTATE(4);
1234 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1235 R600_OUT_BATCH(evergreen->VGT_REUSE_OFF.u32All);
1236 R600_OUT_BATCH(evergreen->VGT_VTX_CNT_EN.u32All);
1237 END_BATCH();
1238
1239 BEGIN_BATCH_NO_AUTOSTATE(3);
1240 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, evergreen->VGT_SHADER_STAGES_EN.u32All);
1241 END_BATCH();
1242
1243 BEGIN_BATCH_NO_AUTOSTATE(4);
1244 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1245 R600_OUT_BATCH(evergreen->VGT_STRMOUT_CONFIG.u32All);
1246 R600_OUT_BATCH(evergreen->VGT_STRMOUT_BUFFER_CONFIG.u32All);
1247 END_BATCH();
1248
1249 COMMIT_BATCH();
1250 }
1251
1252 static void evergreenSendTIMESTAMP(GLcontext *ctx, struct radeon_state_atom *atom)
1253 {
1254 context_t *context = EVERGREEN_CONTEXT(ctx);
1255 BATCH_LOCALS(&context->radeon);
1256 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1257 }
1258
1259 void evergreenInitAtoms(context_t *context)
1260 {
1261 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1262 context->radeon.hw.max_state_size = 10 + 5 + 14 + 3; /* start 3d, idle, cb/db flush, 3 for time stamp */
1263
1264 /* Setup the atom linked list */
1265 make_empty_list(&context->radeon.hw.atomlist);
1266 context->radeon.hw.atomlist.name = "atom-list";
1267
1268 EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
1269
1270 //make sure send first
1271 EVERGREEN_ALLOC_STATE(cp, always, 3, evergreenSendCP);
1272
1273 EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (6 + (VERT_ATTRIB_MAX * 12)), evergreenSendVTX);
1274 EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA);
1275 EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP);
1276 EVERGREEN_ALLOC_STATE(sq, always, 86, evergreenSendSQ); /* 85 */
1277 EVERGREEN_ALLOC_STATE(vs, always, 16, evergreenSendVSresource);
1278 EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI);
1279 EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX);
1280 EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */
1281 EVERGREEN_ALLOC_STATE(db, always, 60, evergreenSendDB);
1282 EVERGREEN_ALLOC_STATE(cb, always, 35, evergreenSendCB);
1283 EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
1284 EVERGREEN_ALLOC_STATE(timestamp, always, 3, evergreenSendTIMESTAMP);
1285
1286 //evergreen_init_query_stateobj(&context->radeon, 6 * 2);
1287
1288 context->radeon.hw.is_dirty = GL_TRUE;
1289 context->radeon.hw.all_dirty = GL_TRUE;
1290 }