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r600c/eg: remove obselete comment
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_chip.c
1 /*
2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/imports.h"
28 #include "main/glheader.h"
29 #include "main/simple_list.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "evergreen_chip.h"
35 #include "evergreen_off.h"
36 #include "evergreen_diff.h"
37 #include "evergreen_fragprog.h"
38 #include "evergreen_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 void evergreenCreateChip(context_t *context)
43 {
44 EVERGREEN_CHIP_CONTEXT * evergreen =
45 (EVERGREEN_CHIP_CONTEXT*) CALLOC(sizeof(EVERGREEN_CHIP_CONTEXT));
46
47 context->pChip = (void*)evergreen;
48 }
49
50 #define EVERGREEN_ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
51 do { \
52 context->evergreen_atoms.ATOM.cmd_size = (SZ); \
53 context->evergreen_atoms.ATOM.cmd = NULL; \
54 context->evergreen_atoms.ATOM.name = #ATOM; \
55 context->evergreen_atoms.ATOM.idx = 0; \
56 context->evergreen_atoms.ATOM.check = check_##CHK; \
57 context->evergreen_atoms.ATOM.dirty = GL_FALSE; \
58 context->evergreen_atoms.ATOM.emit = (EMIT); \
59 context->radeon.hw.max_state_size += (SZ); \
60 insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
61 } while (0)
62
63 static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
64 {
65 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
66 struct radeon_query_object *query = radeon->query.current;
67 int count;
68
69 if (!query || query->emitted_begin)
70 count = 0;
71 else
72 count = atom->cmd_size;
73 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
74 return count;
75 }
76
77 static void evergreenSendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
78 {
79 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
80 struct radeon_query_object *query = radeon->query.current;
81 BATCH_LOCALS(radeon);
82 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
83
84 /* clear the buffer */
85 radeon_bo_map(query->bo, GL_FALSE);
86 memset(query->bo->ptr, 0, 8 * 2 * sizeof(uint64_t)); /* 8 DBs, 2 qwords each */
87 radeon_bo_unmap(query->bo);
88
89 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
90 query->bo,
91 0, RADEON_GEM_DOMAIN_GTT);
92
93 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
94 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
95 R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
96 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
97 R600_OUT_BATCH(0x00000000);
98 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
99 END_BATCH();
100 query->emitted_begin = GL_TRUE;
101 }
102
103 static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
104 {
105 radeon->query.queryobj.cmd_size = (SZ);
106 radeon->query.queryobj.cmd = NULL;
107 radeon->query.queryobj.name = "queryobj";
108 radeon->query.queryobj.idx = 0;
109 radeon->query.queryobj.check = check_queryobj;
110 radeon->query.queryobj.dirty = GL_FALSE;
111 radeon->query.queryobj.emit = evergreenSendQueryBegin;
112 radeon->hw.max_state_size += (SZ);
113 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
114 }
115
116
117 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
118 {
119 return atom->cmd_size;
120 }
121
122 static void evergreenSendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
123 {
124 context_t *context = EVERGREEN_CONTEXT(ctx);
125 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
126
127 struct evergreen_vertex_program *vp = context->selected_vp;
128
129 struct radeon_bo *bo = NULL;
130 unsigned int i;
131 unsigned int nBorderSet = 0;
132 BATCH_LOCALS(&context->radeon);
133
134 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
135
136 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
137 if (ctx->Texture.Unit[i]._ReallyEnabled) {
138 radeonTexObj *t = evergreen->textures[i];
139
140 if (t) {
141 /* Tex resource */
142 if (!t->image_override) {
143 bo = t->mt->bo;
144 } else {
145 bo = t->bo;
146 }
147 if (bo)
148 {
149
150 r700SyncSurf(context, bo,
151 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
152 0, TC_ACTION_ENA_bit);
153
154 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
155 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
156
157 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
158 { /* vs texture */
159 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
160 }
161 else
162 {
163 R600_OUT_BATCH(i * EG_FETCH_RESOURCE_STRIDE);
164 }
165
166 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE0);
167 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE1);
168 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE2);
169 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE3);
170 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE4);
171 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE5);
172 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE6);
173 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE7);
174
175 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE2,
176 bo,
177 evergreen->textures[i]->SQ_TEX_RESOURCE2,
178 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
179 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE3,
180 bo,
181 evergreen->textures[i]->SQ_TEX_RESOURCE3,
182 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
183 END_BATCH();
184 COMMIT_BATCH();
185 }
186 /* Tex sampler */
187 BEGIN_BATCH_NO_AUTOSTATE(5);
188 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
189
190 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
191 { /* vs texture */
192 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * 3);
193 }
194 else
195 {
196 R600_OUT_BATCH(i * 3);
197 }
198 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER0);
199 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER1);
200 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER2);
201
202 END_BATCH();
203 COMMIT_BATCH();
204
205 /* Tex border color */
206 if(0 == nBorderSet)
207 {
208 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
209 R600_OUT_BATCH_REGSEQ(EG_TD_PS_BORDER_COLOR_RED, 4);
210 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
211 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
212 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
213 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
214 END_BATCH();
215 COMMIT_BATCH();
216
217 nBorderSet = 1;
218 }
219 }
220 }
221 }
222 }
223
224 static int check_evergreen_tx(GLcontext *ctx, struct radeon_state_atom *atom)
225 {
226 context_t *context = EVERGREEN_CONTEXT(ctx);
227 unsigned int i, count = 0;
228 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
229
230 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
231 if (ctx->Texture.Unit[i]._ReallyEnabled) {
232 radeonTexObj *t = evergreen->textures[i];
233 if (t)
234 count++;
235 }
236 }
237 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
238 return count * 37 + 6;
239 }
240
241 static void evergreenSendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
242 {
243 context_t *context = EVERGREEN_CONTEXT(ctx);
244 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
245 BATCH_LOCALS(&context->radeon);
246 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
247
248 BEGIN_BATCH_NO_AUTOSTATE(19);
249 //6
250 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL, evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All);
251 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL_1, evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All);
252 //6
253 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
254 R600_OUT_BATCH(evergreen->evergreen_config.SQ_CONFIG.u32All);
255 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
256 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
257 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All);
258 //7
259 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
260 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All);
261 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All);
262 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
263 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
264 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All);
265
266 END_BATCH();
267
268 COMMIT_BATCH();
269 }
270
271 extern int evergreen_getTypeSize(GLenum type);
272 static void evergreenSetupVTXConstants(GLcontext * ctx,
273 void * pAos,
274 StreamDesc * pStreamDesc)
275 {
276 context_t *context = EVERGREEN_CONTEXT(ctx);
277 struct radeon_aos * paos = (struct radeon_aos *)pAos;
278 unsigned int nVBsize;
279 BATCH_LOCALS(&context->radeon);
280
281 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
282 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
283 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
284 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
285 unsigned int uSQ_VTX_CONSTANT_WORD7_0 = 0;
286
287 if (!paos->bo)
288 return;
289
290 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
291
292 if(0 == pStreamDesc->stride)
293 {
294 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
295 }
296 else
297 {
298 nVBsize = (paos->count - 1) * pStreamDesc->stride
299 + pStreamDesc->size * getTypeSize(pStreamDesc->type);
300 }
301
302 //uSQ_VTX_CONSTANT_WORD0_0
303 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
304
305 //uSQ_VTX_CONSTANT_WORD1_0
306 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize;
307
308 //uSQ_VTX_CONSTANT_WORD2_0
309 SETfield(uSQ_VTX_CONSTANT_WORD2_0,
310 pStreamDesc->stride,
311 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
312 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
313 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
314 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
315 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
316 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
317 if(GL_TRUE == pStreamDesc->normalize)
318 {
319 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
320 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
321 }
322 else
323 {
324 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
325 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
326 }
327 if(1 == pStreamDesc->_signed)
328 {
329 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
330 }
331
332 //uSQ_VTX_CONSTANT_WORD3_0
333 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_X,
334 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
335 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
336 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Y,
337 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
338 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
339 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Z,
340 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
341 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
342 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_W,
343 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
344 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
345
346 //uSQ_VTX_CONSTANT_WORD7_0
347 SETfield(uSQ_VTX_CONSTANT_WORD7_0, SQ_TEX_VTX_VALID_BUFFER,
348 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
349
350 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
351
352 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
353 R600_OUT_BATCH((pStreamDesc->element + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
354 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
355 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
356 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
357 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
358 R600_OUT_BATCH(0);
359 R600_OUT_BATCH(0);
360 R600_OUT_BATCH(0);
361 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD7_0);
362 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
363 paos->bo,
364 uSQ_VTX_CONSTANT_WORD0_0,
365 RADEON_GEM_DOMAIN_GTT, 0, 0);
366 END_BATCH();
367
368 COMMIT_BATCH();
369 }
370
371 static int check_evergreen_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
372 {
373 context_t *context = EVERGREEN_CONTEXT(ctx);
374 int count = context->radeon.tcl.aos_count * 12;
375
376 if (count)
377 count += 6;
378
379 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
380 return count;
381 }
382
383 static void evergreenSendVTX(GLcontext *ctx, struct radeon_state_atom *atom)
384 {
385 context_t *context = EVERGREEN_CONTEXT(ctx);
386 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
387 unsigned int i, j = 0;
388 BATCH_LOCALS(&context->radeon);
389 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
390
391 if (context->radeon.tcl.aos_count == 0)
392 return;
393
394 BEGIN_BATCH_NO_AUTOSTATE(6);
395 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
396 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
397 R600_OUT_BATCH(0);
398
399 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
400 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
401 R600_OUT_BATCH(0);
402 END_BATCH();
403 COMMIT_BATCH();
404
405 for(i=0; i<VERT_ATTRIB_MAX; i++) {
406 if(vp->mesa_program->Base.InputsRead & (1 << i))
407 {
408 evergreenSetupVTXConstants(ctx,
409 (void*)(&context->radeon.tcl.aos[j]),
410 &(context->stream_desc[j]));
411 j++;
412 }
413 }
414 }
415 static void evergreenSendPA(GLcontext *ctx, struct radeon_state_atom *atom)
416 {
417 context_t *context = EVERGREEN_CONTEXT(ctx);
418 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
419 BATCH_LOCALS(&context->radeon);
420 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
421 int id = 0;
422
423 BEGIN_BATCH_NO_AUTOSTATE(3);
424 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
425 END_BATCH();
426
427 BEGIN_BATCH_NO_AUTOSTATE(22);
428 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
429 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All);
430 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All);
431
432 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 12);
433 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_OFFSET.u32All);
434 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All);
435 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All);
436 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_RULE.u32All);
437 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_TL.u32All);
438 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_BR.u32All);
439 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_TL.u32All);
440 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_BR.u32All);
441 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_TL.u32All);
442 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_BR.u32All);
443 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_TL.u32All);
444 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_BR.u32All);
445
446 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
447 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All);
448 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All);
449 END_BATCH();
450
451 BEGIN_BATCH_NO_AUTOSTATE(3);
452 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SC_EDGERULE, evergreen->PA_SC_EDGERULE.u32All);
453 END_BATCH();
454
455
456 BEGIN_BATCH_NO_AUTOSTATE(18);
457 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 4);
458 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
459 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
460 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
461 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
462
463 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
464 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
465 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
466
467 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_VPORT_XSCALE, 6);
468 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XSCALE.u32All);
469 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
470 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YSCALE.u32All);
471 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
472 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
473 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
474 END_BATCH();
475
476
477 for (id = 0; id < EVERGREEN_MAX_UCP; id++) {
478 if (evergreen->ucp[id].enabled) {
479 BEGIN_BATCH_NO_AUTOSTATE(6);
480 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_UCP_0_X + (4 * id), 4);
481 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_X.u32All);
482 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Y.u32All);
483 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Z.u32All);
484 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_W.u32All);
485 END_BATCH();
486 }
487 }
488
489 BEGIN_BATCH_NO_AUTOSTATE(42);
490 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_CLIP_CNTL, 5);
491 R600_OUT_BATCH(evergreen->PA_CL_CLIP_CNTL.u32All);
492 R600_OUT_BATCH(evergreen->PA_SU_SC_MODE_CNTL.u32All);
493 R600_OUT_BATCH(evergreen->PA_CL_VTE_CNTL.u32All);
494 R600_OUT_BATCH(evergreen->PA_CL_VS_OUT_CNTL.u32All);
495 R600_OUT_BATCH(evergreen->PA_CL_NANINF_CNTL.u32All);
496
497 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 3);
498 R600_OUT_BATCH(evergreen->PA_SU_POINT_SIZE.u32All);
499 R600_OUT_BATCH(evergreen->PA_SU_POINT_MINMAX.u32All);
500 R600_OUT_BATCH(evergreen->PA_SU_LINE_CNTL.u32All);
501
502 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
503 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_0.u32All);
504 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_1.u32All);
505
506 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
507 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
508 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_CLAMP.u32All);
509 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
510 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
511 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
512 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
513
514 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
515 R600_OUT_BATCH(evergreen->PA_SC_LINE_CNTL.u32All);
516 R600_OUT_BATCH(evergreen->PA_SC_AA_CONFIG.u32All);
517 R600_OUT_BATCH(evergreen->PA_SU_VTX_CNTL.u32All);
518 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All);
519 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All);
520 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
521 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All);
522 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_0.u32All);
523 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_1.u32All);
524 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_2.u32All);
525 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_3.u32All);
526 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_4.u32All);
527 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_5.u32All);
528 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_6.u32All);
529 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_7.u32All);
530 R600_OUT_BATCH(evergreen->PA_SC_AA_MASK.u32All);
531
532 END_BATCH();
533
534 COMMIT_BATCH();
535 }
536 static void evergreenSendTP(GLcontext *ctx, struct radeon_state_atom *atom)
537 {
538 /*
539 context_t *context = EVERGREEN_CONTEXT(ctx);
540 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
541 BATCH_LOCALS(&context->radeon);
542 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
543
544 COMMIT_BATCH();
545 */
546 }
547
548 static void evergreenSendPSresource(GLcontext *ctx)
549 {
550 context_t *context = EVERGREEN_CONTEXT(ctx);
551 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
552 struct radeon_bo * pbo;
553
554 struct radeon_bo * pbo_const;
555
556 BATCH_LOCALS(&context->radeon);
557 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
558
559 pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(GL_CONTEXT(context));
560
561 if (!pbo)
562 return;
563
564 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
565
566 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
567 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
568 R600_OUT_BATCH(evergreen->ps.SQ_PGM_START_PS.u32All);
569 R600_OUT_BATCH_RELOC(evergreen->ps.SQ_PGM_START_PS.u32All,
570 pbo,
571 evergreen->ps.SQ_PGM_START_PS.u32All,
572 RADEON_GEM_DOMAIN_GTT, 0, 0);
573 END_BATCH();
574
575 BEGIN_BATCH_NO_AUTOSTATE(3);
576 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LOOP_CONST_0, 0x01000FFF);
577 END_BATCH();
578
579 pbo_const = (struct radeon_bo *)(context->fp_Constbo);
580
581 if(NULL != pbo_const)
582 {
583 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
584
585 BEGIN_BATCH_NO_AUTOSTATE(3);
586
587 if(evergreen->ps.num_consts < 4)
588 {
589 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, 1);
590 }
591 else
592 {
593 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, (evergreen->ps.num_consts * 4)/16 );
594 }
595
596 END_BATCH();
597
598 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
599 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_PS_0, 1);
600 R600_OUT_BATCH(context->fp_bo_offset >> 8);
601 R600_OUT_BATCH_RELOC(0,
602 pbo_const,
603 0,
604 RADEON_GEM_DOMAIN_GTT, 0, 0);
605 END_BATCH();
606 }
607
608 COMMIT_BATCH();
609 }
610
611 static void evergreenSendVSresource(GLcontext *ctx, struct radeon_state_atom *atom)
612 {
613 context_t *context = EVERGREEN_CONTEXT(ctx);
614 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
615 struct radeon_bo * pbo;
616
617 struct radeon_bo * pbo_const;
618
619 BATCH_LOCALS(&context->radeon);
620 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
621
622 pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(GL_CONTEXT(context));
623
624 if (!pbo)
625 return;
626
627 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
628
629 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
630 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
631 R600_OUT_BATCH(evergreen->vs.SQ_PGM_START_VS.u32All);
632 R600_OUT_BATCH_RELOC(evergreen->vs.SQ_PGM_START_VS.u32All,
633 pbo,
634 evergreen->vs.SQ_PGM_START_VS.u32All,
635 RADEON_GEM_DOMAIN_GTT, 0, 0);
636 END_BATCH();
637
638 BEGIN_BATCH_NO_AUTOSTATE(3);
639 EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + 32*1), 0x0100000F); //consts == 1
640 //EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
641 END_BATCH();
642
643 pbo_const = (struct radeon_bo *)(context->vp_Constbo);
644
645 if(NULL != pbo_const)
646 {
647 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
648
649 BEGIN_BATCH_NO_AUTOSTATE(3);
650
651 if(evergreen->vs.num_consts < 4)
652 {
653 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, 1);
654 }
655 else
656 {
657 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, (evergreen->vs.num_consts * 4)/16 );
658 }
659
660 END_BATCH();
661
662 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
663 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_VS_0, 1);
664 R600_OUT_BATCH(context->vp_bo_offset >> 8);
665 R600_OUT_BATCH_RELOC(0,
666 pbo_const,
667 0,
668 RADEON_GEM_DOMAIN_GTT, 0, 0);
669 END_BATCH();
670 }
671
672 COMMIT_BATCH();
673 }
674
675 static void evergreenSendSQ(GLcontext *ctx, struct radeon_state_atom *atom)
676 {
677 context_t *context = EVERGREEN_CONTEXT(ctx);
678 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
679 BATCH_LOCALS(&context->radeon);
680 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
681
682 evergreenSendPSresource(ctx); //16 entries now
683
684 BEGIN_BATCH_NO_AUTOSTATE(77);
685
686 //34
687 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_VTX_SEMANTIC_0, 32);
688 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_0.u32All); //// // = 0x28380, // SAME
689 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_1.u32All); //// // = 0x28384, // SAME
690 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_2.u32All); //// // = 0x28388, // SAME
691 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_3.u32All); //// // = 0x2838C, // SAME
692 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_4.u32All); //// // = 0x28390, // SAME
693 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_5.u32All); //// // = 0x28394, // SAME
694 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_6.u32All); //// // = 0x28398, // SAME
695 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_7.u32All); //// // = 0x2839C, // SAME
696 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_8.u32All); //// // = 0x283A0, // SAME
697 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_9.u32All); //// // = 0x283A4, // SAME
698 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_10.u32All); //// // = 0x283A8, // SAME
699 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_11.u32All); //// // = 0x283AC, // SAME
700 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_12.u32All); //// // = 0x283B0, // SAME
701 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_13.u32All); //// // = 0x283B4, // SAME
702 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_14.u32All); //// // = 0x283B8, // SAME
703 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_15.u32All); //// // = 0x283BC, // SAME
704 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_16.u32All); //// // = 0x283C0, // SAME
705 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_17.u32All); //// // = 0x283C4, // SAME
706 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_18.u32All); //// // = 0x283C8, // SAME
707 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_19.u32All); //// // = 0x283CC, // SAME
708 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_20.u32All); //// // = 0x283D0, // SAME
709 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_21.u32All); //// // = 0x283D4, // SAME
710 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_22.u32All); //// // = 0x283D8, // SAME
711 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_23.u32All); //// // = 0x283DC, // SAME
712 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_24.u32All); //// // = 0x283E0, // SAME
713 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_25.u32All); //// // = 0x283E4, // SAME
714 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_26.u32All); //// // = 0x283E8, // SAME
715 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_27.u32All); //// // = 0x283EC, // SAME
716 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_28.u32All); //// // = 0x283F0, // SAME
717 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_29.u32All); //// // = 0x283F4, // SAME
718 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_30.u32All); //// // = 0x283F8, // SAME
719 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_31.u32All); //// // = 0x283FC, // SAME
720
721
722 //3
723 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_DYN_GPR_RESOURCE_LIMIT_1, 1);
724 R600_OUT_BATCH(evergreen->SQ_DYN_GPR_RESOURCE_LIMIT_1.u32All);//// // = 0x28838, //
725
726 //5
727 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
728 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_PS.u32All); //// // = 0x28844, // DIFF 0x28850
729 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_PS.u32All); //// // = 0x28848, //
730 R600_OUT_BATCH(evergreen->SQ_PGM_EXPORTS_PS.u32All); //// // = 0x2884C, // SAME 0x28854
731
732 //4
733 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
734 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_VS.u32All);//// // = 0x28860, // DIFF 0x28868
735 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_VS.u32All); //// // = 0x28864, //
736
737 //5
738 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_GS, 2);
739 /*
740 R600_OUT_BATCH(evergreen->SQ_PGM_START_GS.u32All); //// // = 0x28874, // SAME 0x2886C
741 */
742 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_GS.u32All); //// // = 0x28878, // DIFF 0x2887C
743 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_GS.u32All); //// // = 0x2887C, //
744
745 //5
746 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_ES, 2);
747 /*
748 R600_OUT_BATCH(evergreen->SQ_PGM_START_ES.u32All); //// // = 0x2888C, // SAME 0x28880
749 */
750 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_ES.u32All); //// // = 0x28890, // DIFF
751 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_ES.u32All); //// // = 0x28894, //
752
753 //4
754 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_FS, 1);
755 /*
756 R600_OUT_BATCH(evergreen->SQ_PGM_START_FS.u32All); //// // = 0x288A4, // SAME 0x28894
757 */
758 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_FS.u32All); //// // = 0x288A8, // DIFF 0x288A4
759
760 //3
761 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_HS, 1);
762 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_HS.u32All);//// // = 0x288C0, //
763
764 //3
765 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_LS, 1);
766 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_LS.u32All); //// // = 0x288D8, //
767
768 //3
769 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_LDS_ALLOC_PS, 1);
770 R600_OUT_BATCH(evergreen->SQ_LDS_ALLOC_PS.u32All); //// // = 0x288EC, //
771
772 //8
773 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
774 R600_OUT_BATCH(evergreen->SQ_ESGS_RING_ITEMSIZE.u32All); //// // = 0x28900, // SAME 0x288A8
775 R600_OUT_BATCH(evergreen->SQ_GSVS_RING_ITEMSIZE.u32All); //// // = 0x28904, // SAME 0x288AC
776 R600_OUT_BATCH(evergreen->SQ_ESTMP_RING_ITEMSIZE.u32All); //// // = 0x28908, // SAME 0x288B0
777 R600_OUT_BATCH(evergreen->SQ_GSTMP_RING_ITEMSIZE.u32All); //// // = 0x2890C, // SAME 0x288B4
778 R600_OUT_BATCH(evergreen->SQ_VSTMP_RING_ITEMSIZE.u32All); //// // = 0x28910, // SAME 0x288B8
779 R600_OUT_BATCH(evergreen->SQ_PSTMP_RING_ITEMSIZE.u32All); //// // = 0x28914, // SAME 0x288BC
780
781 //3
782 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 1);
783 R600_OUT_BATCH(evergreen->SQ_GS_VERT_ITEMSIZE.u32All); //// // = 0x2891C, // SAME 0x288C8
784
785 END_BATCH();
786
787 COMMIT_BATCH();
788
789 }
790 static void evergreenSendSPI(GLcontext *ctx, struct radeon_state_atom *atom)
791 {
792 context_t *context = EVERGREEN_CONTEXT(ctx);
793 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
794 BATCH_LOCALS(&context->radeon);
795 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
796
797 BEGIN_BATCH_NO_AUTOSTATE(59);
798
799 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_VS_OUT_ID_0, 10);
800 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_0.u32All);
801 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_1.u32All);
802 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_2.u32All);
803 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_3.u32All);
804 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_4.u32All);
805 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_5.u32All);
806 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_6.u32All);
807 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_7.u32All);
808 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_8.u32All);
809 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_9.u32All);
810
811 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_INPUT_CNTL_0, 45);
812 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[0].u32All);
813 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[1].u32All);
814 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[2].u32All);
815 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[3].u32All);
816 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[4].u32All);
817 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[5].u32All);
818 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[6].u32All);
819 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[7].u32All);
820 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[8].u32All);
821 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[9].u32All);
822 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[10].u32All);
823 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[11].u32All);
824 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[12].u32All);
825 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[13].u32All);
826 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[14].u32All);
827 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[15].u32All);
828 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[16].u32All);
829 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[17].u32All);
830 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[18].u32All);
831 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[19].u32All);
832 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[20].u32All);
833 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[21].u32All);
834 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[22].u32All);
835 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[23].u32All);
836 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[24].u32All);
837 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[25].u32All);
838 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[26].u32All);
839 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[27].u32All);
840 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[28].u32All);
841 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[29].u32All);
842 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[30].u32All);
843 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[31].u32All);
844 R600_OUT_BATCH(evergreen->SPI_VS_OUT_CONFIG.u32All);
845 R600_OUT_BATCH(evergreen->SPI_THREAD_GROUPING.u32All);
846 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_0.u32All);
847 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_1.u32All);
848 R600_OUT_BATCH(evergreen->SPI_INTERP_CONTROL_0.u32All);
849 R600_OUT_BATCH(evergreen->SPI_INPUT_Z.u32All);
850 R600_OUT_BATCH(evergreen->SPI_FOG_CNTL.u32All);
851 R600_OUT_BATCH(evergreen->SPI_BARYC_CNTL.u32All);
852 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_2.u32All);
853 R600_OUT_BATCH(evergreen->SPI_COMPUTE_INPUT_CNTL.u32All);
854 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_X.u32All);
855 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Y.u32All);
856 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Z.u32All);
857
858 END_BATCH();
859
860 COMMIT_BATCH();
861 }
862 static void evergreenSendSX(GLcontext *ctx, struct radeon_state_atom *atom)
863 {
864 context_t *context = EVERGREEN_CONTEXT(ctx);
865 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
866 BATCH_LOCALS(&context->radeon);
867 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
868
869 BEGIN_BATCH_NO_AUTOSTATE(9);
870
871 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, evergreen->SX_MISC.u32All);
872 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_TEST_CONTROL, evergreen->SX_ALPHA_TEST_CONTROL.u32All);
873 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_REF, evergreen->SX_ALPHA_REF.u32All);
874
875 END_BATCH();
876
877 COMMIT_BATCH();
878 }
879
880 static void evergreenSetDepthTarget(context_t *context)
881 {
882 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
883 struct radeon_renderbuffer *rrb;
884 unsigned int nPitchInPixel;
885
886 rrb = radeon_get_depthbuffer(&context->radeon);
887 if (!rrb)
888 {
889 return;
890 }
891
892 EVERGREEN_STATECHANGE(context, db);
893
894 evergreen->DB_DEPTH_SIZE.u32All = 0;
895
896 nPitchInPixel = rrb->pitch/rrb->cpp;
897
898 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
899 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift,
900 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask);
901 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (context->radeon.radeonScreen->driScreen->fbHeight/8)-1,
902 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift,
903 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask);
904 evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1;
905
906 if(4 == rrb->cpp)
907 {
908 SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_8_24,
909 EG_DB_Z_INFO__FORMAT_shift,
910 EG_DB_Z_INFO__FORMAT_mask);
911 }
912 else
913 {
914 SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_16,
915 EG_DB_Z_INFO__FORMAT_shift,
916 EG_DB_Z_INFO__FORMAT_mask);
917 }
918 SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
919 EG_DB_Z_INFO__ARRAY_MODE_shift,
920 EG_DB_Z_INFO__ARRAY_MODE_mask);
921 }
922
923 static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom)
924 {
925 context_t *context = EVERGREEN_CONTEXT(ctx);
926 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
927 struct radeon_renderbuffer *rrb;
928 BATCH_LOCALS(&context->radeon);
929 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
930
931 evergreenSetDepthTarget(context);
932
933 //8
934 BEGIN_BATCH_NO_AUTOSTATE(7);
935 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
936 R600_OUT_BATCH(evergreen->DB_RENDER_CONTROL.u32All);
937 R600_OUT_BATCH(evergreen->DB_COUNT_CONTROL.u32All);
938 R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All);
939 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All);
940 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All);
941 END_BATCH();
942
943 //4
944 BEGIN_BATCH_NO_AUTOSTATE(4);
945 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
946 R600_OUT_BATCH(evergreen->DB_STENCIL_CLEAR.u32All);
947 R600_OUT_BATCH(evergreen->DB_DEPTH_CLEAR.u32All);
948 END_BATCH();
949
950 //4
951 BEGIN_BATCH_NO_AUTOSTATE(4);
952 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_DEPTH_SIZE, 2);
953 R600_OUT_BATCH(evergreen->DB_DEPTH_SIZE.u32All);
954 R600_OUT_BATCH(evergreen->DB_DEPTH_SLICE.u32All);
955 END_BATCH();
956
957 //3
958 BEGIN_BATCH_NO_AUTOSTATE(3);
959 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, evergreen->DB_DEPTH_CONTROL.u32All);
960 END_BATCH();
961
962 //3
963 BEGIN_BATCH_NO_AUTOSTATE(3);
964 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_SHADER_CONTROL, evergreen->DB_SHADER_CONTROL.u32All);
965 END_BATCH();
966
967 //5
968 BEGIN_BATCH_NO_AUTOSTATE(5);
969 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_SRESULTS_COMPARE_STATE0, 3);
970 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE0.u32All);
971 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE1.u32All);
972 R600_OUT_BATCH(evergreen->DB_PRELOAD_CONTROL.u32All);
973 END_BATCH();
974
975 //3
976 BEGIN_BATCH_NO_AUTOSTATE(3);
977 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, evergreen->DB_ALPHA_TO_MASK.u32All);
978 END_BATCH();
979
980 rrb = radeon_get_depthbuffer(&context->radeon);
981 if( (rrb != NULL) && (rrb->bo != NULL) )
982 {
983
984 /* make the hw happy */
985 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
986 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All);
987 R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All,
988 rrb->bo,
989 evergreen->DB_HTILE_DATA_BASE.u32All,
990 0, RADEON_GEM_DOMAIN_VRAM, 0);
991 END_BATCH();
992
993 //5
994 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
995 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All);
996 R600_OUT_BATCH_RELOC(evergreen->DB_Z_INFO.u32All,
997 rrb->bo,
998 evergreen->DB_Z_INFO.u32All,
999 0, RADEON_GEM_DOMAIN_VRAM, 0);
1000 END_BATCH();
1001
1002 //5
1003 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_ENABLE_bit) > 0)
1004 {
1005 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1006 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_READ_BASE, evergreen->DB_Z_READ_BASE.u32All);
1007 R600_OUT_BATCH_RELOC(evergreen->DB_Z_READ_BASE.u32All,
1008 rrb->bo,
1009 evergreen->DB_Z_READ_BASE.u32All,
1010 0, RADEON_GEM_DOMAIN_VRAM, 0);
1011 END_BATCH();
1012 }
1013 //5
1014 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_WRITE_ENABLE_bit) > 0)
1015 {
1016 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1017 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_WRITE_BASE, evergreen->DB_Z_READ_BASE.u32All);
1018 R600_OUT_BATCH_RELOC(evergreen->DB_Z_WRITE_BASE.u32All,
1019 rrb->bo,
1020 evergreen->DB_Z_WRITE_BASE.u32All,
1021 0, RADEON_GEM_DOMAIN_VRAM, 0);
1022 END_BATCH();
1023 }
1024 }
1025 /*
1026 if (ctx->DrawBuffer)
1027 {
1028 rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
1029
1030 if((rrb != NULL) && (rrb->bo != NULL))
1031 {
1032 //5
1033 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1034 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_Z_INFO.u32All);
1035 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All,
1036 rrb->bo,
1037 evergreen->DB_STENCIL_INFO.u32All,
1038 0, RADEON_GEM_DOMAIN_VRAM, 0);
1039 END_BATCH();
1040
1041 //10
1042 if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
1043 {
1044 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1045 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
1046 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
1047 rrb->bo,
1048 evergreen->DB_STENCIL_READ_BASE.u32All,
1049 0, RADEON_GEM_DOMAIN_VRAM, 0);
1050 END_BATCH();
1051
1052 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1053 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
1054 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
1055 rrb->bo,
1056 evergreen->DB_STENCIL_WRITE_BASE.u32All,
1057 0, RADEON_GEM_DOMAIN_VRAM, 0);
1058 END_BATCH();
1059 }
1060 }
1061 }
1062 */
1063 COMMIT_BATCH();
1064 }
1065
1066 static void evergreenSetRenderTarget(context_t *context, int id)
1067 {
1068 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1069 uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM, source_format = 1;
1070 struct radeon_renderbuffer *rrb;
1071 unsigned int nPitchInPixel;
1072
1073 rrb = radeon_get_colorbuffer(&context->radeon);
1074 if (!rrb || !rrb->bo) {
1075 return;
1076 }
1077
1078 EVERGREEN_STATECHANGE(context, cb);
1079
1080 /* addr */
1081 evergreen->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
1082
1083 /* pitch */
1084 nPitchInPixel = rrb->pitch/rrb->cpp;
1085
1086 SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1,
1087 EG_CB_COLOR0_PITCH__TILE_MAX_shift,
1088 EG_CB_COLOR0_PITCH__TILE_MAX_mask);
1089
1090 /* slice */
1091 SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All,
1092 ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1093 EG_CB_COLOR0_SLICE__TILE_MAX_shift,
1094 EG_CB_COLOR0_SLICE__TILE_MAX_mask);
1095
1096 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
1097 SETbit(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All,
1098 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
1099
1100 /* CB_COLOR0_INFO */
1101 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1102 ENDIAN_NONE,
1103 EG_CB_COLOR0_INFO__ENDIAN_shift,
1104 EG_CB_COLOR0_INFO__ENDIAN_mask);
1105 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1106 ARRAY_LINEAR_GENERAL,
1107 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1108 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1109
1110 switch (rrb->base.Format) {
1111 case MESA_FORMAT_RGBA8888:
1112 format = COLOR_8_8_8_8;
1113 comp_swap = SWAP_STD_REV;
1114 number_type = NUMBER_UNORM;
1115 source_format = 1;
1116 break;
1117 case MESA_FORMAT_SIGNED_RGBA8888:
1118 format = COLOR_8_8_8_8;
1119 comp_swap = SWAP_STD_REV;
1120 number_type = NUMBER_SNORM;
1121 source_format = 1;
1122 break;
1123 case MESA_FORMAT_RGBA8888_REV:
1124 format = COLOR_8_8_8_8;
1125 comp_swap = SWAP_STD;
1126 number_type = NUMBER_UNORM;
1127 source_format = 1;
1128 break;
1129 case MESA_FORMAT_SIGNED_RGBA8888_REV:
1130 format = COLOR_8_8_8_8;
1131 comp_swap = SWAP_STD;
1132 number_type = NUMBER_SNORM;
1133 source_format = 1;
1134 break;
1135 case MESA_FORMAT_ARGB8888:
1136 case MESA_FORMAT_XRGB8888:
1137 format = COLOR_8_8_8_8;
1138 comp_swap = SWAP_ALT;
1139 number_type = NUMBER_UNORM;
1140 source_format = 1;
1141 break;
1142 case MESA_FORMAT_ARGB8888_REV:
1143 case MESA_FORMAT_XRGB8888_REV:
1144 format = COLOR_8_8_8_8;
1145 comp_swap = SWAP_ALT_REV;
1146 number_type = NUMBER_UNORM;
1147 source_format = 1;
1148 break;
1149 case MESA_FORMAT_RGB565:
1150 format = COLOR_5_6_5;
1151 comp_swap = SWAP_STD_REV;
1152 number_type = NUMBER_UNORM;
1153 source_format = 1;
1154 break;
1155 case MESA_FORMAT_RGB565_REV:
1156 format = COLOR_5_6_5;
1157 comp_swap = SWAP_STD;
1158 number_type = NUMBER_UNORM;
1159 source_format = 1;
1160 break;
1161 case MESA_FORMAT_ARGB4444:
1162 format = COLOR_4_4_4_4;
1163 comp_swap = SWAP_ALT;
1164 number_type = NUMBER_UNORM;
1165 source_format = 1;
1166 break;
1167 case MESA_FORMAT_ARGB4444_REV:
1168 format = COLOR_4_4_4_4;
1169 comp_swap = SWAP_ALT_REV;
1170 number_type = NUMBER_UNORM;
1171 source_format = 1;
1172 break;
1173 case MESA_FORMAT_ARGB1555:
1174 format = COLOR_1_5_5_5;
1175 comp_swap = SWAP_ALT;
1176 number_type = NUMBER_UNORM;
1177 source_format = 1;
1178 break;
1179 case MESA_FORMAT_ARGB1555_REV:
1180 format = COLOR_1_5_5_5;
1181 comp_swap = SWAP_ALT_REV;
1182 number_type = NUMBER_UNORM;
1183 source_format = 1;
1184 break;
1185 case MESA_FORMAT_AL88:
1186 format = COLOR_8_8;
1187 comp_swap = SWAP_STD;
1188 number_type = NUMBER_UNORM;
1189 source_format = 1;
1190 break;
1191 case MESA_FORMAT_AL88_REV:
1192 format = COLOR_8_8;
1193 comp_swap = SWAP_STD_REV;
1194 number_type = NUMBER_UNORM;
1195 source_format = 1;
1196 break;
1197 case MESA_FORMAT_RGB332:
1198 format = COLOR_3_3_2;
1199 comp_swap = SWAP_STD_REV;
1200 number_type = NUMBER_UNORM;
1201 source_format = 1;
1202 break;
1203 case MESA_FORMAT_A8:
1204 format = COLOR_8;
1205 comp_swap = SWAP_ALT_REV;
1206 number_type = NUMBER_UNORM;
1207 source_format = 1;
1208 break;
1209 case MESA_FORMAT_I8:
1210 case MESA_FORMAT_CI8:
1211 format = COLOR_8;
1212 comp_swap = SWAP_STD;
1213 number_type = NUMBER_UNORM;
1214 source_format = 1;
1215 break;
1216 case MESA_FORMAT_L8:
1217 format = COLOR_8;
1218 comp_swap = SWAP_ALT;
1219 number_type = NUMBER_UNORM;
1220 source_format = 1;
1221 break;
1222 case MESA_FORMAT_RGBA_FLOAT32:
1223 format = COLOR_32_32_32_32_FLOAT;
1224 comp_swap = SWAP_STD_REV;
1225 number_type = NUMBER_FLOAT;
1226 source_format = 0;
1227 break;
1228 case MESA_FORMAT_RGBA_FLOAT16:
1229 format = COLOR_16_16_16_16_FLOAT;
1230 comp_swap = SWAP_STD_REV;
1231 number_type = NUMBER_FLOAT;
1232 source_format = 0;
1233 break;
1234 case MESA_FORMAT_ALPHA_FLOAT32:
1235 format = COLOR_32_FLOAT;
1236 comp_swap = SWAP_ALT_REV;
1237 number_type = NUMBER_FLOAT;
1238 source_format = 0;
1239 break;
1240 case MESA_FORMAT_ALPHA_FLOAT16:
1241 format = COLOR_16_FLOAT;
1242 comp_swap = SWAP_ALT_REV;
1243 number_type = NUMBER_FLOAT;
1244 source_format = 0;
1245 break;
1246 case MESA_FORMAT_LUMINANCE_FLOAT32:
1247 format = COLOR_32_FLOAT;
1248 comp_swap = SWAP_ALT;
1249 number_type = NUMBER_FLOAT;
1250 source_format = 0;
1251 break;
1252 case MESA_FORMAT_LUMINANCE_FLOAT16:
1253 format = COLOR_16_FLOAT;
1254 comp_swap = SWAP_ALT;
1255 number_type = NUMBER_FLOAT;
1256 source_format = 0;
1257 break;
1258 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
1259 format = COLOR_32_32_FLOAT;
1260 comp_swap = SWAP_ALT_REV;
1261 number_type = NUMBER_FLOAT;
1262 source_format = 0;
1263 break;
1264 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
1265 format = COLOR_16_16_FLOAT;
1266 comp_swap = SWAP_ALT_REV;
1267 number_type = NUMBER_FLOAT;
1268 source_format = 0;
1269 break;
1270 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
1271 format = COLOR_32_FLOAT;
1272 comp_swap = SWAP_STD;
1273 number_type = NUMBER_FLOAT;
1274 source_format = 0;
1275 break;
1276 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
1277 format = COLOR_16_FLOAT;
1278 comp_swap = SWAP_STD;
1279 number_type = NUMBER_UNORM;
1280 source_format = 0;
1281 break;
1282 case MESA_FORMAT_X8_Z24:
1283 case MESA_FORMAT_S8_Z24:
1284 format = COLOR_8_24;
1285 comp_swap = SWAP_STD;
1286 number_type = NUMBER_UNORM;
1287 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1288 ARRAY_1D_TILED_THIN1,
1289 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1290 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1291 source_format = 0;
1292 break;
1293 case MESA_FORMAT_Z24_S8:
1294 format = COLOR_24_8;
1295 comp_swap = SWAP_STD;
1296 number_type = NUMBER_UNORM;
1297 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1298 ARRAY_1D_TILED_THIN1,
1299 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1300 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1301 source_format = 0;
1302 break;
1303 case MESA_FORMAT_Z16:
1304 format = COLOR_16;
1305 comp_swap = SWAP_STD;
1306 number_type = NUMBER_UNORM;
1307 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1308 ARRAY_1D_TILED_THIN1,
1309 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1310 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1311 source_format = 0;
1312 break;
1313 case MESA_FORMAT_Z32:
1314 format = COLOR_32;
1315 comp_swap = SWAP_STD;
1316 number_type = NUMBER_UNORM;
1317 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1318 ARRAY_1D_TILED_THIN1,
1319 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1320 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1321 source_format = 0;
1322 break;
1323 case MESA_FORMAT_SARGB8:
1324 format = COLOR_8_8_8_8;
1325 comp_swap = SWAP_ALT;
1326 number_type = NUMBER_SRGB;
1327 source_format = 1;
1328 break;
1329 case MESA_FORMAT_SLA8:
1330 format = COLOR_8_8;
1331 comp_swap = SWAP_ALT_REV;
1332 number_type = NUMBER_SRGB;
1333 source_format = 1;
1334 break;
1335 case MESA_FORMAT_SL8:
1336 format = COLOR_8;
1337 comp_swap = SWAP_ALT_REV;
1338 number_type = NUMBER_SRGB;
1339 source_format = 1;
1340 break;
1341 default:
1342 _mesa_problem(context->radeon.glCtx, "unexpected format in evergreenSetRenderTarget()");
1343 break;
1344 }
1345
1346 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1347 format,
1348 EG_CB_COLOR0_INFO__FORMAT_shift,
1349 EG_CB_COLOR0_INFO__FORMAT_mask);
1350 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1351 comp_swap,
1352 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1353 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1354 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1355 number_type,
1356 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
1357 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
1358 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1359 source_format,
1360 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
1361 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
1362 SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1363 EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
1364
1365 evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
1366 evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
1367 evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
1368 evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
1369
1370 evergreen->render_target[id].enabled = GL_TRUE;
1371 }
1372
1373 static void evergreenSendCB(GLcontext *ctx, struct radeon_state_atom *atom)
1374 {
1375 context_t *context = EVERGREEN_CONTEXT(ctx);
1376 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1377 struct radeon_renderbuffer *rrb;
1378 BATCH_LOCALS(&context->radeon);
1379 int id = 0;
1380 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1381
1382 rrb = radeon_get_colorbuffer(&context->radeon);
1383 if (!rrb || !rrb->bo) {
1384 return;
1385 }
1386
1387 evergreenSetRenderTarget(context, 0);
1388
1389 if (!evergreen->render_target[id].enabled)
1390 return;
1391
1392 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1393 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
1394 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_BASE.u32All);
1395 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1396 rrb->bo,
1397 evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1398 0, RADEON_GEM_DOMAIN_VRAM, 0);
1399 END_BATCH();
1400
1401 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1402 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, evergreen->render_target[id].CB_COLOR0_INFO.u32All);
1403 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1404 rrb->bo,
1405 evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1406 0, RADEON_GEM_DOMAIN_VRAM, 0);
1407 END_BATCH();
1408
1409 BEGIN_BATCH_NO_AUTOSTATE(5);
1410 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
1411 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_PITCH.u32All);
1412 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_SLICE.u32All);
1413 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_VIEW.u32All);
1414 END_BATCH();
1415
1416 BEGIN_BATCH_NO_AUTOSTATE(4);
1417 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2);
1418 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All);
1419 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_DIM.u32All);
1420 /*
1421 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
1422 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
1423 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
1424 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
1425 */
1426 END_BATCH();
1427
1428 BEGIN_BATCH_NO_AUTOSTATE(4);
1429 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_TARGET_MASK, 2);
1430 R600_OUT_BATCH(evergreen->CB_TARGET_MASK.u32All);
1431 R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All);
1432 END_BATCH();
1433
1434 BEGIN_BATCH_NO_AUTOSTATE(6);
1435 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 4);
1436 R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All);
1437 R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All);
1438 R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All);
1439 R600_OUT_BATCH(evergreen->CB_BLEND_ALPHA.u32All);
1440 END_BATCH();
1441
1442 BEGIN_BATCH_NO_AUTOSTATE(6);
1443 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All);
1444 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All);
1445 END_BATCH();
1446
1447 COMMIT_BATCH();
1448 }
1449
1450 static void evergreenSendVGT(GLcontext *ctx, struct radeon_state_atom *atom)
1451 {
1452 context_t *context = EVERGREEN_CONTEXT(ctx);
1453 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1454 BATCH_LOCALS(&context->radeon);
1455 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1456
1457 /* moved to draw:
1458 VGT_DRAW_INITIATOR
1459 VGT_INDEX_TYPE
1460 VGT_PRIMITIVE_TYPE
1461 */
1462 BEGIN_BATCH_NO_AUTOSTATE(5);
1463 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 3);
1464 R600_OUT_BATCH(evergreen->VGT_MAX_VTX_INDX.u32All);
1465 R600_OUT_BATCH(evergreen->VGT_MIN_VTX_INDX.u32All);
1466 R600_OUT_BATCH(evergreen->VGT_INDX_OFFSET.u32All);
1467 END_BATCH();
1468
1469 BEGIN_BATCH_NO_AUTOSTATE(6);
1470 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_OUTPUT_PATH_CNTL, evergreen->VGT_OUTPUT_PATH_CNTL.u32All);
1471
1472 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_GS_MODE, evergreen->VGT_GS_MODE.u32All);
1473 END_BATCH();
1474
1475 BEGIN_BATCH_NO_AUTOSTATE(3);
1476 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVEID_EN, 1);
1477 R600_OUT_BATCH(evergreen->VGT_PRIMITIVEID_EN.u32All);
1478 END_BATCH();
1479
1480 BEGIN_BATCH_NO_AUTOSTATE(4);
1481 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1482 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_0.u32All);
1483 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_1.u32All);
1484 END_BATCH();
1485
1486 BEGIN_BATCH_NO_AUTOSTATE(4);
1487 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1488 R600_OUT_BATCH(evergreen->VGT_REUSE_OFF.u32All);
1489 R600_OUT_BATCH(evergreen->VGT_VTX_CNT_EN.u32All);
1490 END_BATCH();
1491
1492 BEGIN_BATCH_NO_AUTOSTATE(3);
1493 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, evergreen->VGT_SHADER_STAGES_EN.u32All);
1494 END_BATCH();
1495
1496 BEGIN_BATCH_NO_AUTOSTATE(4);
1497 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1498 R600_OUT_BATCH(evergreen->VGT_STRMOUT_CONFIG.u32All);
1499 R600_OUT_BATCH(evergreen->VGT_STRMOUT_BUFFER_CONFIG.u32All);
1500 END_BATCH();
1501
1502 COMMIT_BATCH();
1503 }
1504
1505 void evergreenInitAtoms(context_t *context)
1506 {
1507 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1508 context->radeon.hw.max_state_size = 10 + 5 + 14 + 3; /* start 3d, idle, cb/db flush, 3 for time stamp */
1509
1510 /* Setup the atom linked list */
1511 make_empty_list(&context->radeon.hw.atomlist);
1512 context->radeon.hw.atomlist.name = "atom-list";
1513
1514 EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
1515 EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (6 + (VERT_ATTRIB_MAX * 12)), evergreenSendVTX);
1516 EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA);
1517 EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP);
1518 EVERGREEN_ALLOC_STATE(sq, always, 86, evergreenSendSQ); /* 85 */
1519 EVERGREEN_ALLOC_STATE(vs, always, 16, evergreenSendVSresource);
1520 EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI);
1521 EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX);
1522 EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */
1523 EVERGREEN_ALLOC_STATE(db, always, 65, evergreenSendDB);
1524 EVERGREEN_ALLOC_STATE(cb, always, 33, evergreenSendCB);
1525 EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
1526
1527 evergreen_init_query_stateobj(&context->radeon, 6 * 2);
1528
1529 context->radeon.hw.is_dirty = GL_TRUE;
1530 context->radeon.hw.all_dirty = GL_TRUE;
1531 }