projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600c: add support for more rendering formats on evergreen
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_chip.c
1 /*
2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/imports.h"
28 #include "main/glheader.h"
29 #include "main/simple_list.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "evergreen_chip.h"
35 #include "evergreen_off.h"
36 #include "evergreen_diff.h"
37 #include "evergreen_fragprog.h"
38 #include "evergreen_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 void evergreenCreateChip(context_t *context)
43 {
44 EVERGREEN_CHIP_CONTEXT * evergreen =
45 (EVERGREEN_CHIP_CONTEXT*) CALLOC(sizeof(EVERGREEN_CHIP_CONTEXT));
46
47 context->pChip = (void*)evergreen;
48 }
49
50 #define EVERGREEN_ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
51 do { \
52 context->evergreen_atoms.ATOM.cmd_size = (SZ); \
53 context->evergreen_atoms.ATOM.cmd = NULL; \
54 context->evergreen_atoms.ATOM.name = #ATOM; \
55 context->evergreen_atoms.ATOM.idx = 0; \
56 context->evergreen_atoms.ATOM.check = check_##CHK; \
57 context->evergreen_atoms.ATOM.dirty = GL_FALSE; \
58 context->evergreen_atoms.ATOM.emit = (EMIT); \
59 context->radeon.hw.max_state_size += (SZ); \
60 insert_at_tail(&context->radeon.hw.atomlist, &context->evergreen_atoms.ATOM); \
61 } while (0)
62
63 /*
64 static void evergreen_init_query_stateobj(radeonContextPtr radeon, int SZ)
65 {
66 radeon->query.queryobj.cmd_size = (SZ);
67 radeon->query.queryobj.cmd = NULL;
68 radeon->query.queryobj.name = "queryobj";
69 radeon->query.queryobj.idx = 0;
70 radeon->query.queryobj.check = check_queryobj;
71 radeon->query.queryobj.dirty = GL_FALSE;
72 radeon->query.queryobj.emit = r700SendQueryBegin;
73 radeon->hw.max_state_size += (SZ);
74 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
75 }
76 */
77
78 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
79 {
80 return atom->cmd_size;
81 }
82
83 static void evergreenSendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
84 {
85 context_t *context = EVERGREEN_CONTEXT(ctx);
86 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
87
88 struct evergreen_vertex_program *vp = context->selected_vp;
89
90 struct radeon_bo *bo = NULL;
91 unsigned int i;
92 unsigned int nBorderSet = 0;
93 BATCH_LOCALS(&context->radeon);
94
95 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
96
97 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
98 if (ctx->Texture.Unit[i]._ReallyEnabled) {
99 radeonTexObj *t = evergreen->textures[i];
100
101 if (t) {
102 /* Tex resource */
103 if (!t->image_override) {
104 bo = t->mt->bo;
105 } else {
106 bo = t->bo;
107 }
108 if (bo)
109 {
110 radeon_bo_unmap(bo);
111
112 r700SyncSurf(context, bo,
113 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
114 0, TC_ACTION_ENA_bit);
115
116 BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
117 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
118
119 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
120 { /* vs texture */
121 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
122 }
123 else
124 {
125 R600_OUT_BATCH(i * EG_FETCH_RESOURCE_STRIDE);
126 }
127
128 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE0);
129 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE1);
130 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE2);
131 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE3);
132 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE4);
133 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE5);
134 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE6);
135 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_RESOURCE7);
136
137 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE2,
138 bo,
139 evergreen->textures[i]->SQ_TEX_RESOURCE2,
140 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
141 R600_OUT_BATCH_RELOC(evergreen->textures[i]->SQ_TEX_RESOURCE3,
142 bo,
143 evergreen->textures[i]->SQ_TEX_RESOURCE3,
144 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
145 END_BATCH();
146 COMMIT_BATCH();
147 }
148 /* Tex sampler */
149 BEGIN_BATCH_NO_AUTOSTATE(5);
150 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
151
152 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
153 { /* vs texture */
154 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * 3);
155 }
156 else
157 {
158 R600_OUT_BATCH(i * 3);
159 }
160 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER0);
161 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER1);
162 R600_OUT_BATCH(evergreen->textures[i]->SQ_TEX_SAMPLER2);
163
164 END_BATCH();
165 COMMIT_BATCH();
166
167 /* Tex border color */
168 if(0 == nBorderSet)
169 {
170 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
171 R600_OUT_BATCH_REGSEQ(EG_TD_PS_BORDER_COLOR_RED, 4);
172 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
173 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
174 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
175 R600_OUT_BATCH(evergreen->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
176 END_BATCH();
177 COMMIT_BATCH();
178
179 nBorderSet = 1;
180 }
181 }
182 }
183 }
184 }
185
186 static int check_evergreen_tx(GLcontext *ctx, struct radeon_state_atom *atom)
187 {
188 context_t *context = EVERGREEN_CONTEXT(ctx);
189 unsigned int i, count = 0;
190 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
191
192 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
193 if (ctx->Texture.Unit[i]._ReallyEnabled) {
194 radeonTexObj *t = evergreen->textures[i];
195 if (t)
196 count++;
197 }
198 }
199 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
200 return count * 37 + 6;
201 }
202
203 static void evergreenSendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
204 {
205 context_t *context = EVERGREEN_CONTEXT(ctx);
206 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
207 BATCH_LOCALS(&context->radeon);
208 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
209
210 BEGIN_BATCH_NO_AUTOSTATE(19);
211 //6
212 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL, evergreen->evergreen_config.SPI_CONFIG_CNTL.u32All);
213 EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_CONFIG_CNTL_1, evergreen->evergreen_config.SPI_CONFIG_CNTL_1.u32All);
214 //6
215 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
216 R600_OUT_BATCH(evergreen->evergreen_config.SQ_CONFIG.u32All);
217 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
218 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
219 R600_OUT_BATCH(evergreen->evergreen_config.SQ_GPR_RESOURCE_MGMT_3.u32All);
220 //7
221 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
222 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT.u32All);
223 R600_OUT_BATCH(evergreen->evergreen_config.SQ_THREAD_RESOURCE_MGMT_2.u32All);
224 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
225 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
226 R600_OUT_BATCH(evergreen->evergreen_config.SQ_STACK_RESOURCE_MGMT_3.u32All);
227
228 END_BATCH();
229
230 COMMIT_BATCH();
231 }
232
233 extern int evergreen_getTypeSize(GLenum type);
234 static void evergreenSetupVTXConstants(GLcontext * ctx,
235 void * pAos,
236 StreamDesc * pStreamDesc)
237 {
238 context_t *context = EVERGREEN_CONTEXT(ctx);
239 struct radeon_aos * paos = (struct radeon_aos *)pAos;
240 unsigned int nVBsize;
241 BATCH_LOCALS(&context->radeon);
242
243 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
244 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
245 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
246 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
247 unsigned int uSQ_VTX_CONSTANT_WORD7_0 = 0;
248
249 if (!paos->bo)
250 return;
251
252 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
253
254 if(0 == pStreamDesc->stride)
255 {
256 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
257 }
258 else
259 {
260 nVBsize = (paos->count - 1) * pStreamDesc->stride
261 + pStreamDesc->size * getTypeSize(pStreamDesc->type);
262 }
263
264 //uSQ_VTX_CONSTANT_WORD0_0
265 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
266
267 //uSQ_VTX_CONSTANT_WORD1_0
268 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize;
269
270 //uSQ_VTX_CONSTANT_WORD2_0
271 SETfield(uSQ_VTX_CONSTANT_WORD2_0,
272 pStreamDesc->stride,
273 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
274 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
275 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
276 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
277 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); // TODO : trace back api for initial data type, not only GL_FLOAT
278 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); // TODO
279 if(GL_TRUE == pStreamDesc->normalize)
280 {
281 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
282 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
283 }
284 else
285 {
286 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
287 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
288 }
289 if(1 == pStreamDesc->_signed)
290 {
291 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
292 }
293
294 //uSQ_VTX_CONSTANT_WORD3_0
295 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_X,
296 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
297 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
298 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Y,
299 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
300 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
301 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_Z,
302 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
303 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
304 SETfield(uSQ_VTX_CONSTANT_WORD3_0, SQ_SEL_W,
305 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
306 EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
307
308 //uSQ_VTX_CONSTANT_WORD7_0
309 SETfield(uSQ_VTX_CONSTANT_WORD7_0, SQ_TEX_VTX_VALID_BUFFER,
310 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
311
312 BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
313
314 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
315 R600_OUT_BATCH((pStreamDesc->element + EG_SQ_FETCH_RESOURCE_VS_OFFSET) * EG_FETCH_RESOURCE_STRIDE);
316 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
317 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
318 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
319 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
320 R600_OUT_BATCH(0);
321 R600_OUT_BATCH(0);
322 R600_OUT_BATCH(0);
323 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD7_0);
324 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
325 paos->bo,
326 uSQ_VTX_CONSTANT_WORD0_0,
327 RADEON_GEM_DOMAIN_GTT, 0, 0);
328 END_BATCH();
329
330 COMMIT_BATCH();
331 }
332
333 static int check_evergreen_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
334 {
335 context_t *context = EVERGREEN_CONTEXT(ctx);
336 int count = context->radeon.tcl.aos_count * 12;
337
338 if (count)
339 count += 6;
340
341 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
342 return count;
343 }
344
345 static void evergreenSendVTX(GLcontext *ctx, struct radeon_state_atom *atom)
346 {
347 context_t *context = EVERGREEN_CONTEXT(ctx);
348 struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *)(context->selected_vp);
349 unsigned int i, j = 0;
350 BATCH_LOCALS(&context->radeon);
351 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
352
353 if (context->radeon.tcl.aos_count == 0)
354 return;
355
356 BEGIN_BATCH_NO_AUTOSTATE(6);
357 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
358 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
359 R600_OUT_BATCH(0);
360
361 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
362 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
363 R600_OUT_BATCH(0);
364 END_BATCH();
365 COMMIT_BATCH();
366
367 for(i=0; i<VERT_ATTRIB_MAX; i++) {
368 if(vp->mesa_program->Base.InputsRead & (1 << i))
369 {
370 evergreenSetupVTXConstants(ctx,
371 (void*)(&context->radeon.tcl.aos[j]),
372 &(context->stream_desc[j]));
373 j++;
374 }
375 }
376 }
377 static void evergreenSendPA(GLcontext *ctx, struct radeon_state_atom *atom)
378 {
379 context_t *context = EVERGREEN_CONTEXT(ctx);
380 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
381 BATCH_LOCALS(&context->radeon);
382 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
383 int id = 0;
384
385 BEGIN_BATCH_NO_AUTOSTATE(3);
386 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
387 END_BATCH();
388
389 BEGIN_BATCH_NO_AUTOSTATE(22);
390 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
391 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All);
392 R600_OUT_BATCH(evergreen->PA_SC_SCREEN_SCISSOR_BR.u32All);
393
394 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 12);
395 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_OFFSET.u32All);
396 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_TL.u32All);
397 R600_OUT_BATCH(evergreen->PA_SC_WINDOW_SCISSOR_BR.u32All);
398 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_RULE.u32All);
399 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_TL.u32All);
400 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_0_BR.u32All);
401 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_TL.u32All);
402 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_1_BR.u32All);
403 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_TL.u32All);
404 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_2_BR.u32All);
405 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_TL.u32All);
406 R600_OUT_BATCH(evergreen->PA_SC_CLIPRECT_3_BR.u32All);
407
408 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
409 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_TL.u32All);
410 R600_OUT_BATCH(evergreen->PA_SC_GENERIC_SCISSOR_BR.u32All);
411 END_BATCH();
412
413 BEGIN_BATCH_NO_AUTOSTATE(3);
414 EVERGREEN_OUT_BATCH_REGVAL(EG_PA_SC_EDGERULE, evergreen->PA_SC_EDGERULE.u32All);
415 END_BATCH();
416
417
418 BEGIN_BATCH_NO_AUTOSTATE(18);
419 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 4);
420 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
421 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
422 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
423 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
424
425 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
426 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
427 R600_OUT_BATCH(evergreen->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
428
429 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_VPORT_XSCALE, 6);
430 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XSCALE.u32All);
431 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
432 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YSCALE.u32All);
433 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
434 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
435 R600_OUT_BATCH(evergreen->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
436 END_BATCH();
437
438
439 for (id = 0; id < EVERGREEN_MAX_UCP; id++) {
440 if (evergreen->ucp[id].enabled) {
441 BEGIN_BATCH_NO_AUTOSTATE(6);
442 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_UCP_0_X + (4 * id), 4);
443 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_X.u32All);
444 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Y.u32All);
445 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_Z.u32All);
446 R600_OUT_BATCH(evergreen->ucp[id].PA_CL_UCP_0_W.u32All);
447 END_BATCH();
448 }
449 }
450
451 BEGIN_BATCH_NO_AUTOSTATE(42);
452 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_CL_CLIP_CNTL, 5);
453 R600_OUT_BATCH(evergreen->PA_CL_CLIP_CNTL.u32All);
454 R600_OUT_BATCH(evergreen->PA_SU_SC_MODE_CNTL.u32All);
455 R600_OUT_BATCH(evergreen->PA_CL_VTE_CNTL.u32All);
456 R600_OUT_BATCH(evergreen->PA_CL_VS_OUT_CNTL.u32All);
457 R600_OUT_BATCH(evergreen->PA_CL_NANINF_CNTL.u32All);
458
459 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 3);
460 R600_OUT_BATCH(evergreen->PA_SU_POINT_SIZE.u32All);
461 R600_OUT_BATCH(evergreen->PA_SU_POINT_MINMAX.u32All);
462 R600_OUT_BATCH(evergreen->PA_SU_LINE_CNTL.u32All);
463
464 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
465 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_0.u32All);
466 R600_OUT_BATCH(evergreen->PA_SC_MODE_CNTL_1.u32All);
467
468 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
469 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
470 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_CLAMP.u32All);
471 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
472 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
473 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
474 R600_OUT_BATCH(evergreen->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
475
476 EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
477 R600_OUT_BATCH(evergreen->PA_SC_LINE_CNTL.u32All);
478 R600_OUT_BATCH(evergreen->PA_SC_AA_CONFIG.u32All);
479 R600_OUT_BATCH(evergreen->PA_SU_VTX_CNTL.u32All);
480 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_CLIP_ADJ.u32All);
481 R600_OUT_BATCH(evergreen->PA_CL_GB_VERT_DISC_ADJ.u32All);
482 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
483 R600_OUT_BATCH(evergreen->PA_CL_GB_HORZ_DISC_ADJ.u32All);
484 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_0.u32All);
485 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_1.u32All);
486 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_2.u32All);
487 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_3.u32All);
488 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_4.u32All);
489 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_5.u32All);
490 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_6.u32All);
491 R600_OUT_BATCH(evergreen->PA_SC_AA_SAMPLE_LOCS_7.u32All);
492 R600_OUT_BATCH(evergreen->PA_SC_AA_MASK.u32All);
493
494 END_BATCH();
495
496 COMMIT_BATCH();
497 }
498 static void evergreenSendTP(GLcontext *ctx, struct radeon_state_atom *atom)
499 {
500 /*
501 context_t *context = EVERGREEN_CONTEXT(ctx);
502 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
503 BATCH_LOCALS(&context->radeon);
504 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
505
506 COMMIT_BATCH();
507 */
508 }
509
510 static void evergreenSendPSresource(GLcontext *ctx)
511 {
512 context_t *context = EVERGREEN_CONTEXT(ctx);
513 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
514 struct radeon_bo * pbo;
515
516 struct radeon_bo * pbo_const;
517
518 BATCH_LOCALS(&context->radeon);
519 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
520
521 pbo = (struct radeon_bo *)evergreenGetActiveFpShaderBo(GL_CONTEXT(context));
522
523 if (!pbo)
524 return;
525
526 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
527
528 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
529 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
530 R600_OUT_BATCH(evergreen->ps.SQ_PGM_START_PS.u32All);
531 R600_OUT_BATCH_RELOC(evergreen->ps.SQ_PGM_START_PS.u32All,
532 pbo,
533 evergreen->ps.SQ_PGM_START_PS.u32All,
534 RADEON_GEM_DOMAIN_GTT, 0, 0);
535 END_BATCH();
536
537 BEGIN_BATCH_NO_AUTOSTATE(3);
538 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LOOP_CONST_0, 0x01000FFF);
539 END_BATCH();
540
541 pbo_const = (struct radeon_bo *)(context->fp_Constbo);
542
543 if(NULL != pbo_const)
544 {
545 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
546
547 BEGIN_BATCH_NO_AUTOSTATE(3);
548
549 if(evergreen->ps.num_consts < 4)
550 {
551 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, 1);
552 }
553 else
554 {
555 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0, (evergreen->ps.num_consts * 4)/16 );
556 }
557
558 END_BATCH();
559
560 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
561 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_PS_0, 1);
562 R600_OUT_BATCH(context->fp_bo_offset >> 8);
563 R600_OUT_BATCH_RELOC(0,
564 pbo_const,
565 0,
566 RADEON_GEM_DOMAIN_GTT, 0, 0);
567 END_BATCH();
568 }
569
570 COMMIT_BATCH();
571 }
572
573 static void evergreenSendVSresource(GLcontext *ctx, struct radeon_state_atom *atom)
574 {
575 context_t *context = EVERGREEN_CONTEXT(ctx);
576 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
577 struct radeon_bo * pbo;
578
579 struct radeon_bo * pbo_const;
580
581 BATCH_LOCALS(&context->radeon);
582 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
583
584 pbo = (struct radeon_bo *)evergreenGetActiveVpShaderBo(GL_CONTEXT(context));
585
586 if (!pbo)
587 return;
588
589 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
590
591 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
592 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
593 R600_OUT_BATCH(evergreen->vs.SQ_PGM_START_VS.u32All);
594 R600_OUT_BATCH_RELOC(evergreen->vs.SQ_PGM_START_VS.u32All,
595 pbo,
596 evergreen->vs.SQ_PGM_START_VS.u32All,
597 RADEON_GEM_DOMAIN_GTT, 0, 0);
598 END_BATCH();
599
600 BEGIN_BATCH_NO_AUTOSTATE(3);
601 EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + 32*1), 0x0100000F); //consts == 1
602 //EVERGREEN_OUT_BATCH_REGVAL((EG_SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
603 END_BATCH();
604
605 pbo_const = (struct radeon_bo *)(context->vp_Constbo);
606
607 if(NULL != pbo_const)
608 {
609 r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
610
611 BEGIN_BATCH_NO_AUTOSTATE(3);
612
613 if(evergreen->vs.num_consts < 4)
614 {
615 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, 1);
616 }
617 else
618 {
619 EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0, (evergreen->vs.num_consts * 4)/16 );
620 }
621
622 END_BATCH();
623
624 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
625 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ALU_CONST_CACHE_VS_0, 1);
626 R600_OUT_BATCH(context->vp_bo_offset >> 8);
627 R600_OUT_BATCH_RELOC(0,
628 pbo_const,
629 0,
630 RADEON_GEM_DOMAIN_GTT, 0, 0);
631 END_BATCH();
632 }
633
634 COMMIT_BATCH();
635 }
636
637 static void evergreenSendSQ(GLcontext *ctx, struct radeon_state_atom *atom)
638 {
639 context_t *context = EVERGREEN_CONTEXT(ctx);
640 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
641 BATCH_LOCALS(&context->radeon);
642 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
643
644 evergreenSendPSresource(ctx); //16 entries now
645
646 BEGIN_BATCH_NO_AUTOSTATE(77);
647
648 //34
649 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_VTX_SEMANTIC_0, 32);
650 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_0.u32All); //// // = 0x28380, // SAME
651 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_1.u32All); //// // = 0x28384, // SAME
652 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_2.u32All); //// // = 0x28388, // SAME
653 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_3.u32All); //// // = 0x2838C, // SAME
654 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_4.u32All); //// // = 0x28390, // SAME
655 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_5.u32All); //// // = 0x28394, // SAME
656 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_6.u32All); //// // = 0x28398, // SAME
657 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_7.u32All); //// // = 0x2839C, // SAME
658 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_8.u32All); //// // = 0x283A0, // SAME
659 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_9.u32All); //// // = 0x283A4, // SAME
660 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_10.u32All); //// // = 0x283A8, // SAME
661 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_11.u32All); //// // = 0x283AC, // SAME
662 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_12.u32All); //// // = 0x283B0, // SAME
663 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_13.u32All); //// // = 0x283B4, // SAME
664 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_14.u32All); //// // = 0x283B8, // SAME
665 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_15.u32All); //// // = 0x283BC, // SAME
666 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_16.u32All); //// // = 0x283C0, // SAME
667 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_17.u32All); //// // = 0x283C4, // SAME
668 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_18.u32All); //// // = 0x283C8, // SAME
669 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_19.u32All); //// // = 0x283CC, // SAME
670 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_20.u32All); //// // = 0x283D0, // SAME
671 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_21.u32All); //// // = 0x283D4, // SAME
672 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_22.u32All); //// // = 0x283D8, // SAME
673 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_23.u32All); //// // = 0x283DC, // SAME
674 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_24.u32All); //// // = 0x283E0, // SAME
675 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_25.u32All); //// // = 0x283E4, // SAME
676 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_26.u32All); //// // = 0x283E8, // SAME
677 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_27.u32All); //// // = 0x283EC, // SAME
678 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_28.u32All); //// // = 0x283F0, // SAME
679 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_29.u32All); //// // = 0x283F4, // SAME
680 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_30.u32All); //// // = 0x283F8, // SAME
681 R600_OUT_BATCH(evergreen->SQ_VTX_SEMANTIC_31.u32All); //// // = 0x283FC, // SAME
682
683
684 //3
685 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_DYN_GPR_RESOURCE_LIMIT_1, 1);
686 R600_OUT_BATCH(evergreen->SQ_DYN_GPR_RESOURCE_LIMIT_1.u32All);//// // = 0x28838, //
687
688 //5
689 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
690 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_PS.u32All); //// // = 0x28844, // DIFF 0x28850
691 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_PS.u32All); //// // = 0x28848, //
692 R600_OUT_BATCH(evergreen->SQ_PGM_EXPORTS_PS.u32All); //// // = 0x2884C, // SAME 0x28854
693
694 //4
695 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
696 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_VS.u32All);//// // = 0x28860, // DIFF 0x28868
697 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_VS.u32All); //// // = 0x28864, //
698
699 //5
700 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_GS, 2);
701 /*
702 R600_OUT_BATCH(evergreen->SQ_PGM_START_GS.u32All); //// // = 0x28874, // SAME 0x2886C
703 */
704 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_GS.u32All); //// // = 0x28878, // DIFF 0x2887C
705 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_GS.u32All); //// // = 0x2887C, //
706
707 //5
708 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_ES, 2);
709 /*
710 R600_OUT_BATCH(evergreen->SQ_PGM_START_ES.u32All); //// // = 0x2888C, // SAME 0x28880
711 */
712 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_ES.u32All); //// // = 0x28890, // DIFF
713 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_ES.u32All); //// // = 0x28894, //
714
715 //4
716 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_FS, 1);
717 /*
718 R600_OUT_BATCH(evergreen->SQ_PGM_START_FS.u32All); //// // = 0x288A4, // SAME 0x28894
719 */
720 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_FS.u32All); //// // = 0x288A8, // DIFF 0x288A4
721
722 //3
723 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_HS, 1);
724 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_HS.u32All);//// // = 0x288C0, //
725
726 //3
727 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_2_LS, 1);
728 R600_OUT_BATCH(evergreen->SQ_PGM_RESOURCES_2_LS.u32All); //// // = 0x288D8, //
729
730 //3
731 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_LDS_ALLOC_PS, 1);
732 R600_OUT_BATCH(evergreen->SQ_LDS_ALLOC_PS.u32All); //// // = 0x288EC, //
733
734 //8
735 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
736 R600_OUT_BATCH(evergreen->SQ_ESGS_RING_ITEMSIZE.u32All); //// // = 0x28900, // SAME 0x288A8
737 R600_OUT_BATCH(evergreen->SQ_GSVS_RING_ITEMSIZE.u32All); //// // = 0x28904, // SAME 0x288AC
738 R600_OUT_BATCH(evergreen->SQ_ESTMP_RING_ITEMSIZE.u32All); //// // = 0x28908, // SAME 0x288B0
739 R600_OUT_BATCH(evergreen->SQ_GSTMP_RING_ITEMSIZE.u32All); //// // = 0x2890C, // SAME 0x288B4
740 R600_OUT_BATCH(evergreen->SQ_VSTMP_RING_ITEMSIZE.u32All); //// // = 0x28910, // SAME 0x288B8
741 R600_OUT_BATCH(evergreen->SQ_PSTMP_RING_ITEMSIZE.u32All); //// // = 0x28914, // SAME 0x288BC
742
743 //3
744 EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 1);
745 R600_OUT_BATCH(evergreen->SQ_GS_VERT_ITEMSIZE.u32All); //// // = 0x2891C, // SAME 0x288C8
746
747 END_BATCH();
748
749 COMMIT_BATCH();
750
751 }
752 static void evergreenSendSPI(GLcontext *ctx, struct radeon_state_atom *atom)
753 {
754 context_t *context = EVERGREEN_CONTEXT(ctx);
755 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
756 BATCH_LOCALS(&context->radeon);
757 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
758
759 BEGIN_BATCH_NO_AUTOSTATE(59);
760
761 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_VS_OUT_ID_0, 10);
762 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_0.u32All);
763 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_1.u32All);
764 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_2.u32All);
765 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_3.u32All);
766 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_4.u32All);
767 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_5.u32All);
768 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_6.u32All);
769 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_7.u32All);
770 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_8.u32All);
771 R600_OUT_BATCH(evergreen->SPI_VS_OUT_ID_9.u32All);
772
773 EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_INPUT_CNTL_0, 45);
774 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[0].u32All);
775 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[1].u32All);
776 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[2].u32All);
777 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[3].u32All);
778 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[4].u32All);
779 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[5].u32All);
780 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[6].u32All);
781 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[7].u32All);
782 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[8].u32All);
783 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[9].u32All);
784 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[10].u32All);
785 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[11].u32All);
786 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[12].u32All);
787 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[13].u32All);
788 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[14].u32All);
789 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[15].u32All);
790 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[16].u32All);
791 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[17].u32All);
792 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[18].u32All);
793 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[19].u32All);
794 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[20].u32All);
795 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[21].u32All);
796 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[22].u32All);
797 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[23].u32All);
798 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[24].u32All);
799 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[25].u32All);
800 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[26].u32All);
801 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[27].u32All);
802 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[28].u32All);
803 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[29].u32All);
804 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[30].u32All);
805 R600_OUT_BATCH(evergreen->SPI_PS_INPUT_CNTL[31].u32All);
806 R600_OUT_BATCH(evergreen->SPI_VS_OUT_CONFIG.u32All);
807 R600_OUT_BATCH(evergreen->SPI_THREAD_GROUPING.u32All);
808 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_0.u32All);
809 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_1.u32All);
810 R600_OUT_BATCH(evergreen->SPI_INTERP_CONTROL_0.u32All);
811 R600_OUT_BATCH(evergreen->SPI_INPUT_Z.u32All);
812 R600_OUT_BATCH(evergreen->SPI_FOG_CNTL.u32All);
813 R600_OUT_BATCH(evergreen->SPI_BARYC_CNTL.u32All);
814 R600_OUT_BATCH(evergreen->SPI_PS_IN_CONTROL_2.u32All);
815 R600_OUT_BATCH(evergreen->SPI_COMPUTE_INPUT_CNTL.u32All);
816 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_X.u32All);
817 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Y.u32All);
818 R600_OUT_BATCH(evergreen->SPI_COMPUTE_NUM_THREAD_Z.u32All);
819
820 END_BATCH();
821
822 COMMIT_BATCH();
823 }
824 static void evergreenSendSX(GLcontext *ctx, struct radeon_state_atom *atom)
825 {
826 context_t *context = EVERGREEN_CONTEXT(ctx);
827 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
828 BATCH_LOCALS(&context->radeon);
829 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
830
831 BEGIN_BATCH_NO_AUTOSTATE(9);
832
833 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, evergreen->SX_MISC.u32All);
834 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_TEST_CONTROL, evergreen->SX_ALPHA_TEST_CONTROL.u32All);
835 EVERGREEN_OUT_BATCH_REGVAL(EG_SX_ALPHA_REF, evergreen->SX_ALPHA_REF.u32All);
836
837 END_BATCH();
838
839 COMMIT_BATCH();
840 }
841
842 static void evergreenSetDepthTarget(context_t *context)
843 {
844 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
845 struct radeon_renderbuffer *rrb;
846 unsigned int nPitchInPixel;
847
848 rrb = radeon_get_depthbuffer(&context->radeon);
849 if (!rrb)
850 {
851 return;
852 }
853
854 EVERGREEN_STATECHANGE(context, db);
855
856 evergreen->DB_DEPTH_SIZE.u32All = 0;
857
858 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
859 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift,
860 EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask);
861 SETfield(evergreen->DB_DEPTH_SIZE.u32All, (context->radeon.radeonScreen->driScreen->fbHeight/8)-1,
862 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift,
863 EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask);
864 evergreen->DB_DEPTH_SLICE.u32All = ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1;
865
866 if(4 == rrb->cpp)
867 {
868 SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_8_24,
869 EG_DB_Z_INFO__FORMAT_shift,
870 EG_DB_Z_INFO__FORMAT_mask);
871 }
872 else
873 {
874 SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_16,
875 EG_DB_Z_INFO__FORMAT_shift,
876 EG_DB_Z_INFO__FORMAT_mask);
877 }
878 SETfield(evergreen->DB_Z_INFO.u32All, ARRAY_1D_TILED_THIN1,
879 EG_DB_Z_INFO__ARRAY_MODE_shift,
880 EG_DB_Z_INFO__ARRAY_MODE_mask);
881 }
882
883 static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom)
884 {
885 context_t *context = EVERGREEN_CONTEXT(ctx);
886 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
887 struct radeon_renderbuffer *rrb;
888 BATCH_LOCALS(&context->radeon);
889 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
890
891 evergreenSetDepthTarget(context);
892
893 //8
894 BEGIN_BATCH_NO_AUTOSTATE(7);
895 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
896 R600_OUT_BATCH(evergreen->DB_RENDER_CONTROL.u32All);
897 R600_OUT_BATCH(evergreen->DB_COUNT_CONTROL.u32All);
898 R600_OUT_BATCH(evergreen->DB_DEPTH_VIEW.u32All);
899 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE.u32All);
900 R600_OUT_BATCH(evergreen->DB_RENDER_OVERRIDE2.u32All);
901 END_BATCH();
902
903 //4
904 BEGIN_BATCH_NO_AUTOSTATE(4);
905 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
906 R600_OUT_BATCH(evergreen->DB_STENCIL_CLEAR.u32All);
907 R600_OUT_BATCH(evergreen->DB_DEPTH_CLEAR.u32All);
908 END_BATCH();
909
910 //4
911 BEGIN_BATCH_NO_AUTOSTATE(4);
912 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_DEPTH_SIZE, 2);
913 R600_OUT_BATCH(evergreen->DB_DEPTH_SIZE.u32All);
914 R600_OUT_BATCH(evergreen->DB_DEPTH_SLICE.u32All);
915 END_BATCH();
916
917 //3
918 BEGIN_BATCH_NO_AUTOSTATE(3);
919 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, evergreen->DB_DEPTH_CONTROL.u32All);
920 END_BATCH();
921
922 //3
923 BEGIN_BATCH_NO_AUTOSTATE(3);
924 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_SHADER_CONTROL, evergreen->DB_SHADER_CONTROL.u32All);
925 END_BATCH();
926
927 //5
928 BEGIN_BATCH_NO_AUTOSTATE(5);
929 EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_SRESULTS_COMPARE_STATE0, 3);
930 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE0.u32All);
931 R600_OUT_BATCH(evergreen->DB_SRESULTS_COMPARE_STATE1.u32All);
932 R600_OUT_BATCH(evergreen->DB_PRELOAD_CONTROL.u32All);
933 END_BATCH();
934
935 //3
936 BEGIN_BATCH_NO_AUTOSTATE(3);
937 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, evergreen->DB_ALPHA_TO_MASK.u32All);
938 END_BATCH();
939
940 rrb = radeon_get_depthbuffer(&context->radeon);
941 if( (rrb != NULL) && (rrb->bo != NULL) )
942 {
943
944 /* make the hw happy */
945 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
946 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All);
947 R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All,
948 rrb->bo,
949 evergreen->DB_HTILE_DATA_BASE.u32All,
950 0, RADEON_GEM_DOMAIN_VRAM, 0);
951 END_BATCH();
952
953 //5
954 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
955 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_INFO, evergreen->DB_Z_INFO.u32All);
956 R600_OUT_BATCH_RELOC(evergreen->DB_Z_INFO.u32All,
957 rrb->bo,
958 evergreen->DB_Z_INFO.u32All,
959 0, RADEON_GEM_DOMAIN_VRAM, 0);
960 END_BATCH();
961
962 //5
963 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_ENABLE_bit) > 0)
964 {
965 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
966 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_READ_BASE, evergreen->DB_Z_READ_BASE.u32All);
967 R600_OUT_BATCH_RELOC(evergreen->DB_Z_READ_BASE.u32All,
968 rrb->bo,
969 evergreen->DB_Z_READ_BASE.u32All,
970 0, RADEON_GEM_DOMAIN_VRAM, 0);
971 END_BATCH();
972 }
973 //5
974 if((evergreen->DB_DEPTH_CONTROL.u32All & Z_WRITE_ENABLE_bit) > 0)
975 {
976 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
977 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_Z_WRITE_BASE, evergreen->DB_Z_READ_BASE.u32All);
978 R600_OUT_BATCH_RELOC(evergreen->DB_Z_WRITE_BASE.u32All,
979 rrb->bo,
980 evergreen->DB_Z_WRITE_BASE.u32All,
981 0, RADEON_GEM_DOMAIN_VRAM, 0);
982 END_BATCH();
983 }
984 }
985 /*
986 if (ctx->DrawBuffer)
987 {
988 rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
989
990 if((rrb != NULL) && (rrb->bo != NULL))
991 {
992 //5
993 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
994 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_Z_INFO.u32All);
995 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All,
996 rrb->bo,
997 evergreen->DB_STENCIL_INFO.u32All,
998 0, RADEON_GEM_DOMAIN_VRAM, 0);
999 END_BATCH();
1000
1001 //10
1002 if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0)
1003 {
1004 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1005 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All);
1006 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All,
1007 rrb->bo,
1008 evergreen->DB_STENCIL_READ_BASE.u32All,
1009 0, RADEON_GEM_DOMAIN_VRAM, 0);
1010 END_BATCH();
1011
1012 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1013 EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All);
1014 R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All,
1015 rrb->bo,
1016 evergreen->DB_STENCIL_WRITE_BASE.u32All,
1017 0, RADEON_GEM_DOMAIN_VRAM, 0);
1018 END_BATCH();
1019 }
1020 }
1021 }
1022 */
1023 COMMIT_BATCH();
1024 }
1025
1026 static void evergreenSetRenderTarget(context_t *context, int id)
1027 {
1028 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1029 uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM, source_format = 1;
1030 struct radeon_renderbuffer *rrb;
1031 unsigned int nPitchInPixel;
1032
1033 rrb = radeon_get_colorbuffer(&context->radeon);
1034 if (!rrb || !rrb->bo) {
1035 return;
1036 }
1037
1038 EVERGREEN_STATECHANGE(context, cb);
1039
1040 /* addr */
1041 evergreen->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
1042
1043 /* pitch */
1044 nPitchInPixel = rrb->pitch/rrb->cpp;
1045
1046 SETfield(evergreen->render_target[id].CB_COLOR0_PITCH.u32All, (nPitchInPixel/8)-1,
1047 EG_CB_COLOR0_PITCH__TILE_MAX_shift,
1048 EG_CB_COLOR0_PITCH__TILE_MAX_mask);
1049
1050 /* skice */
1051 SETfield(evergreen->render_target[id].CB_COLOR0_SLICE.u32All,
1052 //( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1053 ( (nPitchInPixel * 240)/64 )-1,
1054 EG_CB_COLOR0_SLICE__TILE_MAX_shift,
1055 EG_CB_COLOR0_SLICE__TILE_MAX_mask);
1056
1057 /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
1058 SETbit(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All,
1059 EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
1060
1061 /* CB_COLOR0_INFO */
1062 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1063 ENDIAN_NONE,
1064 EG_CB_COLOR0_INFO__ENDIAN_shift,
1065 EG_CB_COLOR0_INFO__ENDIAN_mask);
1066 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1067 ARRAY_LINEAR_GENERAL,
1068 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1069 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1070
1071 switch (rrb->base.Format) {
1072 case MESA_FORMAT_RGBA8888:
1073 format = COLOR_8_8_8_8;
1074 comp_swap = SWAP_STD_REV;
1075 number_type = NUMBER_UNORM;
1076 source_format = 1;
1077 break;
1078 case MESA_FORMAT_SIGNED_RGBA8888:
1079 format = COLOR_8_8_8_8;
1080 comp_swap = SWAP_STD_REV;
1081 number_type = NUMBER_SNORM;
1082 source_format = 1;
1083 break;
1084 case MESA_FORMAT_RGBA8888_REV:
1085 format = COLOR_8_8_8_8;
1086 comp_swap = SWAP_STD;
1087 number_type = NUMBER_UNORM;
1088 source_format = 1;
1089 break;
1090 case MESA_FORMAT_SIGNED_RGBA8888_REV:
1091 format = COLOR_8_8_8_8;
1092 comp_swap = SWAP_STD;
1093 number_type = NUMBER_SNORM;
1094 source_format = 1;
1095 break;
1096 case MESA_FORMAT_ARGB8888:
1097 case MESA_FORMAT_XRGB8888:
1098 format = COLOR_8_8_8_8;
1099 comp_swap = SWAP_ALT;
1100 number_type = NUMBER_UNORM;
1101 source_format = 1;
1102 break;
1103 case MESA_FORMAT_ARGB8888_REV:
1104 case MESA_FORMAT_XRGB8888_REV:
1105 format = COLOR_8_8_8_8;
1106 comp_swap = SWAP_ALT_REV;
1107 number_type = NUMBER_UNORM;
1108 source_format = 1;
1109 break;
1110 case MESA_FORMAT_RGB565:
1111 format = COLOR_5_6_5;
1112 comp_swap = SWAP_STD_REV;
1113 number_type = NUMBER_UNORM;
1114 source_format = 1;
1115 break;
1116 case MESA_FORMAT_RGB565_REV:
1117 format = COLOR_5_6_5;
1118 comp_swap = SWAP_STD;
1119 number_type = NUMBER_UNORM;
1120 source_format = 1;
1121 break;
1122 case MESA_FORMAT_ARGB4444:
1123 format = COLOR_4_4_4_4;
1124 comp_swap = SWAP_ALT;
1125 number_type = NUMBER_UNORM;
1126 source_format = 1;
1127 break;
1128 case MESA_FORMAT_ARGB4444_REV:
1129 format = COLOR_4_4_4_4;
1130 comp_swap = SWAP_ALT_REV;
1131 number_type = NUMBER_UNORM;
1132 source_format = 1;
1133 break;
1134 case MESA_FORMAT_ARGB1555:
1135 format = COLOR_1_5_5_5;
1136 comp_swap = SWAP_ALT;
1137 number_type = NUMBER_UNORM;
1138 source_format = 1;
1139 break;
1140 case MESA_FORMAT_ARGB1555_REV:
1141 format = COLOR_1_5_5_5;
1142 comp_swap = SWAP_ALT_REV;
1143 number_type = NUMBER_UNORM;
1144 source_format = 1;
1145 break;
1146 case MESA_FORMAT_AL88:
1147 format = COLOR_8_8;
1148 comp_swap = SWAP_STD;
1149 number_type = NUMBER_UNORM;
1150 source_format = 1;
1151 break;
1152 case MESA_FORMAT_AL88_REV:
1153 format = COLOR_8_8;
1154 comp_swap = SWAP_STD_REV;
1155 number_type = NUMBER_UNORM;
1156 source_format = 1;
1157 break;
1158 case MESA_FORMAT_RGB332:
1159 format = COLOR_3_3_2;
1160 comp_swap = SWAP_STD_REV;
1161 number_type = NUMBER_UNORM;
1162 source_format = 1;
1163 break;
1164 case MESA_FORMAT_A8:
1165 format = COLOR_8;
1166 comp_swap = SWAP_ALT_REV;
1167 number_type = NUMBER_UNORM;
1168 source_format = 1;
1169 break;
1170 case MESA_FORMAT_I8:
1171 case MESA_FORMAT_CI8:
1172 format = COLOR_8;
1173 comp_swap = SWAP_STD;
1174 number_type = NUMBER_UNORM;
1175 source_format = 1;
1176 break;
1177 case MESA_FORMAT_L8:
1178 format = COLOR_8;
1179 comp_swap = SWAP_ALT;
1180 number_type = NUMBER_UNORM;
1181 source_format = 1;
1182 break;
1183 case MESA_FORMAT_RGBA_FLOAT32:
1184 format = COLOR_32_32_32_32_FLOAT;
1185 comp_swap = SWAP_STD_REV;
1186 number_type = NUMBER_FLOAT;
1187 source_format = 0;
1188 break;
1189 case MESA_FORMAT_RGBA_FLOAT16:
1190 format = COLOR_16_16_16_16_FLOAT;
1191 comp_swap = SWAP_STD_REV;
1192 number_type = NUMBER_FLOAT;
1193 source_format = 0;
1194 break;
1195 case MESA_FORMAT_ALPHA_FLOAT32:
1196 format = COLOR_32_FLOAT;
1197 comp_swap = SWAP_ALT_REV;
1198 number_type = NUMBER_FLOAT;
1199 source_format = 0;
1200 break;
1201 case MESA_FORMAT_ALPHA_FLOAT16:
1202 format = COLOR_16_FLOAT;
1203 comp_swap = SWAP_ALT_REV;
1204 number_type = NUMBER_FLOAT;
1205 source_format = 0;
1206 break;
1207 case MESA_FORMAT_LUMINANCE_FLOAT32:
1208 format = COLOR_32_FLOAT;
1209 comp_swap = SWAP_ALT;
1210 number_type = NUMBER_FLOAT;
1211 source_format = 0;
1212 break;
1213 case MESA_FORMAT_LUMINANCE_FLOAT16:
1214 format = COLOR_16_FLOAT;
1215 comp_swap = SWAP_ALT;
1216 number_type = NUMBER_FLOAT;
1217 source_format = 0;
1218 break;
1219 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
1220 format = COLOR_32_32_FLOAT;
1221 comp_swap = SWAP_ALT_REV;
1222 number_type = NUMBER_FLOAT;
1223 source_format = 0;
1224 break;
1225 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
1226 format = COLOR_16_16_FLOAT;
1227 comp_swap = SWAP_ALT_REV;
1228 number_type = NUMBER_FLOAT;
1229 source_format = 0;
1230 break;
1231 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
1232 format = COLOR_32_FLOAT;
1233 comp_swap = SWAP_STD;
1234 number_type = NUMBER_FLOAT;
1235 source_format = 0;
1236 break;
1237 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
1238 format = COLOR_16_FLOAT;
1239 comp_swap = SWAP_STD;
1240 number_type = NUMBER_UNORM;
1241 source_format = 0;
1242 break;
1243 case MESA_FORMAT_X8_Z24:
1244 case MESA_FORMAT_S8_Z24:
1245 format = COLOR_8_24;
1246 comp_swap = SWAP_STD;
1247 number_type = NUMBER_UNORM;
1248 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1249 ARRAY_1D_TILED_THIN1,
1250 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1251 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1252 source_format = 0;
1253 break;
1254 case MESA_FORMAT_Z24_S8:
1255 format = COLOR_24_8;
1256 comp_swap = SWAP_STD;
1257 number_type = NUMBER_UNORM;
1258 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1259 ARRAY_1D_TILED_THIN1,
1260 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1261 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1262 source_format = 0;
1263 break;
1264 case MESA_FORMAT_Z16:
1265 format = COLOR_16;
1266 comp_swap = SWAP_STD;
1267 number_type = NUMBER_UNORM;
1268 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1269 ARRAY_1D_TILED_THIN1,
1270 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1271 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1272 source_format = 0;
1273 break;
1274 case MESA_FORMAT_Z32:
1275 format = COLOR_32;
1276 comp_swap = SWAP_STD;
1277 number_type = NUMBER_UNORM;
1278 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1279 ARRAY_1D_TILED_THIN1,
1280 EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
1281 EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
1282 source_format = 0;
1283 break;
1284 case MESA_FORMAT_SARGB8:
1285 format = COLOR_8_8_8_8;
1286 comp_swap = SWAP_ALT;
1287 number_type = NUMBER_SRGB;
1288 source_format = 1;
1289 break;
1290 case MESA_FORMAT_SLA8:
1291 format = COLOR_8_8;
1292 comp_swap = SWAP_ALT_REV;
1293 number_type = NUMBER_SRGB;
1294 source_format = 1;
1295 break;
1296 case MESA_FORMAT_SL8:
1297 format = COLOR_8;
1298 comp_swap = SWAP_ALT_REV;
1299 number_type = NUMBER_SRGB;
1300 source_format = 1;
1301 break;
1302 default:
1303 _mesa_problem(context->radeon.glCtx, "unexpected format in evergreenSetRenderTarget()");
1304 break;
1305 }
1306
1307 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1308 format,
1309 EG_CB_COLOR0_INFO__FORMAT_shift,
1310 EG_CB_COLOR0_INFO__FORMAT_mask);
1311 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1312 comp_swap,
1313 EG_CB_COLOR0_INFO__COMP_SWAP_shift,
1314 EG_CB_COLOR0_INFO__COMP_SWAP_mask);
1315 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1316 number_type,
1317 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
1318 EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
1319 SETfield(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1320 source_format,
1321 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
1322 EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
1323 SETbit(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1324 EG_CB_COLOR0_INFO__BLEND_CLAMP_bit);
1325
1326 evergreen->render_target[id].CB_COLOR0_VIEW.u32All = 0;
1327 evergreen->render_target[id].CB_COLOR0_CMASK.u32All = 0;
1328 evergreen->render_target[id].CB_COLOR0_FMASK.u32All = 0;
1329 evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All = 0;
1330
1331 evergreen->render_target[id].enabled = GL_TRUE;
1332 }
1333
1334 static void evergreenSendCB(GLcontext *ctx, struct radeon_state_atom *atom)
1335 {
1336 context_t *context = EVERGREEN_CONTEXT(ctx);
1337 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1338 struct radeon_renderbuffer *rrb;
1339 BATCH_LOCALS(&context->radeon);
1340 int id = 0;
1341 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1342
1343 rrb = radeon_get_colorbuffer(&context->radeon);
1344 if (!rrb || !rrb->bo) {
1345 return;
1346 }
1347
1348 evergreenSetRenderTarget(context, 0);
1349
1350 if (!evergreen->render_target[id].enabled)
1351 return;
1352
1353 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1354 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
1355 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_BASE.u32All);
1356 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1357 rrb->bo,
1358 evergreen->render_target[id].CB_COLOR0_BASE.u32All,
1359 0, RADEON_GEM_DOMAIN_VRAM, 0);
1360 END_BATCH();
1361
1362 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
1363 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, evergreen->render_target[id].CB_COLOR0_INFO.u32All);
1364 R600_OUT_BATCH_RELOC(evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1365 rrb->bo,
1366 evergreen->render_target[id].CB_COLOR0_INFO.u32All,
1367 0, RADEON_GEM_DOMAIN_VRAM, 0);
1368 END_BATCH();
1369
1370 BEGIN_BATCH_NO_AUTOSTATE(5);
1371 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
1372 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_PITCH.u32All);
1373 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_SLICE.u32All);
1374 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_VIEW.u32All);
1375 END_BATCH();
1376
1377 BEGIN_BATCH_NO_AUTOSTATE(4);
1378 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2);
1379 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_ATTRIB.u32All);
1380 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_DIM.u32All);
1381 /*
1382 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
1383 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
1384 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
1385 R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
1386 */
1387 END_BATCH();
1388
1389 BEGIN_BATCH_NO_AUTOSTATE(4);
1390 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_TARGET_MASK, 2);
1391 R600_OUT_BATCH(evergreen->CB_TARGET_MASK.u32All);
1392 R600_OUT_BATCH(evergreen->CB_SHADER_MASK.u32All);
1393 END_BATCH();
1394
1395 BEGIN_BATCH_NO_AUTOSTATE(5);
1396 EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_BLEND_RED, 3);
1397 R600_OUT_BATCH(evergreen->CB_BLEND_RED.u32All);
1398 R600_OUT_BATCH(evergreen->CB_BLEND_GREEN.u32All);
1399 R600_OUT_BATCH(evergreen->CB_BLEND_BLUE.u32All);
1400 END_BATCH();
1401
1402 BEGIN_BATCH_NO_AUTOSTATE(9);
1403 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND_ALPHA, evergreen->CB_BLEND_ALPHA.u32All);
1404 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, evergreen->CB_BLEND0_CONTROL.u32All);
1405 EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR_CONTROL, evergreen->CB_COLOR_CONTROL.u32All);
1406 END_BATCH();
1407
1408 COMMIT_BATCH();
1409 }
1410 static void evergreenSendCP(GLcontext *ctx, struct radeon_state_atom *atom)
1411 {
1412 context_t *context = EVERGREEN_CONTEXT(ctx);
1413 BATCH_LOCALS(&context->radeon);
1414 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1415
1416 //first to send
1417 //r700Start3D
1418 BEGIN_BATCH_NO_AUTOSTATE(3);
1419 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1)); //IT_CONTEXT_CONTROL 0x28
1420 R600_OUT_BATCH(0x80000000);
1421 R600_OUT_BATCH(0x80000000);
1422 END_BATCH();
1423
1424 COMMIT_BATCH();
1425 }
1426 static void evergreenSendVGT(GLcontext *ctx, struct radeon_state_atom *atom)
1427 {
1428 context_t *context = EVERGREEN_CONTEXT(ctx);
1429 EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
1430 BATCH_LOCALS(&context->radeon);
1431 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1432
1433 /* moved to draw:
1434 VGT_DRAW_INITIATOR
1435 VGT_INDEX_TYPE
1436 VGT_PRIMITIVE_TYPE
1437 */
1438 BEGIN_BATCH_NO_AUTOSTATE(5);
1439 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 3);
1440 R600_OUT_BATCH(evergreen->VGT_MAX_VTX_INDX.u32All);
1441 R600_OUT_BATCH(evergreen->VGT_MIN_VTX_INDX.u32All);
1442 R600_OUT_BATCH(evergreen->VGT_INDX_OFFSET.u32All);
1443 END_BATCH();
1444
1445 BEGIN_BATCH_NO_AUTOSTATE(6);
1446 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_OUTPUT_PATH_CNTL, evergreen->VGT_OUTPUT_PATH_CNTL.u32All);
1447
1448 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_GS_MODE, evergreen->VGT_GS_MODE.u32All);
1449 END_BATCH();
1450
1451 BEGIN_BATCH_NO_AUTOSTATE(3);
1452 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVEID_EN, 1);
1453 R600_OUT_BATCH(evergreen->VGT_PRIMITIVEID_EN.u32All);
1454 END_BATCH();
1455
1456 BEGIN_BATCH_NO_AUTOSTATE(4);
1457 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1458 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_0.u32All);
1459 R600_OUT_BATCH(evergreen->VGT_INSTANCE_STEP_RATE_1.u32All);
1460 END_BATCH();
1461
1462 BEGIN_BATCH_NO_AUTOSTATE(4);
1463 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1464 R600_OUT_BATCH(evergreen->VGT_REUSE_OFF.u32All);
1465 R600_OUT_BATCH(evergreen->VGT_VTX_CNT_EN.u32All);
1466 END_BATCH();
1467
1468 BEGIN_BATCH_NO_AUTOSTATE(3);
1469 EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, evergreen->VGT_SHADER_STAGES_EN.u32All);
1470 END_BATCH();
1471
1472 BEGIN_BATCH_NO_AUTOSTATE(4);
1473 EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1474 R600_OUT_BATCH(evergreen->VGT_STRMOUT_CONFIG.u32All);
1475 R600_OUT_BATCH(evergreen->VGT_STRMOUT_BUFFER_CONFIG.u32All);
1476 END_BATCH();
1477
1478 COMMIT_BATCH();
1479 }
1480
1481 static void evergreenSendTIMESTAMP(GLcontext *ctx, struct radeon_state_atom *atom)
1482 {
1483 context_t *context = EVERGREEN_CONTEXT(ctx);
1484 BATCH_LOCALS(&context->radeon);
1485 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1486 }
1487
1488 void evergreenInitAtoms(context_t *context)
1489 {
1490 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1491 context->radeon.hw.max_state_size = 10 + 5 + 14 + 3; /* start 3d, idle, cb/db flush, 3 for time stamp */
1492
1493 /* Setup the atom linked list */
1494 make_empty_list(&context->radeon.hw.atomlist);
1495 context->radeon.hw.atomlist.name = "atom-list";
1496
1497 EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
1498
1499 //make sure send first
1500 EVERGREEN_ALLOC_STATE(cp, always, 3, evergreenSendCP);
1501
1502 EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (6 + (VERT_ATTRIB_MAX * 12)), evergreenSendVTX);
1503 EVERGREEN_ALLOC_STATE(pa, always, 124, evergreenSendPA);
1504 EVERGREEN_ALLOC_STATE(tp, always, 0, evergreenSendTP);
1505 EVERGREEN_ALLOC_STATE(sq, always, 86, evergreenSendSQ); /* 85 */
1506 EVERGREEN_ALLOC_STATE(vs, always, 16, evergreenSendVSresource);
1507 EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI);
1508 EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX);
1509 EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */
1510 EVERGREEN_ALLOC_STATE(db, always, 65, evergreenSendDB);
1511 EVERGREEN_ALLOC_STATE(cb, always, 35, evergreenSendCB);
1512 EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT);
1513 EVERGREEN_ALLOC_STATE(timestamp, always, 3, evergreenSendTIMESTAMP);
1514
1515 //evergreen_init_query_stateobj(&context->radeon, 6 * 2);
1516
1517 context->radeon.hw.is_dirty = GL_TRUE;
1518 context->radeon.hw.all_dirty = GL_TRUE;
1519 }