2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/state.h"
29 #include "main/imports.h"
30 #include "main/enums.h"
31 #include "main/macros.h"
32 #include "main/context.h"
34 #include "main/simple_list.h"
35 #include "main/api_arrayelt.h"
36 #include "swrast/swrast.h"
37 #include "swrast_setup/swrast_setup.h"
41 #include "tnl/t_vp_build.h"
42 #include "tnl/t_context.h"
43 #include "tnl/t_vertex.h"
44 #include "vbo/vbo_context.h"
46 #include "r600_context.h"
47 #include "r600_cmdbuf.h"
49 #include "evergreen_fragprog.h"
50 #include "evergreen_vertprog.h"
52 #include "evergreen_state.h"
53 #include "evergreen_tex.h"
55 #include "radeon_buffer_objects.h"
56 #include "radeon_common_context.h"
58 static unsigned int evergreenPrimitiveType(int prim
) //same
60 switch (prim
& PRIM_MODE_MASK
)
63 return DI_PT_POINTLIST
;
66 return DI_PT_LINELIST
;
69 return DI_PT_LINESTRIP
;
72 return DI_PT_LINELOOP
;
77 case GL_TRIANGLE_STRIP
:
78 return DI_PT_TRISTRIP
;
84 return DI_PT_QUADLIST
;
87 return DI_PT_QUADSTRIP
;
99 static int evergreenNumVerts(int num_verts
, int prim
) //same
103 switch (prim
& PRIM_MODE_MASK
) {
108 verts_off
= num_verts
% 2;
112 verts_off
= num_verts
;
116 verts_off
= num_verts
;
119 verts_off
= num_verts
% 3;
121 case GL_TRIANGLE_STRIP
:
123 verts_off
= num_verts
;
125 case GL_TRIANGLE_FAN
:
127 verts_off
= num_verts
;
130 verts_off
= num_verts
% 4;
134 verts_off
= num_verts
;
136 verts_off
= num_verts
% 2;
140 verts_off
= num_verts
;
148 return num_verts
- verts_off
;
151 static void evergreenRunRenderPrimitive(struct gl_context
* ctx
, int start
, int end
, int prim
,
152 GLint basevertex
) //same
154 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
155 BATCH_LOCALS(&context
->radeon
);
156 int type
, total_emit
;
158 uint32_t vgt_draw_initiator
= 0;
159 uint32_t vgt_index_type
= 0;
160 uint32_t vgt_primitive_type
= 0;
161 uint32_t vgt_num_indices
= 0;
163 type
= evergreenPrimitiveType(prim
);
164 num_indices
= evergreenNumVerts(end
- start
, prim
);
166 radeon_print(RADEON_RENDER
, RADEON_TRACE
,
167 "%s type %x num_indices %d\n",
168 __func__
, type
, num_indices
);
170 if (type
< 0 || num_indices
<= 0)
173 SETfield(vgt_primitive_type
, type
,
174 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
176 SETfield(vgt_index_type
, DI_INDEX_SIZE_32_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
178 if(GL_TRUE
!= context
->ind_buf
.is_32bit
)
180 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
183 /* 16-bit indexes are packed in a 32-bit value */
184 SETfield(vgt_index_type
,
190 SWAP_MODE_shift
, SWAP_MODE_mask
);
192 vgt_num_indices
= num_indices
;
193 SETfield(vgt_draw_initiator
, DI_SRC_SEL_DMA
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
194 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
, MAJOR_MODE_mask
);
196 total_emit
= 3 /* VGT_PRIMITIVE_TYPE */
197 + 2 /* VGT_INDEX_TYPE */
198 + 2 /* NUM_INSTANCES */
199 + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
200 + 5 + 2; /* DRAW_INDEX */
202 BEGIN_BATCH_NO_AUTOSTATE(total_emit
);
204 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE
, 1);
205 R600_OUT_BATCH(vgt_primitive_type
);
207 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
208 R600_OUT_BATCH(vgt_index_type
);
210 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
213 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 2));
214 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
215 R600_OUT_BATCH(basevertex
); //VTX_BASE_VTX_LOC
216 R600_OUT_BATCH(0); //VTX_START_INST_LOC
218 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX
, 3));
219 R600_OUT_BATCH(context
->ind_buf
.bo_offset
);
221 R600_OUT_BATCH(vgt_num_indices
);
222 R600_OUT_BATCH(vgt_draw_initiator
);
223 R600_OUT_BATCH_RELOC(context
->ind_buf
.bo_offset
,
225 context
->ind_buf
.bo_offset
,
226 RADEON_GEM_DOMAIN_GTT
, 0, 0);
231 static void evergreenRunRenderPrimitiveImmediate(struct gl_context
* ctx
, int start
, int end
, int prim
) //same
233 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
234 BATCH_LOCALS(&context
->radeon
);
236 uint32_t num_indices
, total_emit
= 0;
237 uint32_t vgt_draw_initiator
= 0;
238 uint32_t vgt_index_type
= 0;
239 uint32_t vgt_primitive_type
= 0;
240 uint32_t vgt_num_indices
= 0;
242 type
= evergreenPrimitiveType(prim
);
243 num_indices
= evergreenNumVerts(end
- start
, prim
);
245 radeon_print(RADEON_RENDER
, RADEON_TRACE
,
246 "%s type %x num_indices %d\n",
247 __func__
, type
, num_indices
);
249 if (type
< 0 || num_indices
<= 0)
252 SETfield(vgt_primitive_type
, type
,
253 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
255 if (num_indices
> 0xffff)
257 SETfield(vgt_index_type
, DI_INDEX_SIZE_32_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
261 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
264 /* 16-bit indexes are packed in a 32-bit value */
265 SETfield(vgt_index_type
,
271 SWAP_MODE_shift
, SWAP_MODE_mask
);
273 vgt_num_indices
= num_indices
;
274 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
, MAJOR_MODE_mask
);
278 SETfield(vgt_draw_initiator
, DI_SRC_SEL_AUTO_INDEX
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
282 if (num_indices
> 0xffff)
284 total_emit
+= num_indices
;
288 total_emit
+= (num_indices
+ 1) / 2;
290 SETfield(vgt_draw_initiator
, DI_SRC_SEL_IMMEDIATE
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
293 total_emit
+= 3 /* VGT_PRIMITIVE_TYPE */
294 + 2 /* VGT_INDEX_TYPE */
295 + 2 /* NUM_INSTANCES */
296 + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
299 BEGIN_BATCH_NO_AUTOSTATE(total_emit
);
301 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE
, 1);
302 R600_OUT_BATCH(vgt_primitive_type
);
304 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
305 R600_OUT_BATCH(vgt_index_type
);
307 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
310 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 2));
311 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
312 R600_OUT_BATCH(0); //VTX_BASE_VTX_LOC
313 R600_OUT_BATCH(0); //VTX_START_INST_LOC
317 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO
, 1));
318 R600_OUT_BATCH(vgt_num_indices
);
319 R600_OUT_BATCH(vgt_draw_initiator
);
323 if (num_indices
> 0xffff)
325 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD
, (num_indices
+ 1)));
326 R600_OUT_BATCH(vgt_num_indices
);
327 R600_OUT_BATCH(vgt_draw_initiator
);
328 for (i
= start
; i
< (start
+ num_indices
); i
++)
335 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD
, (((num_indices
+ 1) / 2) + 1)));
336 R600_OUT_BATCH(vgt_num_indices
);
337 R600_OUT_BATCH(vgt_draw_initiator
);
338 for (i
= start
; i
< (start
+ num_indices
); i
+= 2)
340 if ((i
+ 1) == (start
+ num_indices
))
346 R600_OUT_BATCH(((i
+ 1) << 16) | (i
));
356 #define CONVERT( TYPE, MACRO ) do { \
359 if (input->Normalized) { \
360 for (i = 0; i < count; i++) { \
361 const TYPE *in = (TYPE *)src_ptr; \
362 for (j = 0; j < sz; j++) { \
363 *dst_ptr++ = MACRO(*in); \
369 for (i = 0; i < count; i++) { \
370 const TYPE *in = (TYPE *)src_ptr; \
371 for (j = 0; j < sz; j++) { \
372 *dst_ptr++ = (GLfloat)(*in); \
381 * Convert attribute data type to float
382 * If the attribute uses named buffer object replace the bo with newly allocated bo
384 static void evergreenConvertAttrib(struct gl_context
*ctx
, int count
,
385 const struct gl_client_array
*input
,
386 struct StreamDesc
*attr
)
388 context_t
*context
= R700_CONTEXT(ctx
);
389 const GLvoid
*src_ptr
;
390 GLboolean mapped_named_bo
= GL_FALSE
;
394 stride
= (input
->StrideB
== 0) ? evergreen_getTypeSize(input
->Type
) * input
->Size
: input
->StrideB
;
396 /* Convert value for first element only */
397 if (input
->StrideB
== 0)
402 if (input
->BufferObj
->Name
)
404 if (!input
->BufferObj
->Pointer
)
406 ctx
->Driver
.MapBufferRange(ctx
, 0, input
->BufferObj
->Size
,
407 GL_MAP_READ_BIT
, input
->BufferObj
);
408 mapped_named_bo
= GL_TRUE
;
411 src_ptr
= ADD_POINTERS(input
->BufferObj
->Pointer
, input
->Ptr
);
415 src_ptr
= input
->Ptr
;
418 radeonAllocDmaRegion(&context
->radeon
, &attr
->bo
, &attr
->bo_offset
,
419 sizeof(GLfloat
) * input
->Size
* count
, 32);
421 radeon_bo_map(attr
->bo
, 1);
423 dst_ptr
= (GLfloat
*)ADD_POINTERS(attr
->bo
->ptr
, attr
->bo_offset
);
425 assert(src_ptr
!= NULL
);
430 CONVERT(GLdouble
, (GLfloat
));
432 case GL_UNSIGNED_INT
:
433 CONVERT(GLuint
, UINT_TO_FLOAT
);
436 CONVERT(GLint
, INT_TO_FLOAT
);
438 case GL_UNSIGNED_SHORT
:
439 CONVERT(GLushort
, USHORT_TO_FLOAT
);
442 CONVERT(GLshort
, SHORT_TO_FLOAT
);
444 case GL_UNSIGNED_BYTE
:
445 assert(input
->Format
!= GL_BGRA
);
446 CONVERT(GLubyte
, UBYTE_TO_FLOAT
);
449 CONVERT(GLbyte
, BYTE_TO_FLOAT
);
456 radeon_bo_unmap(attr
->bo
);
460 ctx
->Driver
.UnmapBuffer(ctx
, input
->BufferObj
);
464 static void evergreenFixupIndexBuffer(struct gl_context
*ctx
, const struct _mesa_index_buffer
*mesa_ind_buf
)
466 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
470 GLboolean mapped_named_bo
= GL_FALSE
;
472 if (mesa_ind_buf
->obj
->Name
&& !mesa_ind_buf
->obj
->Pointer
)
474 ctx
->Driver
.MapBufferRange(ctx
, 0, mesa_ind_buf
->obj
->Size
,
475 GL_MAP_READ_BIT
, mesa_ind_buf
->obj
);
476 mapped_named_bo
= GL_TRUE
;
477 assert(mesa_ind_buf
->obj
->Pointer
!= NULL
);
479 src_ptr
= ADD_POINTERS(mesa_ind_buf
->obj
->Pointer
, mesa_ind_buf
->ptr
);
481 if (mesa_ind_buf
->type
== GL_UNSIGNED_BYTE
)
483 GLuint size
= sizeof(GLushort
) * ((mesa_ind_buf
->count
+ 1) & ~1);
484 GLubyte
*in
= (GLubyte
*)src_ptr
;
486 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
487 &context
->ind_buf
.bo_offset
, size
, 4);
489 radeon_bo_map(context
->ind_buf
.bo
, 1);
490 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
491 out
= (GLuint
*)ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
493 for (i
= 0; i
+ 1 < mesa_ind_buf
->count
; i
+= 2)
495 *out
++ = in
[i
] | in
[i
+ 1] << 16;
498 if (i
< mesa_ind_buf
->count
)
503 radeon_bo_unmap(context
->ind_buf
.bo
);
507 { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
508 GLushort
*in
= (GLushort
*)src_ptr
;
509 GLuint size
= sizeof(GLushort
) * ((mesa_ind_buf
->count
+ 1) & ~1);
511 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
512 &context
->ind_buf
.bo_offset
, size
, 4);
514 radeon_bo_map(context
->ind_buf
.bo
, 1);
515 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
516 out
= (GLuint
*)ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
518 for (i
= 0; i
+ 1 < mesa_ind_buf
->count
; i
+= 2)
520 *out
++ = in
[i
] | in
[i
+ 1] << 16;
523 if (i
< mesa_ind_buf
->count
)
527 radeon_bo_unmap(context
->ind_buf
.bo
);
531 context
->ind_buf
.is_32bit
= GL_FALSE
;
532 context
->ind_buf
.count
= mesa_ind_buf
->count
;
536 ctx
->Driver
.UnmapBuffer(ctx
, mesa_ind_buf
->obj
);
540 static GLboolean
evergreen_check_fallbacks(struct gl_context
*ctx
) //same
542 if (ctx
->RenderMode
!= GL_RENDER
)
548 /* start 3d, idle, cb/db flush */
549 #define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
551 static GLuint
evergreenPredictRenderSize(struct gl_context
* ctx
,
552 const struct _mesa_prim
*prim
,
553 const struct _mesa_index_buffer
*ib
,
556 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
561 dwords
= PRE_EMIT_STATE_BUFSZ
;
563 dwords
+= nr_prims
* 18;
565 for (i
= 0; i
< nr_prims
; ++i
)
567 if (prim
[i
].start
== 0)
569 else if (prim
[i
].count
> 0xffff)
570 dwords
+= prim
[i
].count
+ 14;
572 dwords
+= ((prim
[i
].count
+ 1) / 2) + 14;
576 state_size
= radeonCountStateEmitSize(&context
->radeon
);
577 flushed
= rcommonEnsureCmdBufSpace(&context
->radeon
,
581 dwords
+= radeonCountStateEmitSize(&context
->radeon
);
583 dwords
+= state_size
;
585 radeon_print(RADEON_RENDER
, RADEON_VERBOSE
, "%s: total prediction size is %d.\n", __FUNCTION__
, dwords
);
590 static void evergreenSetupIndexBuffer(struct gl_context
*ctx
, const struct _mesa_index_buffer
*mesa_ind_buf
)
592 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
595 context
->ind_buf
.bo
= NULL
;
600 if (mesa_ind_buf
->type
== GL_UNSIGNED_INT
)
602 if (mesa_ind_buf
->type
!= GL_UNSIGNED_BYTE
)
605 const GLvoid
*src_ptr
;
607 GLboolean mapped_named_bo
= GL_FALSE
;
609 if (mesa_ind_buf
->obj
->Name
&& !mesa_ind_buf
->obj
->Pointer
)
611 ctx
->Driver
.MapBufferRange(ctx
, 0, mesa_ind_buf
->obj
->Size
,
612 GL_MAP_READ_BIT
, mesa_ind_buf
->obj
);
613 assert(mesa_ind_buf
->obj
->Pointer
!= NULL
);
614 mapped_named_bo
= GL_TRUE
;
617 src_ptr
= ADD_POINTERS(mesa_ind_buf
->obj
->Pointer
, mesa_ind_buf
->ptr
);
619 const GLuint size
= mesa_ind_buf
->count
* getTypeSize(mesa_ind_buf
->type
);
621 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
622 &context
->ind_buf
.bo_offset
, size
, 4);
623 radeon_bo_map(context
->ind_buf
.bo
, 1);
624 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
625 dst_ptr
= ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
627 memcpy(dst_ptr
, src_ptr
, size
);
629 radeon_bo_unmap(context
->ind_buf
.bo
);
630 context
->ind_buf
.is_32bit
= (mesa_ind_buf
->type
== GL_UNSIGNED_INT
);
631 context
->ind_buf
.count
= mesa_ind_buf
->count
;
635 ctx
->Driver
.UnmapBuffer(ctx
, mesa_ind_buf
->obj
);
640 evergreenFixupIndexBuffer(ctx
, mesa_ind_buf
);
645 static void evergreenAlignDataToDword(struct gl_context
*ctx
,
646 const struct gl_client_array
*input
,
648 struct StreamDesc
*attr
)
650 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
651 const int dst_stride
= (input
->StrideB
+ 3) & ~3;
652 const int size
= getTypeSize(input
->Type
) * input
->Size
* count
;
653 GLboolean mapped_named_bo
= GL_FALSE
;
655 radeonAllocDmaRegion(&context
->radeon
, &attr
->bo
, &attr
->bo_offset
, size
, 32);
657 radeon_bo_map(attr
->bo
, 1);
659 if (!input
->BufferObj
->Pointer
)
661 ctx
->Driver
.MapBufferRange(ctx
, 0, input
->BufferObj
->Size
,
662 GL_MAP_READ_BIT
, input
->BufferObj
->obj
);
663 mapped_named_bo
= GL_TRUE
;
667 GLvoid
*src_ptr
= ADD_POINTERS(input
->BufferObj
->Pointer
, input
->Ptr
);
668 GLvoid
*dst_ptr
= ADD_POINTERS(attr
->bo
->ptr
, attr
->bo_offset
);
671 for (i
= 0; i
< count
; ++i
)
673 memcpy(dst_ptr
, src_ptr
, input
->StrideB
);
674 src_ptr
+= input
->StrideB
;
675 dst_ptr
+= dst_stride
;
679 radeon_bo_unmap(attr
->bo
);
682 ctx
->Driver
.UnmapBuffer(ctx
, input
->BufferObj
);
685 attr
->stride
= dst_stride
;
689 static void evergreenSetupStreams(struct gl_context
*ctx
, const struct gl_client_array
*input
[], int count
)
691 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
696 EVERGREEN_STATECHANGE(context
, vtx
);
698 for(index
= 0; index
< context
->nNumActiveAos
; index
++)
700 struct radeon_aos
*aos
= &context
->radeon
.tcl
.aos
[index
];
701 i
= context
->stream_desc
[index
].element
;
703 stride
= (input
[i
]->StrideB
== 0) ? getTypeSize(input
[i
]->Type
) * input
[i
]->Size
: input
[i
]->StrideB
;
705 if (input
[i
]->Type
== GL_DOUBLE
|| input
[i
]->Type
== GL_UNSIGNED_INT
|| input
[i
]->Type
== GL_INT
707 || getTypeSize(input
[i
]->Type
) != 4
711 evergreenConvertAttrib(ctx
, count
, input
[i
], &context
->stream_desc
[index
]);
715 if (input
[i
]->BufferObj
->Name
)
717 context
->stream_desc
[index
].stride
= input
[i
]->StrideB
;
718 context
->stream_desc
[index
].bo_offset
= (intptr_t) input
[i
]->Ptr
;
719 context
->stream_desc
[index
].bo
= get_radeon_buffer_object(input
[i
]->BufferObj
)->bo
;
720 context
->stream_desc
[index
].is_named_bo
= GL_TRUE
;
725 int local_count
= count
;
728 if (input
[i
]->StrideB
== 0)
730 size
= getTypeSize(input
[i
]->Type
) * input
[i
]->Size
;
735 size
= getTypeSize(input
[i
]->Type
) * input
[i
]->Size
* local_count
;
738 radeonAllocDmaRegion(&context
->radeon
, &context
->stream_desc
[index
].bo
,
739 &context
->stream_desc
[index
].bo_offset
, size
, 32);
741 radeon_bo_map(context
->stream_desc
[index
].bo
, 1);
742 assert(context
->stream_desc
[index
].bo
->ptr
!= NULL
);
745 dst
= (uint32_t *)ADD_POINTERS(context
->stream_desc
[index
].bo
->ptr
,
746 context
->stream_desc
[index
].bo_offset
);
748 switch (context
->stream_desc
[index
].dwords
)
751 radeonEmitVec4(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
754 radeonEmitVec8(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
757 radeonEmitVec12(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
760 radeonEmitVec16(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
767 radeon_bo_unmap(context
->stream_desc
[index
].bo
);
771 aos
->count
= context
->stream_desc
[index
].stride
== 0 ? 1 : count
;
772 aos
->stride
= context
->stream_desc
[index
].stride
/ sizeof(float);
773 aos
->components
= context
->stream_desc
[index
].dwords
;
774 aos
->bo
= context
->stream_desc
[index
].bo
;
775 aos
->offset
= context
->stream_desc
[index
].bo_offset
;
777 if(context
->stream_desc
[index
].is_named_bo
)
779 radeon_cs_space_add_persistent_bo(context
->radeon
.cmdbuf
.cs
,
780 context
->stream_desc
[index
].bo
,
781 RADEON_GEM_DOMAIN_GTT
, 0);
785 ret
= radeon_cs_space_check_with_bo(context
->radeon
.cmdbuf
.cs
,
786 first_elem(&context
->radeon
.dma
.reserved
)->bo
,
787 RADEON_GEM_DOMAIN_GTT
, 0);
790 static void evergreenFreeData(struct gl_context
*ctx
)
792 /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
793 * to prevent double unref in radeonReleaseArrays
794 * called during context destroy
796 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
800 for (i
= 0; i
< context
->nNumActiveAos
; i
++)
802 if (!context
->stream_desc
[i
].is_named_bo
)
804 radeon_bo_unref(context
->stream_desc
[i
].bo
);
806 context
->radeon
.tcl
.aos
[i
].bo
= NULL
;
809 if(context
->vp_Constbo
!= NULL
)
811 radeon_bo_unref(context
->vp_Constbo
);
812 context
->vp_Constbo
= NULL
;
814 if(context
->fp_Constbo
!= NULL
)
816 radeon_bo_unref(context
->fp_Constbo
);
817 context
->fp_Constbo
= NULL
;
820 if (context
->ind_buf
.bo
!= NULL
)
822 radeon_bo_unref(context
->ind_buf
.bo
);
826 static GLboolean
evergreenTryDrawPrims(struct gl_context
*ctx
,
827 const struct gl_client_array
*arrays
[],
828 const struct _mesa_prim
*prim
,
830 const struct _mesa_index_buffer
*ib
,
834 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
835 radeonContextPtr radeon
= &context
->radeon
;
837 struct radeon_renderbuffer
*rrb
;
840 _mesa_update_state( ctx
);
842 if (evergreen_check_fallbacks(ctx
))
845 _tnl_UpdateFixedFunctionProgram(ctx
);
846 evergreenSetVertexFormat(ctx
, arrays
, max_index
+ 1);
849 /* shaders need to be updated before buffers are validated */
850 evergreenUpdateShaders(ctx
);
851 if (!evergreenValidateBuffers(ctx
))
854 /* always emit CB base to prevent
855 * lock ups on some chips.
857 EVERGREEN_STATECHANGE(context
, cb
);
858 /* mark vtx as dirty since it changes per-draw */
859 EVERGREEN_STATECHANGE(context
, vtx
);
861 evergreenSetScissor(context
);
863 evergreenSetupVertexProgram(ctx
);
864 evergreenSetupFragmentProgram(ctx
);
865 evergreenUpdateShaderStates(ctx
);
867 GLuint emit_end
= evergreenPredictRenderSize(ctx
, prim
, ib
, nr_prims
)
868 + context
->radeon
.cmdbuf
.cs
->cdw
;
870 /* evergreenPredictRenderSize will call radeonReleaseDmaRegions, so update VP/FP const buf after it. */
871 evergreenSetupVPconstants(ctx
);
872 evergreenSetupFPconstants(ctx
);
874 evergreenSetupIndexBuffer(ctx
, ib
);
876 evergreenSetupStreams(ctx
, arrays
, max_index
+ 1);
878 radeonEmitState(radeon
);
880 radeon_debug_add_indent();
882 for (i
= 0; i
< nr_prims
; ++i
)
884 if (context
->ind_buf
.bo
)
885 evergreenRunRenderPrimitive(ctx
,
887 prim
[i
].start
+ prim
[i
].count
,
891 evergreenRunRenderPrimitiveImmediate(ctx
,
893 prim
[i
].start
+ prim
[i
].count
,
897 radeon_debug_remove_indent();
899 /* Flush render op cached for last several quads. */
900 /* XXX drm should handle this in fence submit */
902 //evergreeWaitForIdleClean(context);
904 rrb
= radeon_get_colorbuffer(&context
->radeon
);
906 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
907 CB_ACTION_ENA_bit
| (1 << (id
+ 6)));
909 rrb
= radeon_get_depthbuffer(&context
->radeon
);
911 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
912 DB_ACTION_ENA_bit
| DB_DEST_BASE_ENA_bit
);
914 evergreenFreeData(ctx
);
916 if (emit_end
< context
->radeon
.cmdbuf
.cs
->cdw
)
918 WARN_ONCE("Rendering was %d commands larger than predicted size."
919 " We might overflow command buffer.\n", context
->radeon
.cmdbuf
.cs
->cdw
- emit_end
);
925 static void evergreenDrawPrims(struct gl_context
*ctx
,
926 const struct gl_client_array
*arrays
[],
927 const struct _mesa_prim
*prim
,
929 const struct _mesa_index_buffer
*ib
,
930 GLboolean index_bounds_valid
,
934 GLboolean retval
= GL_FALSE
;
936 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
937 radeonContextPtr radeon
= &context
->radeon
;
938 radeon_prepare_render(radeon
);
940 /* This check should get folded into just the places that
941 * min/max index are really needed.
943 if (!vbo_all_varyings_in_vbos(arrays
)) {
944 if (!index_bounds_valid
)
945 vbo_get_minmax_index(ctx
, prim
, ib
, &min_index
, &max_index
);
946 /* do we want to rebase, minimizes the
947 * amount of data to upload? */
949 vbo_rebase_prims( ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
, evergreenDrawPrims
);
953 /* Make an attempt at drawing */
954 retval
= evergreenTryDrawPrims(ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
);
956 /* If failed run tnl pipeline - it should take care of fallbacks */
958 _swsetup_Wakeup(ctx
);
959 _tnl_draw_prims(ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
);
963 void evergreenInitDraw(struct gl_context
*ctx
)
965 struct vbo_context
*vbo
= vbo_context(ctx
);
968 vbo
->draw_prims
= evergreenDrawPrims
;