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Merge branch 'lp-offset-twoside'
[mesa.git] / src / mesa / drivers / dri / r600 / evergreen_sq.h
1 /*
2 * Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #ifndef _EVERGREEN_SQ_H_
28 #define _EVERGREEN_SQ_H_
29
30 enum{
31 //CF
32 EG_CF_WORD0__ADDR_shift = 0,
33 EG_CF_WORD0__ADDR_mask = 0xFFFFFF,
34 EG_CF_WORD0__JUMPTABLE_SEL_shift = 24,
35 EG_CF_WORD0__JUMPTABLE_SEL_mask = 0x7 << 24,
36
37 EG_CF_WORD1__POP_COUNT_shift = 0, //3 bits
38 EG_CF_WORD1__POP_COUNT_mask = 0x7,
39 EG_CF_WORD1__CF_CONST_shift = 3, //5 bits
40 EG_CF_WORD1__CF_CONST_mask = 0x1F << 3,
41 EG_CF_WORD1__COND_shift = 8, //2 bits
42 EG_CF_WORD1__COND_mask = 0x3 << 8,
43 EG_CF_WORD1__COUNT_shift = 10,//6 bits
44 EG_CF_WORD1__COUNT_mask = 0x3F << 10,
45 EG_CF_WORD1__reserved_shift = 16,//4 bits
46 EG_CF_WORD1__VPM_shift = 20,//1 bit
47 EG_CF_WORD1__VPM_bit = 1 << 20,
48 EG_CF_WORD1__EOP_shift = 21,//1 bit
49 EG_CF_WORD1__EOP_bit = 1 << 21,
50 EG_CF_WORD1__CF_INST_shift = 22,//8 bits
51 EG_CF_WORD1__CF_INST_mask = 0xFF << 22,
52 EG_CF_WORD1__WQM_shift = 30,//1 bit
53 EG_CF_WORD1__WQM_bit = 1 << 30,
54 EG_CF_WORD1__BARRIER_shift = 31,//1 bit
55 EG_CF_WORD1__BARRIER_bit = 1 << 31,
56
57 EG_CF_INST_NOP = 0,
58 EG_CF_INST_TC = 1,
59 EG_CF_INST_VC = 2,
60 EG_CF_INST_GDS = 3,
61 EG_CF_INST_LOOP_START = 4,
62 EG_CF_INST_LOOP_END = 5,
63 EG_CF_INST_LOOP_START_DX10 = 6,
64 EG_CF_INST_LOOP_START_NO_AL = 7,
65 EG_CF_INST_LOOP_CONTINUE = 8,
66 EG_CF_INST_LOOP_BREAK = 9,
67 EG_CF_INST_JUMP = 10,
68 EG_CF_INST_PUSH = 11,
69 EG_CF_INST_Reserved_12 = 12,
70 EG_CF_INST_ELSE = 13,
71 EG_CF_INST_POP = 14,
72 EG_CF_INST_Reserved_15 = 15,
73 EG_CF_INST_Reserved_16 = 16,
74 EG_CF_INST_Reserved_17 = 17,
75 EG_CF_INST_CALL = 18,
76 EG_CF_INST_CALL_FS = 19,
77 EG_CF_INST_RETURN = 20,
78 EG_CF_INST_EMIT_VERTEX = 21,
79 EG_CF_INST_EMIT_CUT_VERTEX = 22,
80 EG_CF_INST_CUT_VERTEX = 23,
81 EG_CF_INST_KILL = 24,
82 EG_CF_INST_Reserved_25 = 25,
83 EG_CF_INST_WAIT_ACK = 26,
84 EG_CF_INST_TC_ACK = 27,
85 EG_CF_INST_VC_ACK = 28,
86 EG_CF_INST_JUMPTABLE = 29,
87 EG_CF_INST_GLOBAL_WAVE_SYNC = 30,
88 EG_CF_INST_HALT = 31,
89
90 //TEX
91 EG_TEX_WORD0__TEX_INST_shift = 0, //5 bits
92 EG_TEX_WORD0__TEX_INST_mask = 0x1F,
93 EG_TEX_WORD0__INST_MOD_shift = 5, //2 bits
94 EG_TEX_WORD0__INST_MOD_mask = 0x3 << 5,
95 EG_TEX_WORD0__FWQ_shift = 7, //1 bit
96 EG_TEX_WORD0__FWQ_bit = 1 << 7,
97 EG_TEX_WORD0__RESOURCE_ID_shift = 8, //8 bits
98 EG_TEX_WORD0__RESOURCE_ID_mask = 0xFF << 8,
99 EG_TEX_WORD0__SRC_GPR_shift = 16,//7 bits
100 EG_TEX_WORD0__SRC_GPR_mask = 0x7F << 16,
101 EG_TEX_WORD0__SRC_REL_shift = 23,//1 bit
102 EG_TEX_WORD0__SRC_REL_bit = 1 << 23,
103 EG_TEX_WORD0__ALT_CONST_shift = 24,//1 bit
104 EG_TEX_WORD0__ALT_CONST_bit = 1 << 24,
105 EG_TEX_WORD0__RIM_shift = 25,//2 bits
106 EG_TEX_WORD0__RIM_mask = 0x3 << 25,
107 EG_TEX_WORD0__SIM_shift = 27,//2 bits
108 EG_TEX_WORD0__SIM_mask = 0x3 << 27,
109 EG_TEX_WORD0__Reserved_shift = 29,//3 bits
110 EG_TEX_WORD0__Reserved_mask = 0x7 << 29,
111
112 EG_TEX_INST_Reserved_0 = 0,
113 EG_TEX_INST_Reserved_1 = 1,
114 EG_TEX_INST_Reserved_2 = 2,
115 EG_TEX_INST_LD = 3,
116 EG_TEX_INST_GET_TEXTURE_RESINFO = 4,
117 EG_TEX_INST_GET_NUMBER_OF_SAMPLES= 5,
118 EG_TEX_INST_GET_COMP_TEX_LOD = 6,
119 EG_TEX_INST_GET_GRADIENTS_H = 7,
120 EG_TEX_INST_GET_GRADIENTS_V = 8,
121 EG_TEX_INST_SET_TEXTURE_OFFSETS = 9,
122 EG_TEX_INST_KEEP_GRADIENTS = 10,
123 EG_TEX_INST_SET_GRADIENTS_H = 11,
124 EG_TEX_INST_SET_GRADIENTS_V = 12,
125 EG_TEX_INST_Reserved_13 = 13,
126 EG_TEX_INST_Reserved_14 = 14,
127 EG_TEX_INST_Reserved_15 = 15,
128 EG_TEX_INST_SAMPLE = 16,
129 EG_TEX_INST_SAMPLE_L = 17,
130 EG_TEX_INST_SAMPLE_LB = 18,
131 EG_TEX_INST_SAMPLE_LZ = 19,
132 EG_TEX_INST_SAMPLE_G = 20,
133 EG_TEX_INST_GATHER4 = 21,
134 EG_TEX_INST_SAMPLE_G_LB = 22,
135 EG_TEX_INST_GATHER4_O = 23,
136 EG_TEX_INST_SAMPLE_C = 24,
137 EG_TEX_INST_SAMPLE_C_L = 25,
138 EG_TEX_INST_SAMPLE_C_LB = 26,
139 EG_TEX_INST_SAMPLE_C_LZ = 27,
140 EG_TEX_INST_SAMPLE_C_G = 28,
141 EG_TEX_INST_GATHER4_C = 29,
142 EG_TEX_INST_SAMPLE_C_G_LB = 30,
143 EG_TEX_INST_GATHER4_C_O = 31,
144
145 EG_TEX_WORD1__DST_GPR_shift = 0, //7 bits
146 EG_TEX_WORD1__DST_GPR_mask = 0x7F,
147 EG_TEX_WORD1__DST_REL_shift = 7, //1 bit
148 EG_TEX_WORD1__DST_REL_bit = 1 << 7,
149 EG_TEX_WORD1__Reserved_shift = 8, //1 bit
150 EG_TEX_WORD1__Reserved_bit = 1 << 8,
151 EG_TEX_WORD1__DST_SEL_X_shift = 9, //3 bits
152 EG_TEX_WORD1__DST_SEL_X_mask = 0x7 << 9,
153 EG_TEX_WORD1__DST_SEL_Y_shift = 12,//3 bits
154 EG_TEX_WORD1__DST_SEL_Y_mask = 0x7 << 12,
155 EG_TEX_WORD1__DST_SEL_Z_shift = 15,//3 bits
156 EG_TEX_WORD1__DST_SEL_Z_mask = 0x7 << 15,
157 EG_TEX_WORD1__DST_SEL_W_shift = 18,//3 bits
158 EG_TEX_WORD1__DST_SEL_W_mask = 0x7 << 18,
159 EG_TEX_WORD1__LOD_BIAS_shift = 21,//7 bits
160 EG_TEX_WORD1__LOD_BIAS_mask = 0x7F << 21,
161 EG_TEX_WORD1__COORD_TYPE_X_shift = 28,//1 bit
162 EG_TEX_WORD1__COORD_TYPE_X_bit = 1 << 28,
163 EG_TEX_WORD1__COORD_TYPE_Y_shift = 29,//1 bit
164 EG_TEX_WORD1__COORD_TYPE_Y_bit = 1 << 29,
165 EG_TEX_WORD1__COORD_TYPE_Z_shift = 30,//1 bit
166 EG_TEX_WORD1__COORD_TYPE_Z_bit = 1 << 30,
167 EG_TEX_WORD1__COORD_TYPE_W_shift = 31,//1 bit
168 EG_TEX_WORD1__COORD_TYPE_W_bit = 1 << 31,
169
170 EG_TEX_WORD2__OFFSET_X_shift = 0, //5 bits
171 EG_TEX_WORD2__OFFSET_X_mask = 0x1F,
172 EG_TEX_WORD2__OFFSET_Y_shift = 5, //5 bits
173 EG_TEX_WORD2__OFFSET_Y_mask = 0x1F << 5,
174 EG_TEX_WORD2__OFFSET_Z_shift = 10,//5 bits
175 EG_TEX_WORD2__OFFSET_Z_mask = 0x1F << 10,
176 EG_TEX_WORD2__SAMPLER_ID_shift = 15,//5 bits
177 EG_TEX_WORD2__SAMPLER_ID_mask = 0x1F << 15,
178 EG_TEX_WORD2__SRC_SEL_X_shift = 20,//3 bits
179 EG_TEX_WORD2__SRC_SEL_X_mask = 0x7 << 20,
180 EG_TEX_WORD2__SRC_SEL_Y_shift = 23,//3 bits
181 EG_TEX_WORD2__SRC_SEL_Y_mask = 0x7 << 23,
182 EG_TEX_WORD2__SRC_SEL_Z_shift = 26,//3 bits
183 EG_TEX_WORD2__SRC_SEL_Z_mask = 0x7 << 26,
184 EG_TEX_WORD2__SRC_SEL_W_shift = 29,//3 bits
185 EG_TEX_WORD2__SRC_SEL_W_mask = 0x7 << 29,
186
187 //VTX
188 EG_VTX_WORD0__VC_INST_shift = 0, //5 bits
189 EG_VTX_WORD0__VC_INST_mask = 0x1F,
190 EG_VTX_WORD0__FETCH_TYPE_shift = 5, //2 bits
191 EG_VTX_WORD0__FETCH_TYPE_mask = 0x3 << 5,
192 EG_VTX_WORD0__FWQ_shift = 7, //1 bit
193 EG_VTX_WORD0__FWQ_bit = 1 << 7,
194 EG_VTX_WORD0__BUFFER_ID_shift = 8, //8 bits
195 EG_VTX_WORD0__BUFFER_ID_mask = 0xFF << 8,
196 EG_VTX_WORD0__SRC_GPR_shift = 16,//7 bits
197 EG_VTX_WORD0__SRC_GPR_mask = 0x7F << 16,
198 EG_VTX_WORD0__SRC_REL_shift = 23,//1 bit
199 EG_VTX_WORD0__SRC_REL_bit = 1 << 23,
200 EG_VTX_WORD0__SRC_SEL_X_shift = 24,//2 bits
201 EG_VTX_WORD0__SRC_SEL_X_mask = 0x3 << 24,
202 EG_VTX_WORD0__MFC_shift = 26,//6 bits
203 EG_VTX_WORD0__MFC_mask = 0x3F << 26,
204
205 EG_VC_INST_FETCH = 0,
206 EG_VC_INST_SEMANTIC = 1,
207 EG_VC_INST_Reserved_2 = 2,
208 EG_VC_INST_Reserved_3 = 3,
209 EG_VC_INST_Reserved_4 = 4,
210 EG_VC_INST_Reserved_5 = 5,
211 EG_VC_INST_Reserved_6 = 6,
212 EG_VC_INST_Reserved_7 = 7,
213 EG_VC_INST_Reserved_8 = 8,
214 EG_VC_INST_Reserved_9 = 9,
215 EG_VC_INST_Reserved_10 = 10,
216 EG_VC_INST_Reserved_11 = 11,
217 EG_VC_INST_Reserved_12 = 12,
218 EG_VC_INST_Reserved_13 = 13,
219 EG_VC_INST_GET_BUFFER_RESINFO = 14,
220
221 EG_VTX_FETCH_VERTEX_DATA = 0,
222 EG_VTX_FETCH_INSTANCE_DATA = 1,
223 EG_VTX_FETCH_NO_INDEX_OFFSET = 2,
224
225 EG_VTX_WORD1_SEM__SEMANTIC_ID_shift = 0, //8 bits
226 EG_VTX_WORD1_SEM__SEMANTIC_ID_mask = 0xFF,
227 EG_VTX_WORD1_GPR__DST_GPR_shift = 0, //7 bits
228 EG_VTX_WORD1_GPR__DST_GPR_mask = 0x7F,
229 EG_VTX_WORD1_GPR__DST_REL_shift = 7, //1 bit
230 EG_VTX_WORD1_GPR__DST_REL_bit = 1 << 7,
231 EG_VTX_WORD1__Reserved_shift = 8, //1 bit
232 EG_VTX_WORD1__Reserved_bit = 1 << 8,
233 EG_VTX_WORD1__DST_SEL_X_shift = 9, //3 bits
234 EG_VTX_WORD1__DST_SEL_X_mask = 0x7 << 9,
235 EG_VTX_WORD1__DST_SEL_Y_shift = 12,//3 bits
236 EG_VTX_WORD1__DST_SEL_Y_mask = 0x7 << 12,
237 EG_VTX_WORD1__DST_SEL_Z_shift = 15,//3 bits
238 EG_VTX_WORD1__DST_SEL_Z_mask = 0x7 << 15,
239 EG_VTX_WORD1__DST_SEL_W_shift = 18,//3 bits
240 EG_VTX_WORD1__DST_SEL_W_mask = 0x7 << 18,
241 EG_VTX_WORD1__UCF_shift = 21,//1 bit
242 EG_VTX_WORD1__UCF_bit = 1 << 21,
243 EG_VTX_WORD1__DATA_FORMAT_shift = 22,//6 bits
244 EG_VTX_WORD1__DATA_FORMAT_mask = 0x3F << 22,
245 EG_VTX_WORD1__NFA_shift = 28,//2 bits
246 EG_VTX_WORD1__NFA_mask = 0x3 << 28,
247 EG_VTX_WORD1__FCA_shift = 30,//1 bit
248 EG_VTX_WORD1__FCA_bit = 1 << 30,
249 EG_VTX_WORD1__SMA_shift = 31,//1 bit
250 EG_VTX_WORD1__SMA_bit = 1 << 31,
251
252 EG_VTX_WORD2__OFFSET_shift = 0, //16 bits
253 EG_VTX_WORD2__OFFSET_mask = 0xFFFF,
254 EG_VTX_WORD2__ENDIAN_SWAP_shift = 16,//2 bits
255 EG_VTX_WORD2__ENDIAN_SWAP_mask = 0x3 << 16,
256 EG_VTX_WORD2__CBNS_shift = 18,//1 bit
257 EG_VTX_WORD2__CBNS_bit = 1 << 18,
258 EG_VTX_WORD2__MEGA_FETCH_shift = 19,//1 bit
259 EG_VTX_WORD2__MEGA_FETCH_mask = 1 << 19,
260 EG_VTX_WORD2__ALT_CONST_shift = 20,//1 bit
261 EG_VTX_WORD2__ALT_CONST_mask = 1 << 20,
262 EG_VTX_WORD2__BIM_shift = 21,//2 bits
263 EG_VTX_WORD2__BIM_mask = 0x3 << 21,
264 EG_VTX_WORD2__Reserved_shift = 23,//9 bits
265 EG_VTX_WORD2__Reserved_mask = 0x1FF << 23,
266
267 //CF_ALU
268 EG_CF_ALU_WORD0__ADDR_shift = 0, //22 bits
269 EG_CF_ALU_WORD0__ADDR_mask = 0x3FFFFF,
270 EG_CF_ALU_WORD0__KCACHE_BANK0_shift = 22,//4 bits
271 EG_CF_ALU_WORD0__KCACHE_BANK0_mask = 0xF << 22,
272 EG_CF_ALU_WORD0__KCACHE_BANK1_shift = 26,//4 bits
273 EG_CF_ALU_WORD0__KCACHE_BANK1_mask = 0xF << 26,
274 EG_CF_ALU_WORD0__KCACHE_MODE0_shift = 30,//2 bits
275 EG_CF_ALU_WORD0__KCACHE_MODE0_mask = 0x3 << 30,
276
277 EG_CF_ALU_WORD1__KCACHE_MODE1_shift = 0, //2 bits
278 EG_CF_ALU_WORD1__KCACHE_MODE1_mask = 0x3,
279 EG_CF_ALU_WORD1__KCACHE_ADDR0_shift = 2, //8 bits
280 EG_CF_ALU_WORD1__KCACHE_ADDR0_mask = 0xFF << 2,
281 EG_CF_ALU_WORD1__KCACHE_ADDR1_shift = 10, //8 bits
282 EG_CF_ALU_WORD1__KCACHE_ADDR1_mask = 0xFF << 10,
283 EG_CF_ALU_WORD1__COUNT_shift = 18, //7 bits
284 EG_CF_ALU_WORD1__COUNT_mask = 0x7F << 18,
285 EG_CF_ALU_WORD1__ALT_CONST_shift = 25, //1 bit
286 EG_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
287 EG_CF_ALU_WORD1__CF_INST_shift = 26, //4 bits
288 EG_CF_ALU_WORD1__CF_INST_mask = 0xF << 26,
289 EG_CF_ALU_WORD1__WQM_shift = 30, //1 bit
290 EG_CF_ALU_WORD1__WQM_bit = 1 << 30,
291 EG_CF_ALU_WORD1__BARRIER_shift = 31, //1 bit
292 EG_CF_ALU_WORD1__BARRIER_bit = 1 << 31,
293
294 EG_CF_INST_ALU = 8,
295 EG_CF_INST_ALU_PUSH_BEFORE = 9,
296 EG_CF_INST_ALU_POP_AFTER = 10,
297 EG_CF_INST_ALU_POP2_AFTER = 11,
298 EG_CF_INST_ALU_EXTENDED = 12,
299 EG_CF_INST_ALU_CONTINUE = 13,
300 EG_CF_INST_ALU_BREAK = 14,
301 EG_CF_INST_ALU_ELSE_AFTER = 15,
302
303 EG_CF_ALU_WORD0_EXT__Reserved0_shift = 0, //4 bits
304 EG_CF_ALU_WORD0_EXT__Reserved0_mask = 0xF,
305 EG_CF_ALU_WORD0_EXT__KBIM0_shift = 4, //2 bits
306 EG_CF_ALU_WORD0_EXT__KBIM0_mask = 0x3 << 4,
307 EG_CF_ALU_WORD0_EXT__KBIM1_shift = 6, //2 bits
308 EG_CF_ALU_WORD0_EXT__KBIM1_mask = 0x3 << 6,
309 EG_CF_ALU_WORD0_EXT__KBIM2_shift = 8, //2 bits
310 EG_CF_ALU_WORD0_EXT__KBIM2_mask = 0x3 << 8,
311 EG_CF_ALU_WORD0_EXT__KBIM3_shift = 10,//2 bits
312 EG_CF_ALU_WORD0_EXT__KBIM3_mask = 0x3 << 10,
313 EG_CF_ALU_WORD0_EXT__Reserved12_shift = 12,//10 bits
314 EG_CF_ALU_WORD0_EXT__Reserved12_mask = 0x3FF << 12,
315 EG_CF_ALU_WORD0_EXT__KCACHE_BANK2_shift = 22,//4 bits
316 EG_CF_ALU_WORD0_EXT__KCACHE_BANK2_mask = 0xF << 22,
317 EG_CF_ALU_WORD0_EXT__KCACHE_BANK3_shift = 26,//4 bits
318 EG_CF_ALU_WORD0_EXT__KCACHE_BANK3_mask = 0xF << 26,
319 EG_CF_ALU_WORD0_EXT__KCACHE_MODE2_shift = 30,//2 btis
320 EG_CF_ALU_WORD0_EXT__KCACHE_MODE2_mask = 0x3 << 30,
321
322 EG_CF_ALU_WORD1_EXT__KCACHE_MODE3_shift = 0, //2 bits
323 EG_CF_ALU_WORD1_EXT__KCACHE_MODE3_mask = 0x3,
324 EG_CF_ALU_WORD1_EXT__KCACHE_ADDR2_shift = 2, //8 bits
325 EG_CF_ALU_WORD1_EXT__KCACHE_ADDR2_mask = 0xFF << 2,
326 EG_CF_ALU_WORD1_EXT__KCACHE_ADDR3_shift = 10, //8 bits
327 EG_CF_ALU_WORD1_EXT__KCACHE_ADDR3_mask = 0xFF << 10,
328 EG_CF_ALU_WORD1_EXT__Reserved18_shift = 18, //8 bits
329 EG_CF_ALU_WORD1_EXT__Reserved18_mask = 0xFF << 18,
330 EG_CF_ALU_WORD1_EXT__CF_INST_shift = 26, //4 bits
331 EG_CF_ALU_WORD1_EXT__CF_INST_mask = 0xF << 26,
332 EG_CF_ALU_WORD1_EXT__Reserved30_shift = 30, //1 bit
333 EG_CF_ALU_WORD1_EXT__Reserved30_bit = 1 << 30,
334 EG_CF_ALU_WORD1_EXT__BARRIER_shift = 31, //1 bit
335 EG_CF_ALU_WORD1_EXT__BARRIER_bit = 1 << 31,
336
337 //ALU
338 EG_ALU_WORD0__SRC0_SEL_shift = 0, //9 bits
339 EG_ALU_WORD0__SRC0_SEL_mask = 0x1FF,
340 EG_ALU_WORD0__SRC1_SEL_shift = 13,//9 bits
341 EG_ALU_WORD0__SRC1_SEL_mask = 0x1FF << 13,
342 EG_ALU_WORD0__SRC0_REL_shift = 9, //1 bit
343 EG_ALU_WORD0__SRC0_REL_bit = 1 << 9,
344 EG_ALU_WORD0__SRC1_REL_shift = 22,//1 bit
345 EG_ALU_WORD0__SRC1_REL_bit = 1 << 22,
346 EG_ALU_WORD0__SRC0_CHAN_shift = 10,//2 bits
347 EG_ALU_WORD0__SRC0_CHAN_mask = 0x3 << 10,
348 EG_ALU_WORD0__SRC1_CHAN_shift = 23,//2 bits
349 EG_ALU_WORD0__SRC1_CHAN_mask = 0x3 << 23,
350 EG_ALU_WORD0__SRC0_NEG_shift = 12,//1 bit
351 EG_ALU_WORD0__SRC0_NEG_bit = 1 << 12,
352 EG_ALU_WORD0__SRC1_NEG_shift = 25,//1 bit
353 EG_ALU_WORD0__SRC1_NEG_bit = 1 << 25,
354 EG_ALU_WORD0__INDEX_MODE_shift = 26,//3 bits
355 EG_ALU_WORD0__INDEX_MODE_mask = 0x7 << 26,
356 EG_ALU_WORD0__PRED_SEL_shift = 29,//2 bits
357 EG_ALU_WORD0__PRED_SEL_mask = 0x3 << 29,
358 EG_ALU_WORD0__LAST_shift = 31,//1 bit
359 EG_ALU_WORD0__LAST_bit = 1 << 31,
360
361 EG_ALU_WORD1_OP2__SRC0_ABS_shift = 0, //1 bit
362 EG_ALU_WORD1_OP2__SRC0_ABS_bit = 1,
363 EG_ALU_WORD1_OP2__SRC1_ABS_shift = 1, //1 bit
364 EG_ALU_WORD1_OP2__SRC1_ABS_bit = 1 << 1,
365 EG_ALU_WORD1_OP2__UEM_shift = 2, //1 bit
366 EG_ALU_WORD1_OP2__UEM_bit = 1 << 2,
367 EG_ALU_WORD1_OP2__UPDATE_PRED_shift = 3, //1 bit
368 EG_ALU_WORD1_OP2__UPDATE_PRED_bit = 1 << 3,
369 EG_ALU_WORD1_OP2__WRITE_MASK_shift = 4, //1 bit
370 EG_ALU_WORD1_OP2__WRITE_MASK_bit = 1 << 4,
371 EG_ALU_WORD1_OP2__OMOD_shift = 5, //2 bits
372 EG_ALU_WORD1_OP2__OMOD_mask = 0x3 << 5,
373 EG_ALU_WORD1_OP2__ALU_INST_shift = 7, //11 bits
374 EG_ALU_WORD1_OP2__ALU_INST_mask = 0x7FF << 7,
375
376 EG_ALU_WORD1__BANK_SWIZZLE_shift = 18,//3 bits
377 EG_ALU_WORD1__BANK_SWIZZLE_mask = 0x7 << 18,
378 EG_ALU_WORD1__DST_GPR_shift = 21,//7 bits
379 EG_ALU_WORD1__DST_GPR_mask = 0x7F << 21,
380 EG_ALU_WORD1__DST_REL_shift = 28,//1 bit
381 EG_ALU_WORD1__DST_REL_mask = 1 << 28,
382 EG_ALU_WORD1__DST_CHAN_shift = 29,//2 bits
383 EG_ALU_WORD1__DST_CHAN_mask = 0x3 << 29,
384 EG_ALU_WORD1__CLAMP_shift = 31,//1 bits
385 EG_ALU_WORD1__CLAMP_mask = 1 << 31,
386
387 EG_ALU_WORD1_OP3__SRC2_SEL_shift = 0, //9 bits
388 EG_ALU_WORD1_OP3__SRC2_SEL_mask = 0x1FF,
389 EG_ALU_WORD1_OP3__SRC2_REL_shift = 9, //1 bit
390 EG_ALU_WORD1_OP3__SRC2_REL_bit = 1 << 9,
391 EG_ALU_WORD1_OP3__SRC2_CHAN_shift = 10,//2 bits
392 EG_ALU_WORD1_OP3__SRC2_CHAN_mask = 0x3 << 10,
393 EG_ALU_WORD1_OP3__SRC2_NEG_shift = 12,//1 bit
394 EG_ALU_WORD1_OP3__SRC2_NEG_bit = 1 << 12,
395 EG_ALU_WORD1_OP3__ALU_INST_shift = 13,//5 bits
396 EG_ALU_WORD1_OP3__ALU_INST_mask = 0x1F << 13,
397
398 EG_OP3_INST_BFE_UINT = 4,
399 EG_OP3_INST_BFE_INT = 5,
400 EG_OP3_INST_BFI_INT = 6,
401 EG_OP3_INST_FMA = 7,
402 EG_OP3_INST_CNDNE_64 = 9,
403 EG_OP3_INST_FMA_64 = 10,
404 EG_OP3_INST_LERP_UINT = 11,
405 EG_OP3_INST_BIT_ALIGN_INT = 12,
406 EG_OP3_INST_BYTE_ALIGN_INT = 13,
407 EG_OP3_INST_SAD_ACCUM_UINT = 14,
408 EG_OP3_INST_SAD_ACCUM_HI_UINT = 15,
409 EG_OP3_INST_MULADD_UINT24 = 16,
410 EG_OP3_INST_LDS_IDX_OP = 17,
411 EG_OP3_INST_MULADD = 20,
412 EG_OP3_INST_MULADD_M2 = 21,
413 EG_OP3_INST_MULADD_M4 = 22,
414 EG_OP3_INST_MULADD_D2 = 23,
415 EG_OP3_INST_MULADD_IEEE = 24,
416 EG_OP3_INST_CNDE = 25,
417 EG_OP3_INST_CNDGT = 26,
418 EG_OP3_INST_CNDGE = 27,
419 EG_OP3_INST_CNDE_INT = 28,
420 EG_OP3_INST_CMNDGT_INT = 29,
421 EG_OP3_INST_CMNDGE_INT = 30,
422 EG_OP3_INST_MUL_LIT = 31,
423
424 EG_OP2_INST_ADD = 0,
425 EG_OP2_INST_MUL = 1,
426 EG_OP2_INST_MUL_IEEE = 2,
427 EG_OP2_INST_MAX = 3,
428 EG_OP2_INST_MIN = 4,
429 EG_OP2_INST_MAX_DX10 = 5,
430 EG_OP2_INST_MIN_DX10 = 6,
431 EG_OP2_INST_SETE = 8,
432 EG_OP2_INST_SETGT = 9,
433 EG_OP2_INST_SETGE = 10,
434 EG_OP2_INST_SETNE = 11,
435 EG_OP2_INST_SETE_DX10 = 12,
436 EG_OP2_INST_SETGT_DX10 = 13,
437 EG_OP2_INST_SETGE_DX10 = 14,
438 EG_OP2_INST_SETNE_DX10 = 15,
439 EG_OP2_INST_FRACT = 16,
440 EG_OP2_INST_TRUNC = 17,
441 EG_OP2_INST_CEIL = 18,
442 EG_OP2_INST_RNDNE = 19,
443 EG_OP2_INST_FLOOR = 20,
444 EG_OP2_INST_ASHR_INT = 21,
445 EG_OP2_INST_LSHR_INT = 22,
446 EG_OP2_INST_LSHL_INT = 23,
447 EG_OP2_INST_MOV = 25,
448 EG_OP2_INST_NOP = 26,
449 EG_OP2_INST_MUL_64 = 27,
450 EG_OP2_INST_FLT64_TO_FLT32 = 28,
451 EG_OP2_INST_FLT32_TO_FLT64 = 29,
452 EG_OP2_INST_PRED_SETGT_UINT = 30,
453 EG_OP2_INST_PRED_SETGE_UINT = 31,
454 EG_OP2_INST_PRED_SETE = 32,
455 EG_OP2_INST_PRED_SETGT = 33,
456 EG_OP2_INST_PRED_SETGE = 34,
457 EG_OP2_INST_PRED_SETNE = 35,
458 EG_OP2_INST_PRED_SET_INV = 36,
459 EG_OP2_INST_PRED_SET_POP = 37,
460 EG_OP2_INST_PRED_SET_CLR = 38,
461 EG_OP2_INST_PRED_SET_RESTORE = 39,
462 EG_OP2_INST_PRED_SETE_PUSH = 40,
463 EG_OP2_INST_PRED_SETGT_PUSH = 41,
464 EG_OP2_INST_PRED_SETGE_PUSH = 42,
465 EG_OP2_INST_PRED_SETNE_PUSH = 43,
466 EG_OP2_INST_KILLE = 44,
467 EG_OP2_INST_KILLGT = 45,
468 EG_OP2_INST_KILLGE = 46,
469 EG_OP2_INST_KILLNE = 47,
470 EG_OP2_INST_AND_INT = 48,
471 EG_OP2_INST_OR_INT = 49,
472 EG_OP2_INST_XOR_INT = 50,
473 EG_OP2_INST_NOT_INT = 51,
474 EG_OP2_INST_ADD_INT = 52,
475 EG_OP2_INST_SUB_INT = 53,
476 EG_OP2_INST_MAX_INT = 54,
477 EG_OP2_INST_MIN_INT = 55,
478 EG_OP2_INST_MAX_UINT = 56,
479 EG_OP2_INST_MIN_UINT = 57,
480 EG_OP2_INST_SETE_INT = 58,
481 EG_OP2_INST_SETGT_INT = 59,
482 EG_OP2_INST_SETGE_INT = 60,
483 EG_OP2_INST_SETNE_INT = 61,
484 EG_OP2_INST_SETGT_UINT = 62,
485 EG_OP2_INST_SETGE_UINT = 63,
486 EG_OP2_INST_KILLGT_UINT = 64,
487 EG_OP2_INST_KILLGE_UINT = 65,
488 EG_OP2_INST_PREDE_INT = 66,
489 EG_OP2_INST_PRED_SETGT_INT = 67,
490 EG_OP2_INST_PRED_SETGE_INT = 68,
491 EG_OP2_INST_PRED_SETNE_INT = 69,
492 EG_OP2_INST_KILLE_INT = 70,
493 EG_OP2_INST_KILLGT_INT = 71,
494 EG_OP2_INST_KILLGE_INT = 72,
495 EG_OP2_INST_KILLNE_INT = 73,
496 EG_OP2_INST_PRED_SETE_PUSH_INT = 74,
497 EG_OP2_INST_PRED_SETGT_PUSH_INT = 75,
498 EG_OP2_INST_PRED_SETGE_PUSH_INT = 76,
499 EG_OP2_INST_PRED_SETNE_PUSH_INT = 77,
500 EG_OP2_INST_PRED_SETLT_PUSH_INT = 78,
501 EG_OP2_INST_PRED_SETLE_PUSH_INT = 79,
502 EG_OP2_INST_FLT_TO_INT = 80,
503 EG_OP2_INST_BFREV_INT = 81,
504 EG_OP2_INST_ADDC_UINT = 82,
505 EG_OP2_INST_SUBB_UINT = 83,
506 EG_OP2_INST_GROUP_BARRIER = 84,
507 EG_OP2_INST_GROUP_SEQ_BEGIN = 85,
508 EG_OP2_INST_GROUP_SEQ_END = 86,
509 EG_OP2_INST_SET_MODE = 87,
510 EG_OP2_INST_SET_CF_IDX0 = 88,
511 EG_OP2_INST_SET_CF_IDX1 = 89,
512 EG_OP2_INST_SET_LDS_SIZE = 90,
513 EG_OP2_INST_EXP_IEEE = 129,
514 EG_OP2_INST_LOG_CLAMPED = 130,
515 EG_OP2_INST_LOG_IEEE = 131,
516 EG_OP2_INST_RECIP_CLAMPED = 132,
517 EG_OP2_INST_RECIP_FF = 133,
518 EG_OP2_INST_RECIP_IEEE = 134,
519 EG_OP2_INST_RECIPSQRT_CLAMPED = 135,
520 EG_OP2_INST_RECIPSQRT_FF = 136,
521 EG_OP2_INST_RECIPSQRT_IEEE = 137,
522 EG_OP2_INST_SQRT_IEEE = 138,
523 EG_OP2_INST_SIN = 141,
524 EG_OP2_INST_COS = 142,
525 EG_OP2_INST_MULLO_INT = 143,
526 EG_OP2_INST_MULHI_INT = 144,
527 EG_OP2_INST_MULLO_UINT = 145,
528 EG_OP2_INST_MULHI_UINT = 146,
529 EG_OP2_INST_RECIP_INT = 147,
530 EG_OP2_INST_RECIP_UINT = 148,
531 EG_OP2_INST_RECIP_64 = 149,
532 EG_OP2_INST_RECIP_CLAMPED_64 = 150,
533 EG_OP2_INST_RECIPSQRT_64 = 151,
534 EG_OP2_INST_RECIPSQRT_CLAMPED_64 = 152,
535 EG_OP2_INST_SQRT_64 = 153,
536 EG_OP2_INST_FLT_TO_UINT = 154,
537 EG_OP2_INST_INT_TO_FLT = 155,
538 EG_OP2_INST_UINT_TO_FLT = 156,
539 EG_OP2_INST_BFM_INT = 160,
540 EG_OP2_INST_FLT32_TO_FLT16 = 162,
541 EG_OP2_INST_FLT16_TO_FLT32 = 163,
542 EG_OP2_INST_UBYTE0_FLT = 164,
543 EG_OP2_INST_UBYTE1_FLT = 165,
544 EG_OP2_INST_UBYTE2_FLT = 166,
545 EG_OP2_INST_UBYTE3_FLT = 167,
546 EG_OP2_INST_BCNT_INT = 170,
547 EG_OP2_INST_FFBH_UINT = 171,
548 EG_OP2_INST_FFBL_INT = 172,
549 EG_OP2_INST_FFBH_INT = 173,
550 EG_OP2_INST_FLT_TO_UINT4 = 174,
551 EG_OP2_INST_DOT_IEEE = 175,
552 EG_OP2_INST_FLT_TO_INT_RPI = 176,
553 EG_OP2_INST_FLT_TO_INT_FLOOR = 177,
554 EG_OP2_INST_MULHI_UINT24 = 178,
555 EG_OP2_INST_MBCNT_32HI_INT = 179,
556 EG_OP2_INST_OFFSET_TO_FLT = 180,
557 EG_OP2_INST_MUL_UINT24 = 181,
558 EG_OP2_INST_BCNT_ACCUM_PREV_INT = 182,
559 EG_OP2_INST_MBCNT_32LO_ACCUM_PREV_INT = 183,
560 EG_OP2_INST_SETE_64 = 184,
561 EG_OP2_INST_SETNE_64 = 185,
562 EG_OP2_INST_SETGT_64 = 186,
563 EG_OP2_INST_SETGE_64 = 187,
564 EG_OP2_INST_MIN_64 = 188,
565 EG_OP2_INST_MAX_64 = 189,
566 EG_OP2_INST_DOT4 = 190,
567 EG_OP2_INST_DOT4_IEEE = 191,
568 EG_OP2_INST_CUBE = 192,
569 EG_OP2_INST_MAX4 = 193,
570 EG_OP2_INST_FREXP_64 = 196,
571 EG_OP2_INST_LDEXP_64 = 197,
572 EG_OP2_INST_FRACT_64 = 198,
573 EG_OP2_INST_PRED_SETGT_64 = 199,
574 EG_OP2_INST_PRED_SETE_64 = 200,
575 EG_OP2_INST_PRED_SETGE_64 = 201,
576 EG_OP2_INST_MUL_64_2 = 202, //same as prev?
577 EG_OP2_INST_ADD_64 = 203,
578 EG_OP2_INST_MOVA_INT = 204,
579 EG_OP2_INST_FLT64_TO_FLT32_2 = 205, //same as prev?
580 EG_OP2_INST_FLT32_TO_FLT64_2 = 206, //same as prev?
581 EG_OP2_INST_SAD_ACCUM_PREV_UINT = 207,
582 EG_OP2_INST_DOT = 208,
583 EG_OP2_INST_MUL_PREV = 209,
584 EG_OP2_INST_MUL_IEEE_PREV = 210,
585 EG_OP2_INST_ADD_PREV = 211,
586 EG_OP2_INST_MULADD_PREV = 212,
587 EG_OP2_INST_MULADD_IEEE_PREV = 213,
588 EG_OP2_INST_INTERP_XY = 214,
589 EG_OP2_INST_INTERP_ZW = 215,
590 EG_OP2_INST_INTERP_X = 216,
591 EG_OP2_INST_INTERP_Z = 217,
592 EG_OP2_INST_STORE_FLAGS = 218,
593 EG_OP2_INST_LOAD_STORE_FLAGS = 219,
594 EG_OP2_INST_LDS_1A = 220,
595 EG_OP2_INST_LDS_1A1D = 221,
596 EG_OP2_INST_LDS_2A = 223,
597 EG_OP2_INST_INTERP_LOAD_P0 = 224,
598 EG_OP2_INST_INTERP_LOAD_P10 = 225,
599 EG_OP2_INST_INTERP_LOAD_P20 = 226,
600
601 EG_SRC_SEL__GPR_start = 0,
602 EG_SRC_SEL__GPR_end = 127,
603 EG_SRC_SEL__KCONST_BANK0_start = 128,
604 EG_SRC_SEL__KCONST_BANK0_end = 159,
605 EG_SRC_SEL__KCONST_BANK1_start = 160,
606 EG_SRC_SEL__KCONST_BANK1_end = 191,
607 EG_SRC_SEL__INLINE_satrt = 192,
608 EG_SRC_SEL__INLINE_end = 255,
609 EG_SRC_SEL__KCONST_BANK2_start = 256,
610 EG_SRC_SEL__KCONST_BANK2_end = 287,
611 EG_SRC_SEL__KCONST_BANK3_start = 288,
612 EG_SRC_SEL__KCONST_BANK3_end = 319,
613 EG_SRC_SEL__ALU_SRC_LDS_OQ_A = 219,
614 EG_SRC_SEL__ALU_SRC_LDS_OQ_B = 220,
615 EG_SRC_SEL__ALU_SRC_LDS_OQ_A_POP = 221,
616 EG_SRC_SEL__ALU_SRC_LDS_OQ_B_POP = 222,
617 EG_SRC_SEL__ALU_SRC_LDS_DIRECT_A = 223,
618 EG_SRC_SEL__ALU_SRC_LDS_DIRECT_B = 224,
619 EG_SRC_SEL__ALU_SRC_TIME_HI = 227,
620 EG_SRC_SEL__ALU_SRC_TIME_LO = 228,
621 EG_SRC_SEL__ALU_SRC_MASK_HI = 229,
622 EG_SRC_SEL__ALU_SRC_MASK_LO = 230,
623 EG_SRC_SEL__ALU_SRC_HW_WAVE_ID = 231,
624 EG_SRC_SEL__ALU_SRC_SIMD_ID = 232,
625 EG_SRC_SEL__ALU_SRC_SE_ID = 233,
626 EG_SRC_SEL__ALU_SRC_HW_THREADGRP_ID = 234,
627 EG_SRC_SEL__ALU_SRC_WAVE_ID_IN_GRP = 235,
628 EG_SRC_SEL__ALU_SRC_NUM_THREADGRP_WAVES = 236,
629 EG_SRC_SEL__ALU_SRC_HW_ALU_ODD = 237,
630 EG_SRC_SEL__ALU_SRC_LOOP_IDX = 238,
631 EG_SRC_SEL__ALU_SRC_PARAM_BASE_ADDR = 240,
632 EG_SRC_SEL__ALU_SRC_NEW_PRIM_MASK = 241,
633 EG_SRC_SEL__ALU_SRC_PRIM_MASK_HI = 242,
634 EG_SRC_SEL__ALU_SRC_PRIM_MASK_LO = 243,
635 EG_SRC_SEL__ALU_SRC_1_DBL_L = 244,
636 EG_SRC_SEL__ALU_SRC_1_DBL_M = 245,
637 EG_SRC_SEL__ALU_SRC_0_5_DBL_L = 246,
638 EG_SRC_SEL__ALU_SRC_0_5_DBL_M = 247,
639 EG_SRC_SEL__ALU_SRC_0 = 248,
640 EG_SRC_SEL__ALU_SRC_1 = 249,
641 EG_SRC_SEL__ALU_SRC_1_INT = 250,
642 EG_SRC_SEL__ALU_SRC_M_1_INT = 251,
643 EG_SRC_SEL__ALU_SRC_0_5 = 252,
644 EG_SRC_SEL__ALU_SRC_LITERAL = 253,
645 EG_SRC_SEL__ALU_SRC_PV = 254,
646 EG_SRC_SEL__ALU_SRC_PS = 255,
647
648 //ALLOC_EXPORT
649 EG_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE_shift = 0, //13 bits
650 EG_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE_mask = 0x1FFF,
651 EG_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13,//2 bits
652 EG_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x3 << 13,
653 EG_CF_ALLOC_EXPORT_WORD0__RW_GPR_shift = 15,//7 bits
654 EG_CF_ALLOC_EXPORT_WORD0__RW_GPR_mask = 0x7F << 15,
655 EG_CF_ALLOC_EXPORT_WORD0__RW_REL_shift = 22,//1 bit
656 EG_CF_ALLOC_EXPORT_WORD0__RW_REL_bit = 1 << 22,
657 EG_CF_ALLOC_EXPORT_WORD0__INDEX_GPR_shift = 23,//7 bits
658 EG_CF_ALLOC_EXPORT_WORD0__INDEX_GPR_mask = 0x7F << 23,
659 EG_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_shift = 30,//2 bits
660 EG_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_mask = 0x3 << 30,
661
662 EG_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_shift = 0, //12 bits
663 EG_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_mask = 0xFFF,
664 EG_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK_shift = 12, //4 bits
665 EG_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK_mask = 0xF << 12,
666
667 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X_shift = 0, //3 bits
668 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X_mask = 0x7,
669 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y_shift = 3, //3 bits
670 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y_mask = 0x7 << 3,
671 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z_shift = 6, //3 bits
672 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z_mask = 0x7 << 6,
673 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W_shift = 9, //3 bits
674 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W_mask = 0x7 << 9,
675 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__Resreve_shift = 12,//4 bits
676 EG_CF_ALLOC_EXPORT_WORD1_SWIZ__Resreve_mask = 0xF << 12,
677
678 EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_shift = 16, //4 bits
679 EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_mask = 0xF << 16,
680 EG_CF_ALLOC_EXPORT_WORD1__VPM_shift = 20, //1 bit
681 EG_CF_ALLOC_EXPORT_WORD1__VPM_bit = 1 << 20,
682 EG_CF_ALLOC_EXPORT_WORD1__EOP_shift = 21, //1 bit
683 EG_CF_ALLOC_EXPORT_WORD1__EOP_bit = 1 << 21,
684 EG_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 22, //8 bits
685 EG_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0xFF << 22,
686 EG_CF_ALLOC_EXPORT_WORD1__MARK_shift = 30, //1 bit
687 EG_CF_ALLOC_EXPORT_WORD1__MARK_bit = 1 << 30,
688 EG_CF_ALLOC_EXPORT_WORD1__BARRIER_shift = 31, //1 bit
689 EG_CF_ALLOC_EXPORT_WORD1__BARRIER_bit = 1 << 31,
690
691 EG_CF_INST_MEM_STREAM0_BUF0 = 64 ,
692 EG_CF_INST_MEM_STREAM0_BUF1 = 65,
693 EG_CF_INST_MEM_STREAM0_BUF2 = 66,
694 EG_CF_INST_MEM_STREAM0_BUF3 = 67,
695 EG_CF_INST_MEM_STREAM1_BUF0 = 68,
696 EG_CF_INST_MEM_STREAM1_BUF1 = 69,
697 EG_CF_INST_MEM_STREAM1_BUF2 = 70,
698 EG_CF_INST_MEM_STREAM1_BUF3 = 71,
699 EG_CF_INST_MEM_STREAM2_BUF0 = 72,
700 EG_CF_INST_MEM_STREAM2_BUF1 = 73,
701 EG_CF_INST_MEM_STREAM2_BUF2 = 74,
702 EG_CF_INST_MEM_STREAM2_BUF3 = 75,
703 EG_CF_INST_MEM_STREAM3_BUF0 = 76,
704 EG_CF_INST_MEM_STREAM3_BUF1 = 77,
705 EG_CF_INST_MEM_STREAM3_BUF2 = 78,
706 EG_CF_INST_MEM_STREAM3_BUF3 = 79,
707 EG_CF_INST_MEM_WR_SCRATCH = 80,
708 EG_CF_INST_MEM_RING = 82,
709 EG_CF_INST_EXPORT = 83,
710 EG_CF_INST_EXPORT_DONE = 84,
711 EG_CF_INST_MEM_EXPORT = 85,
712 EG_CF_INST_MEM_RAT = 86,
713 EG_CF_INST_MEM_RAT_CACHELESS = 87,
714 EG_CF_INST_MEM_RING1 = 88,
715 EG_CF_INST_MEM_RING2 = 89,
716 EG_CF_INST_MEM_RING3 = 90,
717 EG_CF_INST_MEM_EXPORT_COMBINED = 91,
718 EG_CF_INST_MEM_RAT_COMBINED_CACHELESS = 92,
719
720 EG_EXPORT_PIXEL = 0,
721 EG_EXPORT_WRITE = 0,
722 EG_EXPORT_POS = 1,
723 EG_EXPORT_WRITE_IND = 1,
724 EG_EXPORT_PARAM = 2,
725 EG_EXPORT_WRITE_ACK = 2,
726 EG_EXPORT_WRITE_IND_ACK = 3,
727
728 /* PS interp param source */
729 EG_ALU_SRC_PARAM_BASE = 0x000001c0,
730 EG_ALU_SRC_PARAM_SIZE = 0x00000021,
731 };
732
733 #endif //_EVERGREEN_SQ_H_
734
735