2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/imports.h"
30 #include "main/enums.h"
31 #include "main/macros.h"
32 #include "main/context.h"
34 #include "main/simple_list.h"
35 #include "main/state.h"
38 #include "tnl/t_pipeline.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "main/api_arrayelt.h"
42 #include "main/framebuffer.h"
43 #include "drivers/common/meta.h"
44 #include "program/prog_parameter.h"
45 #include "program/prog_statevars.h"
49 #include "r600_context.h"
51 #include "evergreen_state.h"
52 #include "evergreen_diff.h"
53 #include "evergreen_vertprog.h"
54 #include "evergreen_fragprog.h"
55 #include "evergreen_tex.h"
57 void evergreenUpdateStateParameters(struct gl_context
* ctx
, GLuint new_state
); //same
59 void evergreenUpdateShaders(struct gl_context
* ctx
)
61 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
63 /* should only happenen once, just after context is created */
64 /* TODO: shouldn't we fallback to sw here? */
65 if (!ctx
->FragmentProgram
._Current
) {
66 fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
70 evergreenSelectFragmentShader(ctx
);
72 evergreenSelectVertexShader(ctx
);
73 evergreenUpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
74 context
->radeon
.NewGLState
= 0;
77 void evergreeUpdateShaders(struct gl_context
* ctx
)
79 context_t
*context
= R700_CONTEXT(ctx
);
81 /* should only happenen once, just after context is created */
82 /* TODO: shouldn't we fallback to sw here? */
83 if (!ctx
->FragmentProgram
._Current
) {
84 fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
88 evergreenSelectFragmentShader(ctx
);
90 evergreenSelectVertexShader(ctx
);
91 evergreenUpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
92 context
->radeon
.NewGLState
= 0;
96 * To correctly position primitives:
98 void evergreenUpdateViewportOffset(struct gl_context
* ctx
) //------------------
100 context_t
*context
= R700_CONTEXT(ctx
);
101 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
102 __DRIdrawable
*dPriv
= radeon_get_drawable(&context
->radeon
);
103 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
104 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
105 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
108 GLfloat tx
= v
[MAT_TX
] + xoffset
;
109 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
111 if (evergreen
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
!= tx
||
112 evergreen
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
!= ty
) {
113 /* Note: this should also modify whatever data the context reset
116 EVERGREEN_STATECHANGE(context
, pa
);
117 evergreen
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
118 evergreen
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
121 radeonUpdateScissor(ctx
);
124 void evergreenUpdateStateParameters(struct gl_context
* ctx
, GLuint new_state
) //same
126 struct evergreen_fragment_program
*fp
=
127 (struct evergreen_fragment_program
*)ctx
->FragmentProgram
._Current
;
128 struct gl_program_parameter_list
*paramList
;
130 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
)))
133 if (!ctx
->FragmentProgram
._Current
|| !fp
)
136 paramList
= ctx
->FragmentProgram
._Current
->Base
.Parameters
;
141 _mesa_load_state_parameters(ctx
, paramList
);
146 * Called by Mesa after an internal state update.
148 static void evergreenInvalidateState(struct gl_context
* ctx
, GLuint new_state
) //same
150 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
152 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
154 _swrast_InvalidateState(ctx
, new_state
);
155 _swsetup_InvalidateState(ctx
, new_state
);
156 _vbo_InvalidateState(ctx
, new_state
);
157 _tnl_InvalidateState(ctx
, new_state
);
158 _ae_invalidate_state(ctx
, new_state
);
160 if (new_state
& _NEW_BUFFERS
) {
161 _mesa_update_framebuffer(ctx
);
162 /* this updates the DrawBuffer's Width/Height if it's a FBO */
163 _mesa_update_draw_buffer_bounds(ctx
);
165 EVERGREEN_STATECHANGE(context
, cb
);
166 EVERGREEN_STATECHANGE(context
, db
);
169 if (new_state
& (_NEW_LIGHT
)) {
170 EVERGREEN_STATECHANGE(context
, pa
);
171 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
)
172 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
174 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
177 evergreenUpdateStateParameters(ctx
, new_state
);
179 EVERGREEN_STATECHANGE(context
, pa
);
180 EVERGREEN_STATECHANGE(context
, spi
);
182 if(GL_TRUE
== evergreen
->bEnablePerspective
)
184 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
185 CLEARbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
186 CLEARbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
188 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
190 SETbit(evergreen
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
191 CLEARbit(evergreen
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
193 SETfield(evergreen
->SPI_BARYC_CNTL
.u32All
, 1,
194 EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_shift
,
195 EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_mask
);
199 /* For orthogonal case. */
200 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
201 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
203 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
205 CLEARbit(evergreen
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
206 SETbit(evergreen
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
208 SETfield(evergreen
->SPI_BARYC_CNTL
.u32All
, 1,
209 EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_shift
,
210 EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_mask
);
213 context
->radeon
.NewGLState
|= new_state
;
216 static void evergreenSetAlphaState(struct gl_context
* ctx
) //same
218 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
219 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
220 uint32_t alpha_func
= REF_ALWAYS
;
221 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
223 EVERGREEN_STATECHANGE(context
, sx
);
225 switch (ctx
->Color
.AlphaFunc
) {
227 alpha_func
= REF_NEVER
;
230 alpha_func
= REF_LESS
;
233 alpha_func
= REF_EQUAL
;
236 alpha_func
= REF_LEQUAL
;
239 alpha_func
= REF_GREATER
;
242 alpha_func
= REF_NOTEQUAL
;
245 alpha_func
= REF_GEQUAL
;
248 /*alpha_func = REF_ALWAYS; */
249 really_enabled
= GL_FALSE
;
253 if (really_enabled
) {
254 SETfield(evergreen
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
255 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
256 SETbit(evergreen
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
257 evergreen
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
259 CLEARbit(evergreen
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
263 static void evergreenAlphaFunc(struct gl_context
* ctx
, GLenum func
, GLfloat ref
) //same
267 evergreenSetAlphaState(ctx
);
270 static void evergreenBlendColor(struct gl_context
* ctx
, const GLfloat cf
[4]) //same
272 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
273 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
275 EVERGREEN_STATECHANGE(context
, cb
);
277 evergreen
->CB_BLEND_RED
.f32All
= cf
[0];
278 evergreen
->CB_BLEND_GREEN
.f32All
= cf
[1];
279 evergreen
->CB_BLEND_BLUE
.f32All
= cf
[2];
280 evergreen
->CB_BLEND_ALPHA
.f32All
= cf
[3];
283 static int evergreenblend_factor(GLenum factor
, GLboolean is_src
) //same
293 return BLEND_DST_COLOR
;
295 case GL_ONE_MINUS_DST_COLOR
:
296 return BLEND_ONE_MINUS_DST_COLOR
;
299 return BLEND_SRC_COLOR
;
301 case GL_ONE_MINUS_SRC_COLOR
:
302 return BLEND_ONE_MINUS_SRC_COLOR
;
305 return BLEND_SRC_ALPHA
;
307 case GL_ONE_MINUS_SRC_ALPHA
:
308 return BLEND_ONE_MINUS_SRC_ALPHA
;
311 return BLEND_DST_ALPHA
;
313 case GL_ONE_MINUS_DST_ALPHA
:
314 return BLEND_ONE_MINUS_DST_ALPHA
;
316 case GL_SRC_ALPHA_SATURATE
:
317 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
319 case GL_CONSTANT_COLOR
:
320 return BLEND_CONSTANT_COLOR
;
322 case GL_ONE_MINUS_CONSTANT_COLOR
:
323 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
325 case GL_CONSTANT_ALPHA
:
326 return BLEND_CONSTANT_ALPHA
;
328 case GL_ONE_MINUS_CONSTANT_ALPHA
:
329 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
332 fprintf(stderr
, "unknown blend factor %x\n", factor
);
333 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
338 static void evergreenSetBlendState(struct gl_context
* ctx
) //diff : CB_COLOR_CONTROL, CB_BLEND0_CONTROL bits
340 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
341 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
342 uint32_t blend_reg
= 0, eqn
, eqnA
;
344 EVERGREEN_STATECHANGE(context
, cb
);
346 if (ctx
->Color
.ColorLogicOpEnabled
|| !ctx
->Color
.BlendEnabled
) {
348 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
350 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
352 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
354 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
356 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
358 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
359 //if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
360 // evergreen->CB_BLEND_CONTROL.u32All = blend_reg;
362 evergreen
->CB_BLEND0_CONTROL
.u32All
= blend_reg
;
367 evergreenblend_factor(ctx
->Color
.Blend
[0].SrcRGB
, GL_TRUE
),
368 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
370 evergreenblend_factor(ctx
->Color
.Blend
[0].DstRGB
, GL_FALSE
),
371 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
373 switch (ctx
->Color
.Blend
[0].EquationRGB
) {
375 eqn
= COMB_DST_PLUS_SRC
;
377 case GL_FUNC_SUBTRACT
:
378 eqn
= COMB_SRC_MINUS_DST
;
380 case GL_FUNC_REVERSE_SUBTRACT
:
381 eqn
= COMB_DST_MINUS_SRC
;
384 eqn
= COMB_MIN_DST_SRC
;
387 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
390 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
393 eqn
= COMB_MAX_DST_SRC
;
396 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
399 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
404 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
405 __FUNCTION__
, __LINE__
, ctx
->Color
.Blend
[0].EquationRGB
);
409 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
412 evergreenblend_factor(ctx
->Color
.Blend
[0].SrcA
, GL_TRUE
),
413 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
415 evergreenblend_factor(ctx
->Color
.Blend
[0].DstA
, GL_FALSE
),
416 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
418 switch (ctx
->Color
.Blend
[0].EquationA
) {
420 eqnA
= COMB_DST_PLUS_SRC
;
422 case GL_FUNC_SUBTRACT
:
423 eqnA
= COMB_SRC_MINUS_DST
;
425 case GL_FUNC_REVERSE_SUBTRACT
:
426 eqnA
= COMB_DST_MINUS_SRC
;
429 eqnA
= COMB_MIN_DST_SRC
;
432 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
435 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
438 eqnA
= COMB_MAX_DST_SRC
;
441 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
444 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
448 "[%s:%u] Invalid A blend equation (0x%04x).\n",
449 __FUNCTION__
, __LINE__
, ctx
->Color
.Blend
[0].EquationA
);
454 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
456 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
458 SETbit(blend_reg
, EG_CB_BLENDX_CONTROL_ENABLE_bit
);
460 evergreen
->CB_BLEND0_CONTROL
.u32All
= blend_reg
;
463 static void evergreenBlendEquationSeparate(struct gl_context
* ctx
,
464 GLenum modeRGB
, GLenum modeA
) //same
466 evergreenSetBlendState(ctx
);
469 static void evergreenBlendFuncSeparate(struct gl_context
* ctx
,
470 GLenum sfactorRGB
, GLenum dfactorRGB
,
471 GLenum sfactorA
, GLenum dfactorA
) //same
473 evergreenSetBlendState(ctx
);
476 static GLuint
evergreen_translate_logicop(GLenum logicop
) //same
485 case GL_COPY_INVERTED
:
505 case GL_AND_INVERTED
:
512 fprintf(stderr
, "unknown blend logic operation %x\n", logicop
);
517 static void evergreenSetLogicOpState(struct gl_context
*ctx
) //diff : CB_COLOR_CONTROL.ROP3 is actually same bits.
519 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
520 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
522 EVERGREEN_STATECHANGE(context
, cb
);
524 if (ctx
->Color
.ColorLogicOpEnabled
)
525 SETfield(evergreen
->CB_COLOR_CONTROL
.u32All
,
526 evergreen_translate_logicop(ctx
->Color
.LogicOp
),
527 EG_CB_COLOR_CONTROL__ROP3_shift
,
528 EG_CB_COLOR_CONTROL__ROP3_mask
);
530 SETfield(evergreen
->CB_COLOR_CONTROL
.u32All
, 0xCC,
531 EG_CB_COLOR_CONTROL__ROP3_shift
,
532 EG_CB_COLOR_CONTROL__ROP3_mask
);
535 static void evergreenClipPlane( struct gl_context
*ctx
, GLenum plane
, const GLfloat
*eq
) //same , but PA_CL_UCP_0_ offset diff
537 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
538 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
542 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
543 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
545 EVERGREEN_STATECHANGE(context
, pa
);
547 evergreen
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
548 evergreen
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
549 evergreen
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
550 evergreen
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
553 static void evergreenSetClipPlaneState(struct gl_context
* ctx
, GLenum cap
, GLboolean state
) //diff in func calls
555 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
556 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
559 p
= cap
- GL_CLIP_PLANE0
;
561 EVERGREEN_STATECHANGE(context
, pa
);
564 evergreen
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
565 evergreen
->ucp
[p
].enabled
= GL_TRUE
;
566 evergreenClipPlane(ctx
, cap
, NULL
);
568 evergreen
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
569 evergreen
->ucp
[p
].enabled
= GL_FALSE
;
573 static void evergreenSetDBRenderState(struct gl_context
* ctx
)
575 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
576 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
577 struct evergreen_fragment_program
*fp
=
578 (struct evergreen_fragment_program
*)(ctx
->FragmentProgram
._Current
);
580 EVERGREEN_STATECHANGE(context
, db
);
582 SETbit(evergreen
->DB_SHADER_CONTROL
.u32All
,
583 DUAL_EXPORT_ENABLE_bit
);
584 SETfield(evergreen
->DB_SHADER_CONTROL
.u32All
, EARLY_Z_THEN_LATE_Z
,
587 /* XXX need to enable htile for hiz/s */
588 SETfield(evergreen
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
,
589 FORCE_HIZ_ENABLE_shift
,
590 FORCE_HIZ_ENABLE_mask
);
591 SETfield(evergreen
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
,
592 FORCE_HIS_ENABLE0_shift
,
593 FORCE_HIS_ENABLE0_mask
);
594 SETfield(evergreen
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
,
595 FORCE_HIS_ENABLE1_shift
,
596 FORCE_HIS_ENABLE1_mask
);
598 if (context
->radeon
.query
.current
)
600 SETbit(evergreen
->DB_RENDER_OVERRIDE
.u32All
, NOOP_CULL_DISABLE_bit
);
601 SETbit(evergreen
->DB_COUNT_CONTROL
.u32All
,
602 EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_bit
);
606 CLEARbit(evergreen
->DB_RENDER_OVERRIDE
.u32All
, NOOP_CULL_DISABLE_bit
);
607 CLEARbit(evergreen
->DB_COUNT_CONTROL
.u32All
,
608 EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_bit
);
613 if (fp
->r700Shader
.killIsUsed
)
615 SETbit(evergreen
->DB_SHADER_CONTROL
.u32All
, KILL_ENABLE_bit
);
619 CLEARbit(evergreen
->DB_SHADER_CONTROL
.u32All
, KILL_ENABLE_bit
);
622 if (fp
->r700Shader
.depthIsExported
)
624 SETbit(evergreen
->DB_SHADER_CONTROL
.u32All
, Z_EXPORT_ENABLE_bit
);
628 CLEARbit(evergreen
->DB_SHADER_CONTROL
.u32All
, Z_EXPORT_ENABLE_bit
);
633 void evergreenUpdateShaderStates(struct gl_context
* ctx
)
635 evergreenSetDBRenderState(ctx
);
636 evergreenUpdateTextureState(ctx
);
639 static void evergreenSetDepthState(struct gl_context
* ctx
) //same
641 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
642 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
644 EVERGREEN_STATECHANGE(context
, db
);
648 SETbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
651 SETbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
655 CLEARbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
658 switch (ctx
->Depth
.Func
)
661 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
662 ZFUNC_shift
, ZFUNC_mask
);
665 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
666 ZFUNC_shift
, ZFUNC_mask
);
669 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
670 ZFUNC_shift
, ZFUNC_mask
);
673 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
674 ZFUNC_shift
, ZFUNC_mask
);
677 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
678 ZFUNC_shift
, ZFUNC_mask
);
681 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
682 ZFUNC_shift
, ZFUNC_mask
);
685 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
686 ZFUNC_shift
, ZFUNC_mask
);
689 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
690 ZFUNC_shift
, ZFUNC_mask
);
693 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
694 ZFUNC_shift
, ZFUNC_mask
);
700 CLEARbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
701 CLEARbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
705 static void evergreenSetStencilState(struct gl_context
* ctx
, GLboolean state
) //same
707 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
708 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
709 GLboolean hw_stencil
= GL_FALSE
;
711 if (ctx
->DrawBuffer
) {
712 struct radeon_renderbuffer
*rrbStencil
713 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
714 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
718 EVERGREEN_STATECHANGE(context
, db
);
720 SETbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
721 SETbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, BACKFACE_ENABLE_bit
);
722 SETbit(evergreen
->DB_STENCIL_INFO
.u32All
, EG_DB_STENCIL_INFO__FORMAT_bit
);
724 CLEARbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
728 static void evergreenUpdateCulling(struct gl_context
* ctx
) //same
730 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
731 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
733 EVERGREEN_STATECHANGE(context
, pa
);
735 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
736 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
737 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
739 if (ctx
->Polygon
.CullFlag
)
741 switch (ctx
->Polygon
.CullFaceMode
)
744 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
745 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
748 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
749 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
751 case GL_FRONT_AND_BACK
:
752 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
753 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
756 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
757 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
762 switch (ctx
->Polygon
.FrontFace
)
765 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
768 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
771 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
775 /* Winding is inverted when rendering to FBO */
776 if (ctx
->DrawBuffer
&& ctx
->DrawBuffer
->Name
)
777 evergreen
->PA_SU_SC_MODE_CNTL
.u32All
^= FACE_bit
;
780 static void evergreenSetPolygonOffsetState(struct gl_context
* ctx
, GLboolean state
) //same
782 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
783 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
785 EVERGREEN_STATECHANGE(context
, pa
);
788 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
789 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
790 SETbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
792 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
793 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
794 CLEARbit(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
798 static void evergreenUpdateLineStipple(struct gl_context
* ctx
) //diff
803 void evergreenSetScissor(context_t
*context
) //diff
805 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
806 unsigned x1
, y1
, x2
, y2
;
808 struct radeon_renderbuffer
*rrb
;
810 rrb
= radeon_get_colorbuffer(&context
->radeon
);
811 if (!rrb
|| !rrb
->bo
) {
814 if (context
->radeon
.state
.scissor
.enabled
) {
815 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
816 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
817 x2
= context
->radeon
.state
.scissor
.rect
.x2
;
818 y2
= context
->radeon
.state
.scissor
.rect
.y2
;
819 /* r600 has exclusive BR scissors */
820 if (context
->radeon
.radeonScreen
->kernel_mm
) {
825 if (context
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
828 x2
= rrb
->base
.Width
;
829 y2
= rrb
->base
.Height
;
833 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
834 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
838 EVERGREEN_STATECHANGE(context
, pa
);
841 /* TODO : check WINDOW_OFFSET_DISABLE */
842 //SETbit(evergreen->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
843 SETfield(evergreen
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, x1
,
844 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift
, EG_PA_SC_SCREEN_SCISSOR_TL__TL_X_mask
);
845 SETfield(evergreen
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, y1
,
846 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift
, EG_PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask
);
848 SETfield(evergreen
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, x2
,
849 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, EG_PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
850 SETfield(evergreen
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, y2
,
851 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, EG_PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
854 SETbit(evergreen
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
855 SETfield(evergreen
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
856 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, EG_PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
857 SETfield(evergreen
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
858 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, EG_PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
860 SETfield(evergreen
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
861 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, EG_PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
862 SETfield(evergreen
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
863 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, EG_PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
866 SETfield(evergreen
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
867 PA_SC_CLIPRECT_0_TL__TL_X_shift
, EG_PA_SC_CLIPRECT_0_TL__TL_X_mask
);
868 SETfield(evergreen
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
869 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, EG_PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
870 SETfield(evergreen
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
871 PA_SC_CLIPRECT_0_BR__BR_X_shift
, EG_PA_SC_CLIPRECT_0_BR__BR_X_mask
);
872 SETfield(evergreen
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
873 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, EG_PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
875 evergreen
->PA_SC_CLIPRECT_1_TL
.u32All
= evergreen
->PA_SC_CLIPRECT_0_TL
.u32All
;
876 evergreen
->PA_SC_CLIPRECT_1_BR
.u32All
= evergreen
->PA_SC_CLIPRECT_0_BR
.u32All
;
877 evergreen
->PA_SC_CLIPRECT_2_TL
.u32All
= evergreen
->PA_SC_CLIPRECT_0_TL
.u32All
;
878 evergreen
->PA_SC_CLIPRECT_2_BR
.u32All
= evergreen
->PA_SC_CLIPRECT_0_BR
.u32All
;
879 evergreen
->PA_SC_CLIPRECT_3_TL
.u32All
= evergreen
->PA_SC_CLIPRECT_0_TL
.u32All
;
880 evergreen
->PA_SC_CLIPRECT_3_BR
.u32All
= evergreen
->PA_SC_CLIPRECT_0_BR
.u32All
;
882 /* more....2d clip */
883 SETbit(evergreen
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
884 SETfield(evergreen
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
885 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, EG_PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
886 SETfield(evergreen
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
887 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, EG_PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
888 SETfield(evergreen
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
889 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, EG_PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
890 SETfield(evergreen
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
891 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, EG_PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
893 SETbit(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
894 SETfield(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
895 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, EG_PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
896 SETfield(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
897 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, EG_PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
898 SETfield(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
899 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, EG_PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
900 SETfield(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
901 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, EG_PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
904 SETbit(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
905 SETfield(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
906 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, EG_PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
907 SETfield(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
908 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, EG_PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
909 SETfield(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
910 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, EG_PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
911 SETfield(evergreen
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
912 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, EG_PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
914 evergreen
->viewport
[id
].enabled
= GL_TRUE
;
917 static void evergreenUpdateWindow(struct gl_context
* ctx
, int id
) //diff in calling evergreenSetScissor
919 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
920 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
921 __DRIdrawable
*dPriv
= radeon_get_drawable(&context
->radeon
);
922 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
923 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
924 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
925 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
926 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
927 GLfloat y_scale
, y_bias
;
937 GLfloat sx
= v
[MAT_SX
];
938 GLfloat tx
= v
[MAT_TX
] + xoffset
;
939 GLfloat sy
= v
[MAT_SY
] * y_scale
;
940 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
941 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
942 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
944 EVERGREEN_STATECHANGE(context
, pa
);
947 evergreen
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
948 evergreen
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
950 evergreen
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
951 evergreen
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
953 evergreen
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
954 evergreen
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
956 if (ctx
->Transform
.DepthClamp
) {
957 evergreen
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.f32All
= MIN2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
958 evergreen
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.f32All
= MAX2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
959 SETbit(evergreen
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_NEAR_DISABLE_bit
);
960 SETbit(evergreen
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_FAR_DISABLE_bit
);
962 evergreen
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.f32All
= 0.0;
963 evergreen
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.f32All
= 1.0;
964 CLEARbit(evergreen
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_NEAR_DISABLE_bit
);
965 CLEARbit(evergreen
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_FAR_DISABLE_bit
);
968 evergreen
->viewport
[id
].enabled
= GL_TRUE
;
970 evergreenSetScissor(context
);
973 static void evergreenEnable(struct gl_context
* ctx
, GLenum cap
, GLboolean state
) //diff in func calls
975 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
987 evergreenSetAlphaState(ctx
);
989 case GL_COLOR_LOGIC_OP
:
990 evergreenSetLogicOpState(ctx
);
991 /* fall-through, because logic op overrides blending */
993 evergreenSetBlendState(ctx
);
1000 case GL_CLIP_PLANE5
:
1001 evergreenSetClipPlaneState(ctx
, cap
, state
);
1004 evergreenSetDepthState(ctx
);
1006 case GL_STENCIL_TEST
:
1007 evergreenSetStencilState(ctx
, state
);
1010 evergreenUpdateCulling(ctx
);
1012 case GL_POLYGON_OFFSET_POINT
:
1013 case GL_POLYGON_OFFSET_LINE
:
1014 case GL_POLYGON_OFFSET_FILL
:
1015 evergreenSetPolygonOffsetState(ctx
, state
);
1017 case GL_SCISSOR_TEST
:
1018 radeon_firevertices(&context
->radeon
);
1019 context
->radeon
.state
.scissor
.enabled
= state
;
1020 radeonUpdateScissor(ctx
);
1022 case GL_LINE_STIPPLE
:
1023 evergreenUpdateLineStipple(ctx
);
1025 case GL_DEPTH_CLAMP
:
1026 evergreenUpdateWindow(ctx
, 0);
1034 static void evergreenColorMask(struct gl_context
* ctx
,
1035 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //same
1037 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1038 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1039 unsigned int mask
= ((r
? 1 : 0) |
1044 if (mask
!= evergreen
->CB_TARGET_MASK
.u32All
) {
1045 EVERGREEN_STATECHANGE(context
, cb
);
1046 SETfield(evergreen
->CB_TARGET_MASK
.u32All
, mask
, TARGET0_ENABLE_shift
, TARGET0_ENABLE_mask
);
1050 static void evergreenDepthFunc(struct gl_context
* ctx
, GLenum func
) //same
1052 evergreenSetDepthState(ctx
);
1055 static void evergreenDepthMask(struct gl_context
* ctx
, GLboolean mask
) //same
1057 evergreenSetDepthState(ctx
);
1060 static void evergreenCullFace(struct gl_context
* ctx
, GLenum mode
) //same
1062 evergreenUpdateCulling(ctx
);
1065 static void evergreenFogfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
) //same
1069 static void evergreenUpdatePolygonMode(struct gl_context
* ctx
) //same
1071 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1072 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1074 EVERGREEN_STATECHANGE(context
, pa
);
1076 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1078 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1079 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1080 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1083 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1084 * correctly by selecting the correct front and back face
1086 f
= ctx
->Polygon
.FrontMode
;
1087 b
= ctx
->Polygon
.BackMode
;
1089 /* Enable polygon mode */
1090 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1094 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1095 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1098 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1099 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1102 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1103 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1109 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1110 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1113 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1114 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1117 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1118 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1124 static void evergreenFrontFace(struct gl_context
* ctx
, GLenum mode
) //same
1126 evergreenUpdateCulling(ctx
);
1127 evergreenUpdatePolygonMode(ctx
);
1130 static void evergreenShadeModel(struct gl_context
* ctx
, GLenum mode
) //same
1132 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1133 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1135 EVERGREEN_STATECHANGE(context
, spi
);
1137 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
1140 SETbit(evergreen
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
1143 CLEARbit(evergreen
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
1150 static void evergreenLogicOpcode(struct gl_context
*ctx
, GLenum logicop
) //diff
1152 if (ctx
->Color
.ColorLogicOpEnabled
)
1153 evergreenSetLogicOpState(ctx
);
1156 static void evergreenPointSize(struct gl_context
* ctx
, GLfloat size
) //same
1158 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1159 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1161 EVERGREEN_STATECHANGE(context
, pa
);
1163 /* We need to clamp to user defined range here, because
1164 * the HW clamping happens only for per vertex point size. */
1165 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
1167 /* same size limits for AA, non-AA points */
1168 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
1170 /* format is 12.4 fixed point */
1171 SETfield(evergreen
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
1172 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
1173 SETfield(evergreen
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
1174 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
1178 static void evergreenPointParameter(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
) //same
1180 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1181 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1183 EVERGREEN_STATECHANGE(context
, pa
);
1185 /* format is 12.4 fixed point */
1187 case GL_POINT_SIZE_MIN
:
1188 SETfield(evergreen
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 8.0),
1189 MIN_SIZE_shift
, MIN_SIZE_mask
);
1190 evergreenPointSize(ctx
, ctx
->Point
.Size
);
1192 case GL_POINT_SIZE_MAX
:
1193 SETfield(evergreen
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 8.0),
1194 MAX_SIZE_shift
, MAX_SIZE_mask
);
1195 evergreenPointSize(ctx
, ctx
->Point
.Size
);
1197 case GL_POINT_DISTANCE_ATTENUATION
:
1199 case GL_POINT_FADE_THRESHOLD_SIZE
:
1206 static int evergreen_translate_stencil_func(int func
) //same
1220 return REF_NOTEQUAL
;
1229 static void evergreenStencilFuncSeparate(struct gl_context
* ctx
, GLenum face
,
1230 GLenum func
, GLint ref
, GLuint mask
) //same
1232 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1233 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1234 const unsigned back
= ctx
->Stencil
._BackFace
;
1237 EVERGREEN_STATECHANGE(context
, db
);
1240 SETfield(evergreen
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
1241 STENCILREF_shift
, STENCILREF_mask
);
1242 SETfield(evergreen
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
1243 STENCILMASK_shift
, STENCILMASK_mask
);
1245 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, evergreen_translate_stencil_func(ctx
->Stencil
.Function
[0]),
1246 STENCILFUNC_shift
, STENCILFUNC_mask
);
1249 SETfield(evergreen
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
1250 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
1251 SETfield(evergreen
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
1252 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
1254 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, evergreen_translate_stencil_func(ctx
->Stencil
.Function
[back
]),
1255 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
1258 static void evergreenStencilMaskSeparate(struct gl_context
* ctx
, GLenum face
, GLuint mask
) //same
1260 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1261 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1262 const unsigned back
= ctx
->Stencil
._BackFace
;
1264 EVERGREEN_STATECHANGE(context
, db
);
1267 SETfield(evergreen
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
1268 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
1271 SETfield(evergreen
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
1272 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
1276 static int evergreen_translate_stencil_op(int op
) //same
1280 return STENCIL_KEEP
;
1282 return STENCIL_ZERO
;
1284 return STENCIL_REPLACE
;
1286 return STENCIL_INCR_CLAMP
;
1288 return STENCIL_DECR_CLAMP
;
1289 case GL_INCR_WRAP_EXT
:
1290 return STENCIL_INCR_WRAP
;
1291 case GL_DECR_WRAP_EXT
:
1292 return STENCIL_DECR_WRAP
;
1294 return STENCIL_INVERT
;
1296 WARN_ONCE("Do not know how to translate stencil op");
1297 return STENCIL_KEEP
;
1302 static void evergreenStencilOpSeparate(struct gl_context
* ctx
, GLenum face
,
1303 GLenum fail
, GLenum zfail
, GLenum zpass
) //same
1305 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1306 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1307 const unsigned back
= ctx
->Stencil
._BackFace
;
1309 EVERGREEN_STATECHANGE(context
, db
);
1311 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, evergreen_translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
1312 STENCILFAIL_shift
, STENCILFAIL_mask
);
1313 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, evergreen_translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
1314 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
1315 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, evergreen_translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
1316 STENCILZPASS_shift
, STENCILZPASS_mask
);
1318 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, evergreen_translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
1319 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1320 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, evergreen_translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1321 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1322 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, evergreen_translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1323 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1326 static void evergreenViewport(struct gl_context
* ctx
,
1330 GLsizei height
) //diff in evergreenUpdateWindow
1332 evergreenUpdateWindow(ctx
, 0);
1334 radeon_viewport(ctx
, x
, y
, width
, height
);
1337 static void evergreenDepthRange(struct gl_context
* ctx
, GLclampd nearval
, GLclampd farval
) //diff in evergreenUpdateWindow
1339 evergreenUpdateWindow(ctx
, 0);
1342 static void evergreenLineWidth(struct gl_context
* ctx
, GLfloat widthf
) //same
1344 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1345 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1346 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1348 EVERGREEN_STATECHANGE(context
, pa
);
1350 if (lineWidth
> 0xFFFF)
1352 SETfield(evergreen
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1353 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1356 static void evergreenLineStipple(struct gl_context
*ctx
, GLint factor
, GLushort pattern
) //same
1358 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1359 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1361 EVERGREEN_STATECHANGE(context
, pa
);
1363 SETfield(evergreen
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1364 SETfield(evergreen
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1365 SETfield(evergreen
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1368 static void evergreenPolygonOffset(struct gl_context
* ctx
, GLfloat factor
, GLfloat units
) //diff :
1369 //all register here offset diff, bits same
1371 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1372 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1373 GLfloat constant
= units
;
1376 EVERGREEN_STATECHANGE(context
, pa
);
1378 switch (ctx
->Visual
.depthBits
) {
1390 SETfield(evergreen
->PA_SU_POLY_OFFSET_DB_FMT_CNTL
.u32All
, depth
,
1391 POLY_OFFSET_NEG_NUM_DB_BITS_shift
, POLY_OFFSET_NEG_NUM_DB_BITS_mask
);
1392 //evergreen->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1393 evergreen
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1394 evergreen
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1395 evergreen
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1396 evergreen
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1399 static void evergreenPolygonMode(struct gl_context
* ctx
, GLenum face
, GLenum mode
) //same
1404 evergreenUpdatePolygonMode(ctx
);
1407 static void evergreenRenderMode(struct gl_context
* ctx
, GLenum mode
) //same
1411 //TODO : move to kernel.
1412 static void evergreenInitSQConfig(struct gl_context
* ctx
)
1414 context_t
*context
= EVERGREEN_CONTEXT(ctx
);
1415 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1417 uint32_t uSqNumCfInsts
, uMaxGPRs
, uMaxThreads
, uMaxStackEntries
, uPSThreadCount
, uOtherThreadCount
;
1418 uint32_t NUM_PS_GPRS
, NUM_VS_GPRS
, NUM_GS_GPRS
, NUM_ES_GPRS
, NUM_HS_GPRS
, NUM_LS_GPRS
, NUM_CLAUSE_TEMP_GPRS
;
1419 GLboolean bVC_ENABLE
= GL_TRUE
;
1421 R600_STATECHANGE(context
, sq
);
1423 switch (context
->radeon
.radeonScreen
->chip_family
)
1425 case CHIP_FAMILY_CEDAR
:
1427 bVC_ENABLE
= GL_FALSE
;
1429 uPSThreadCount
= 96;
1431 uMaxStackEntries
= 256;
1433 case CHIP_FAMILY_REDWOOD
:
1435 bVC_ENABLE
= GL_TRUE
;
1437 uPSThreadCount
= 128;
1439 uMaxStackEntries
= 256;
1441 case CHIP_FAMILY_JUNIPER
:
1443 bVC_ENABLE
= GL_TRUE
;
1445 uPSThreadCount
= 128;
1447 uMaxStackEntries
= 512;
1449 case CHIP_FAMILY_CYPRESS
:
1451 bVC_ENABLE
= GL_TRUE
;
1453 uPSThreadCount
= 128;
1455 uMaxStackEntries
= 512;
1457 case CHIP_FAMILY_HEMLOCK
:
1458 uSqNumCfInsts
= 2;//?
1459 bVC_ENABLE
= GL_TRUE
;
1461 uPSThreadCount
= 128;
1463 uMaxStackEntries
= 512;
1465 case CHIP_FAMILY_PALM
:
1467 bVC_ENABLE
= GL_FALSE
;
1469 uPSThreadCount
= 96;
1471 uMaxStackEntries
= 256;
1473 case CHIP_FAMILY_SUMO
:
1475 bVC_ENABLE
= GL_FALSE
;
1477 uPSThreadCount
= 96;
1479 uMaxStackEntries
= 256;
1481 case CHIP_FAMILY_SUMO2
:
1483 bVC_ENABLE
= GL_FALSE
;
1485 uPSThreadCount
= 96;
1487 uMaxStackEntries
= 512;
1489 case CHIP_FAMILY_BARTS
:
1491 bVC_ENABLE
= GL_TRUE
;
1493 uPSThreadCount
= 128;
1495 uMaxStackEntries
= 512;
1497 case CHIP_FAMILY_TURKS
:
1499 bVC_ENABLE
= GL_TRUE
;
1501 uPSThreadCount
= 128;
1503 uMaxStackEntries
= 256;
1505 case CHIP_FAMILY_CAICOS
:
1507 bVC_ENABLE
= GL_FALSE
;
1509 uPSThreadCount
= 128;
1511 uMaxStackEntries
= 256;
1515 bVC_ENABLE
= GL_TRUE
;
1517 uPSThreadCount
= 128;
1519 uMaxStackEntries
= 512;
1523 evergreen
->evergreen_config
.SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1525 evergreen
->evergreen_config
.SPI_CONFIG_CNTL
.u32All
= 0;
1526 evergreen
->evergreen_config
.SPI_CONFIG_CNTL_1
.u32All
= 0;
1527 SETfield(evergreen
->evergreen_config
.SPI_CONFIG_CNTL_1
.u32All
, 4,
1528 EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_shift
,
1529 EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_mask
);
1531 evergreen
->evergreen_config
.CP_PERFMON_CNTL
.u32All
= 0;
1533 evergreen
->evergreen_config
.SQ_MS_FIFO_SIZES
.u32All
= 0;
1534 SETfield(evergreen
->evergreen_config
.SQ_MS_FIFO_SIZES
.u32All
, 16 * uSqNumCfInsts
,
1535 EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_shift
,
1536 EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_mask
);
1537 SETfield(evergreen
->evergreen_config
.SQ_MS_FIFO_SIZES
.u32All
, 0x4,
1538 EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_shift
,
1539 EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_mask
);
1540 SETfield(evergreen
->evergreen_config
.SQ_MS_FIFO_SIZES
.u32All
, 0xE0,
1541 EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_shift
,
1542 EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_mask
);
1543 SETfield(evergreen
->evergreen_config
.SQ_MS_FIFO_SIZES
.u32All
, 0x8,
1544 EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_shift
,
1545 EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_mask
);
1547 if(bVC_ENABLE
== GL_TRUE
)
1549 SETbit(evergreen
->evergreen_config
.SQ_CONFIG
.u32All
,
1550 EG_SQ_CONFIG__VC_ENABLE_bit
);
1554 CLEARbit(evergreen
->evergreen_config
.SQ_CONFIG
.u32All
,
1555 EG_SQ_CONFIG__VC_ENABLE_bit
);
1557 SETbit(evergreen
->evergreen_config
.SQ_CONFIG
.u32All
,
1558 EG_SQ_CONFIG__EXPORT_SRC_C_bit
);
1559 SETfield(evergreen
->evergreen_config
.SQ_CONFIG
.u32All
, 0,
1560 EG_SQ_CONFIG__PS_PRIO_shift
,
1561 EG_SQ_CONFIG__PS_PRIO_mask
);
1562 SETfield(evergreen
->evergreen_config
.SQ_CONFIG
.u32All
, 1,
1563 EG_SQ_CONFIG__VS_PRIO_shift
,
1564 EG_SQ_CONFIG__VS_PRIO_mask
);
1565 SETfield(evergreen
->evergreen_config
.SQ_CONFIG
.u32All
, 2,
1566 EG_SQ_CONFIG__GS_PRIO_shift
,
1567 EG_SQ_CONFIG__GS_PRIO_mask
);
1568 SETfield(evergreen
->evergreen_config
.SQ_CONFIG
.u32All
, 3,
1569 EG_SQ_CONFIG__ES_PRIO_shift
,
1570 EG_SQ_CONFIG__ES_PRIO_mask
);
1572 NUM_CLAUSE_TEMP_GPRS
= 4;
1573 NUM_PS_GPRS
= ((uMaxGPRs
-(4*2))*12/32); // 93
1574 NUM_VS_GPRS
= ((uMaxGPRs
-(4*2))*6/32); // 46
1575 NUM_GS_GPRS
= ((uMaxGPRs
-(4*2))*4/32); // 31
1576 NUM_ES_GPRS
= ((uMaxGPRs
-(4*2))*4/32); // 31
1577 NUM_HS_GPRS
= ((uMaxGPRs
-(4*2))*3/32); // 23
1578 NUM_LS_GPRS
= ((uMaxGPRs
-(4*2))*3/32); // 23
1580 evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1581 evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1582 evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_3
.u32All
= 0;
1584 SETfield(evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, NUM_PS_GPRS
,
1585 NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1586 SETfield(evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, NUM_VS_GPRS
,
1587 NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1588 SETfield(evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, NUM_CLAUSE_TEMP_GPRS
,
1589 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1590 SETfield(evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, NUM_GS_GPRS
,
1591 NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1592 SETfield(evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, NUM_ES_GPRS
,
1593 NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1594 SETfield(evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_3
.u32All
, NUM_HS_GPRS
,
1595 NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1596 SETfield(evergreen
->evergreen_config
.SQ_GPR_RESOURCE_MGMT_3
.u32All
, NUM_LS_GPRS
,
1597 NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1599 uOtherThreadCount
= (((uMaxThreads
-uPSThreadCount
)/6)/8)*8;
1600 evergreen
->evergreen_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1601 evergreen
->evergreen_config
.SQ_THREAD_RESOURCE_MGMT_2
.u32All
= 0;
1602 SETfield(evergreen
->evergreen_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, uPSThreadCount
,
1603 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1604 SETfield(evergreen
->evergreen_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, uOtherThreadCount
,
1605 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1606 SETfield(evergreen
->evergreen_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, uOtherThreadCount
,
1607 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1608 SETfield(evergreen
->evergreen_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, uOtherThreadCount
,
1609 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1610 SETfield(evergreen
->evergreen_config
.SQ_THREAD_RESOURCE_MGMT_2
.u32All
, uOtherThreadCount
,
1611 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1612 SETfield(evergreen
->evergreen_config
.SQ_THREAD_RESOURCE_MGMT_2
.u32All
, uOtherThreadCount
,
1613 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1615 uMaxStackEntries
= ((uMaxStackEntries
*1)/6);
1616 evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1617 evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1618 evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_3
.u32All
= 0;
1619 SETfield(evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, uMaxStackEntries
,
1620 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1621 SETfield(evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, uMaxStackEntries
,
1622 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1623 SETfield(evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, uMaxStackEntries
,
1624 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1625 SETfield(evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, uMaxStackEntries
,
1626 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1627 SETfield(evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_3
.u32All
, uMaxStackEntries
,
1628 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1629 SETfield(evergreen
->evergreen_config
.SQ_STACK_RESOURCE_MGMT_3
.u32All
, uMaxStackEntries
,
1630 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1632 evergreen
->evergreen_config
.PA_SC_FORCE_EOV_MAX_CNTS
.u32All
= 0;
1633 SETfield(evergreen
->evergreen_config
.PA_SC_FORCE_EOV_MAX_CNTS
.u32All
, 4095,
1634 EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_shift
,
1635 EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_mask
);
1636 SETfield(evergreen
->evergreen_config
.PA_SC_FORCE_EOV_MAX_CNTS
.u32All
, 255,
1637 EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_shift
,
1638 EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_mask
);
1640 evergreen
->evergreen_config
.VGT_CACHE_INVALIDATION
.u32All
= 0;
1641 SETfield(evergreen
->evergreen_config
.VGT_CACHE_INVALIDATION
.u32All
, 2,
1642 EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_shift
,
1643 EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_mask
);
1645 evergreen
->evergreen_config
.VGT_GS_VERTEX_REUSE
.u32All
= 0;
1646 SETfield(evergreen
->evergreen_config
.VGT_GS_VERTEX_REUSE
.u32All
, 16,
1650 evergreen
->evergreen_config
.PA_SC_LINE_STIPPLE_STATE
.u32All
= 0;
1652 evergreen
->evergreen_config
.PA_CL_ENHANCE
.u32All
= 0;
1653 SETbit(evergreen
->evergreen_config
.PA_CL_ENHANCE
.u32All
,
1654 CLIP_VTX_REORDER_ENA_bit
);
1655 SETfield(evergreen
->evergreen_config
.PA_CL_ENHANCE
.u32All
, 3,
1660 void evergreenInitState(struct gl_context
* ctx
) //diff
1662 context_t
*context
= R700_CONTEXT(ctx
);
1663 EVERGREEN_CHIP_CONTEXT
*evergreen
= GET_EVERGREEN_CHIP(context
);
1667 //calloc should have done this
1668 memset(evergreen
, 0, sizeof(EVERGREEN_CHIP_CONTEXT
));
1670 // Disable window clipping and offset:
1671 SETfield(evergreen
->PA_SC_WINDOW_OFFSET
.u32All
, 0,
1672 EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_shift
, EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_mask
);
1673 SETfield(evergreen
->PA_SC_WINDOW_OFFSET
.u32All
, 0,
1674 EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_shift
, EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_mask
);
1676 SETbit(evergreen
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1678 evergreen
->PA_SC_CLIPRECT_RULE
.u32All
= 0x0000FFFF;
1680 evergreen
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1682 // Set up Z min/max:
1683 evergreen
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.f32All
= 0.0;
1684 evergreen
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.f32All
= 1.0;
1686 SETfield(evergreen
->CB_TARGET_MASK
.u32All
, 0xF, TARGET0_ENABLE_shift
, TARGET0_ENABLE_mask
);
1687 SETfield(evergreen
->CB_SHADER_MASK
.u32All
, 0xF, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
1689 SETfield(evergreen
->SPI_BARYC_CNTL
.u32All
, 1,
1690 EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_shift
,
1691 EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_mask
);
1692 SETfield(evergreen
->SPI_BARYC_CNTL
.u32All
, 1,
1693 EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_shift
,
1694 EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_mask
);
1696 // Turn off vgt reuse:
1697 evergreen
->VGT_REUSE_OFF
.u32All
= 0;
1698 SETbit(evergreen
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1700 // Specify offsetting and clamp values for vertices:
1701 evergreen
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1702 evergreen
->VGT_MIN_VTX_INDX
.u32All
= 0;
1703 evergreen
->VGT_INDX_OFFSET
.u32All
= 0;
1705 evergreen
->VGT_DMA_NUM_INSTANCES
.u32All
= 1;
1707 // Do not alpha blend:
1708 SETfield(evergreen
->SX_ALPHA_TEST_CONTROL
.u32All
, REF_NEVER
,
1709 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
1710 CLEARbit(evergreen
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
1712 evergreen
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1713 evergreen
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1715 evergreen
->SPI_PS_INPUT_CNTL
[0].u32All
= 0x00000800;
1716 evergreen
->SPI_PS_INPUT_CNTL
[1].u32All
= 0x00000801;
1717 evergreen
->SPI_PS_INPUT_CNTL
[2].u32All
= 0x00000802;
1720 // Depth buffer currently disabled:
1721 evergreen
->DB_DEPTH_CONTROL
.u32All
= 0;
1722 SETbit(evergreen
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
1723 SETfield(evergreen
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
1724 ZFUNC_shift
, ZFUNC_mask
);
1726 evergreen
->DB_Z_READ_BASE
.u32All
= 0;
1727 evergreen
->DB_Z_WRITE_BASE
.u32All
= 0;
1729 evergreen
->DB_DEPTH_CLEAR
.f32All
= 1.0;
1731 evergreen
->DB_DEPTH_VIEW
.u32All
= 0;
1733 evergreen
->DB_SHADER_CONTROL
.u32All
= 0;
1734 SETbit(evergreen
->DB_SHADER_CONTROL
.u32All
, EG_DB_SHADER_CONTROL__DUAL_EXPORT_ENABLE_bit
);
1736 evergreen
->DB_Z_INFO
.u32All
= 0;
1737 SETfield(evergreen
->DB_Z_INFO
.u32All
, ARRAY_1D_TILED_THIN1
,
1738 EG_DB_Z_INFO__ARRAY_MODE_shift
, EG_DB_Z_INFO__ARRAY_MODE_mask
);
1739 SETfield(evergreen
->DB_Z_INFO
.u32All
, EG_Z_24
,
1740 EG_DB_Z_INFO__FORMAT_shift
, EG_DB_Z_INFO__FORMAT_mask
);
1741 SETfield(evergreen
->DB_Z_INFO
.u32All
, EG_ADDR_SURF_TILE_SPLIT_256B
,
1742 EG_DB_Z_INFO__TILE_SPLIT_shift
, EG_DB_Z_INFO__TILE_SPLIT_mask
);
1743 SETfield(evergreen
->DB_Z_INFO
.u32All
, EG_ADDR_SURF_8_BANK
,
1744 EG_DB_Z_INFO__NUM_BANKS_shift
, EG_DB_Z_INFO__NUM_BANKS_mask
);
1745 SETfield(evergreen
->DB_Z_INFO
.u32All
, EG_ADDR_SURF_BANK_WIDTH_1
,
1746 EG_DB_Z_INFO__BANK_WIDTH_shift
, EG_DB_Z_INFO__BANK_WIDTH_mask
);
1747 SETfield(evergreen
->DB_Z_INFO
.u32All
, EG_ADDR_SURF_BANK_HEIGHT_1
,
1748 EG_DB_Z_INFO__BANK_HEIGHT_shift
, EG_DB_Z_INFO__BANK_HEIGHT_mask
);
1750 evergreen
->DB_STENCIL_INFO
.u32All
= 0;
1751 CLEARbit(evergreen
->DB_STENCIL_INFO
.u32All
, EG_DB_STENCIL_INFO__FORMAT_bit
);
1752 SETfield(evergreen
->DB_STENCIL_INFO
.u32All
, 0,
1753 EG_DB_STENCIL_INFO__TILE_SPLIT_shift
, EG_DB_STENCIL_INFO__TILE_SPLIT_mask
);
1755 evergreen
->DB_RENDER_CONTROL
.u32All
= 0;
1757 evergreen
->DB_RENDER_OVERRIDE
.u32All
= 0;
1758 SETfield(evergreen
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
1759 SETfield(evergreen
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
1760 SETfield(evergreen
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
1763 evergreenEnable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1764 evergreenStencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1765 evergreenStencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1766 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1767 evergreenStencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1768 ctx
->Stencil
.ZFailFunc
[0],
1769 ctx
->Stencil
.ZPassFunc
[0]);
1771 // Disable ROP3 modes by setting src to dst copy:
1772 SETfield(evergreen
->CB_COLOR_CONTROL
.u32All
, 0xCC,
1773 EG_CB_COLOR_CONTROL__ROP3_shift
,
1774 EG_CB_COLOR_CONTROL__ROP3_mask
);
1775 SETfield(evergreen
->CB_COLOR_CONTROL
.u32All
, EG_CB_NORMAL
,
1776 EG_CB_COLOR_CONTROL__MODE_shift
,
1777 EG_CB_COLOR_CONTROL__MODE_mask
);
1779 SETfield(evergreen
->CB_BLEND0_CONTROL
.u32All
,
1780 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
1782 SETfield(evergreen
->CB_BLEND0_CONTROL
.u32All
,
1783 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
1785 //evergreen->PA_CL_CLIP_CNTL.CLIP_DISABLE = 1;
1787 SETbit(evergreen
->PA_CL_CLIP_CNTL
.u32All
, DX_LINEAR_ATTR_CLIP_ENA_bit
);
1789 // Set up the culling control register:
1790 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, 2,
1791 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
); // draw using triangles
1792 SETfield(evergreen
->PA_SU_SC_MODE_CNTL
.u32All
, 2,
1793 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
); // draw using triangles
1795 // Do scale XY or X by 1/W0. eg:
1796 evergreen
->bEnablePerspective
= GL_TRUE
;
1798 CLEARbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1799 CLEARbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1800 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1802 // Enable viewport scaling for all three axis:
1803 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1804 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1805 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1806 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1807 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1808 SETbit(evergreen
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1810 // Set up point sizes and min/max values:
1811 SETfield(evergreen
->PA_SU_POINT_SIZE
.u32All
, 0x8,
1812 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
1813 SETfield(evergreen
->PA_SU_POINT_SIZE
.u32All
, 0x8,
1814 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
1815 CLEARfield(evergreen
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1816 SETfield(evergreen
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1817 SETfield(evergreen
->PA_SU_LINE_CNTL
.u32All
,0x8,
1818 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1820 // Set up line control:
1821 evergreen
->PA_SC_LINE_CNTL
.u32All
= 0;
1822 CLEARbit(evergreen
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1823 SETbit(evergreen
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1825 // Set up vertex control:
1826 evergreen
->PA_SU_VTX_CNTL
.u32All
= 0;
1827 CLEARfield(evergreen
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1828 SETbit(evergreen
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1829 SETfield(evergreen
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1830 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1832 // to 1.0 = no guard band:
1833 evergreen
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; // 1.0
1834 evergreen
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000; // 1.0
1835 evergreen
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000; // 1.0
1836 evergreen
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000; // 1.0
1838 // Diable color compares:
1839 SETfield(evergreen
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1840 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1841 SETfield(evergreen
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1842 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1843 SETfield(evergreen
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1844 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1847 evergreen
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1849 // Put a compare color in for error checking:
1850 evergreen
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1852 // Set up color compare mask:
1853 evergreen
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1855 // Enable all samples for multi-sample anti-aliasing:
1856 evergreen
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1858 evergreen
->PA_SC_AA_CONFIG
.u32All
= 0;
1860 SETfield(evergreen
->VGT_OUT_DEALLOC_CNTL
.u32All
, 16,
1861 DEALLOC_DIST_shift
, DEALLOC_DIST_mask
);
1862 SETfield(evergreen
->VGT_VERTEX_REUSE_BLOCK_CNTL
.u32All
, 14,
1863 VTX_REUSE_DEPTH_shift
, VTX_REUSE_DEPTH_mask
);
1865 evergreen
->SX_MISC
.u32All
= 0;
1867 SETfield(evergreen
->render_target
[id
].CB_COLOR0_INFO
.u32All
, 1,
1868 EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift
, EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask
);
1869 SETbit(evergreen
->render_target
[id
].CB_COLOR0_INFO
.u32All
, EG_CB_COLOR0_INFO__BLEND_CLAMP_bit
);
1870 SETfield(evergreen
->render_target
[id
].CB_COLOR0_INFO
.u32All
, 0,
1871 EG_CB_COLOR0_INFO__NUMBER_TYPE_shift
, EG_CB_COLOR0_INFO__NUMBER_TYPE_mask
);
1873 SETfield(evergreen
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_STD
,
1874 EG_CB_COLOR0_INFO__COMP_SWAP_shift
, EG_CB_COLOR0_INFO__COMP_SWAP_mask
);
1876 evergreen
->render_target
[id
].CB_COLOR0_VIEW
.u32All
= 0;
1877 evergreen
->render_target
[id
].CB_COLOR0_CMASK
.u32All
= 0;
1878 evergreen
->render_target
[id
].CB_COLOR0_FMASK
.u32All
= 0;
1879 evergreen
->render_target
[id
].CB_COLOR0_FMASK_SLICE
.u32All
= 0;
1881 evergreenInitSQConfig(ctx
);
1883 context
->radeon
.hw
.all_dirty
= GL_TRUE
;
1886 void evergreenInitStateFuncs(radeonContextPtr radeon
, struct dd_function_table
*functions
)
1888 functions
->UpdateState
= evergreenInvalidateState
;
1889 functions
->AlphaFunc
= evergreenAlphaFunc
;
1890 functions
->BlendColor
= evergreenBlendColor
;
1891 functions
->BlendEquationSeparate
= evergreenBlendEquationSeparate
;
1892 functions
->BlendFuncSeparate
= evergreenBlendFuncSeparate
;
1893 functions
->Enable
= evergreenEnable
;
1894 functions
->ColorMask
= evergreenColorMask
;
1895 functions
->DepthFunc
= evergreenDepthFunc
;
1896 functions
->DepthMask
= evergreenDepthMask
;
1897 functions
->CullFace
= evergreenCullFace
;
1898 functions
->Fogfv
= evergreenFogfv
;
1899 functions
->FrontFace
= evergreenFrontFace
;
1900 functions
->ShadeModel
= evergreenShadeModel
;
1901 functions
->LogicOpcode
= evergreenLogicOpcode
;
1903 /* ARB_point_parameters */
1904 functions
->PointParameterfv
= evergreenPointParameter
;
1906 /* Stencil related */
1907 functions
->StencilFuncSeparate
= evergreenStencilFuncSeparate
;
1908 functions
->StencilMaskSeparate
= evergreenStencilMaskSeparate
;
1909 functions
->StencilOpSeparate
= evergreenStencilOpSeparate
;
1911 /* Viewport related */
1912 functions
->Viewport
= evergreenViewport
;
1913 functions
->DepthRange
= evergreenDepthRange
;
1914 functions
->PointSize
= evergreenPointSize
;
1915 functions
->LineWidth
= evergreenLineWidth
;
1916 functions
->LineStipple
= evergreenLineStipple
;
1918 functions
->PolygonOffset
= evergreenPolygonOffset
;
1919 functions
->PolygonMode
= evergreenPolygonMode
;
1921 functions
->RenderMode
= evergreenRenderMode
;
1923 functions
->ClipPlane
= evergreenClipPlane
;
1925 functions
->Scissor
= radeonScissor
;
1927 functions
->DrawBuffer
= radeonDrawBuffer
;
1928 functions
->ReadBuffer
= radeonReadBuffer
;
1930 if (radeon
->radeonScreen
->kernel_mm
) {
1931 functions
->CopyPixels
= _mesa_meta_CopyPixels
;
1932 functions
->DrawPixels
= _mesa_meta_DrawPixels
;
1933 functions
->ReadPixels
= radeonReadPixels
;