src/mesa/drivers/dri/r600/r600_blit.c

   1 /*
   2  * Copyright (C) 2009 Advanced Micro Devices, Inc.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r600_context.h"
  30
  31 #include "r600_blit.h"
  32 #include "r600_blit_shaders.h"
  33 #include "r600_cmdbuf.h"
  34
  35 static inline void
  36 set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
  37                   int pitch, int w, int h, intptr_t dst_offset)
  38 {
  39     uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
  40     int nPitchInPixel, id = 0;
  41     uint32_t comp_swap, format, bpp = _mesa_get_format_bytes(mesa_format);
  42     BATCH_LOCALS(&context->radeon);
  43
  44     cb_color0_base = dst_offset / 256;
  45
  46     nPitchInPixel = pitch/bpp;
  47     SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
  48              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
  49     SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
  50              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
  51
  52     SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
  53     SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
  54              CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
  55
  56     SETbit(cb_color0_info, BLEND_BYPASS_bit);
  57
  58     switch(mesa_format) {
  59     case MESA_FORMAT_RGBA8888:
  60             format = COLOR_8_8_8_8;
  61             comp_swap = SWAP_STD_REV;
  62             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  63             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  64             break;
  65     case MESA_FORMAT_SIGNED_RGBA8888:
  66             format = COLOR_8_8_8_8;
  67             comp_swap = SWAP_STD_REV;
  68             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  69             SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  70             break;
  71     case MESA_FORMAT_RGBA8888_REV:
  72             format = COLOR_8_8_8_8;
  73             comp_swap = SWAP_STD;
  74             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  75             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  76             break;
  77     case MESA_FORMAT_SIGNED_RGBA8888_REV:
  78             format = COLOR_8_8_8_8;
  79             comp_swap = SWAP_STD;
  80             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  81             SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  82             break;
  83     case MESA_FORMAT_ARGB8888:
  84     case MESA_FORMAT_XRGB8888:
  85             format = COLOR_8_8_8_8;
  86             comp_swap = SWAP_ALT;
  87             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  88             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  89             break;
  90     case MESA_FORMAT_ARGB8888_REV:
  91     case MESA_FORMAT_XRGB8888_REV:
  92             format = COLOR_8_8_8_8;
  93             comp_swap = SWAP_ALT_REV;
  94             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  95             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  96             break;
  97     case MESA_FORMAT_RGB565:
  98             format = COLOR_5_6_5;
  99             comp_swap = SWAP_STD_REV;
 100             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 101             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 102             break;
 103     case MESA_FORMAT_RGB565_REV:
 104             format = COLOR_5_6_5;
 105             comp_swap = SWAP_STD;
 106             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 107             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 108             break;
 109     case MESA_FORMAT_ARGB4444:
 110             format = COLOR_4_4_4_4;
 111             comp_swap = SWAP_ALT;
 112             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 113             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 114             break;
 115     case MESA_FORMAT_ARGB4444_REV:
 116             format = COLOR_4_4_4_4;
 117             comp_swap = SWAP_ALT_REV;
 118             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 119             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 120             break;
 121     case MESA_FORMAT_ARGB1555:
 122             format = COLOR_1_5_5_5;
 123             comp_swap = SWAP_ALT;
 124             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 125             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 126             break;
 127     case MESA_FORMAT_ARGB1555_REV:
 128             format = COLOR_1_5_5_5;
 129             comp_swap = SWAP_ALT_REV;
 130             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 131             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 132             break;
 133     case MESA_FORMAT_AL88:
 134             format = COLOR_8_8;
 135             comp_swap = SWAP_STD;
 136             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 137             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 138             break;
 139     case MESA_FORMAT_AL88_REV:
 140             format = COLOR_8_8;
 141             comp_swap = SWAP_STD_REV;
 142             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 143             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 144             break;
 145     case MESA_FORMAT_RGB332:
 146             format = COLOR_3_3_2;
 147             comp_swap = SWAP_STD_REV;
 148             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 149             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 150             break;
 151     case MESA_FORMAT_A8:
 152             format = COLOR_8;
 153             comp_swap = SWAP_ALT_REV;
 154             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 155             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 156             break;
 157     case MESA_FORMAT_I8:
 158     case MESA_FORMAT_CI8:
 159             format = COLOR_8;
 160             comp_swap = SWAP_STD;
 161             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 162             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 163             break;
 164     case MESA_FORMAT_L8:
 165             format = COLOR_8;
 166             comp_swap = SWAP_ALT;
 167             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 168             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 169             break;
 170     case MESA_FORMAT_RGBA_FLOAT32:
 171             format = COLOR_32_32_32_32_FLOAT;
 172             comp_swap = SWAP_STD_REV;
 173             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 174             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 175             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 176             break;
 177     case MESA_FORMAT_RGBA_FLOAT16:
 178             format = COLOR_16_16_16_16_FLOAT;
 179             comp_swap = SWAP_STD_REV;
 180             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 181             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 182             break;
 183     case MESA_FORMAT_ALPHA_FLOAT32:
 184             format = COLOR_32_FLOAT;
 185             comp_swap = SWAP_ALT_REV;
 186             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 187             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 188             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 189             break;
 190     case MESA_FORMAT_ALPHA_FLOAT16:
 191             format = COLOR_16_FLOAT;
 192             comp_swap = SWAP_ALT_REV;
 193             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 194             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 195             break;
 196     case MESA_FORMAT_LUMINANCE_FLOAT32:
 197             format = COLOR_32_FLOAT;
 198             comp_swap = SWAP_ALT;
 199             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 200             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 201             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 202             break;
 203     case MESA_FORMAT_LUMINANCE_FLOAT16:
 204             format = COLOR_16_FLOAT;
 205             comp_swap = SWAP_ALT;
 206             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 207             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 208             break;
 209     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 210             format = COLOR_32_32_FLOAT;
 211             comp_swap = SWAP_ALT_REV;
 212             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 213             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 214             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 215             break;
 216     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 217             format = COLOR_16_16_FLOAT;
 218             comp_swap = SWAP_ALT_REV;
 219             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 220             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 221             break;
 222     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 223             format = COLOR_32_FLOAT;
 224             comp_swap = SWAP_STD;
 225             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 226             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 227             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 228             break;
 229     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 230             format = COLOR_16_FLOAT;
 231             comp_swap = SWAP_STD;
 232             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 233             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 234             break;
 235     case MESA_FORMAT_X8_Z24:
 236     case MESA_FORMAT_S8_Z24:
 237             format = COLOR_8_24;
 238             comp_swap = SWAP_STD;
 239             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 240                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 241             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 242             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 243             break;
 244     case MESA_FORMAT_Z24_S8:
 245             format = COLOR_24_8;
 246             comp_swap = SWAP_STD;
 247             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 248                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 249             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 250             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 251             break;
 252     case MESA_FORMAT_Z16:
 253             format = COLOR_16;
 254             comp_swap = SWAP_STD;
 255             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 256                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 257             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 258             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 259             break;
 260     case MESA_FORMAT_Z32:
 261             format = COLOR_32;
 262             comp_swap = SWAP_STD;
 263             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 264                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 265             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 266             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 267             break;
 268     case MESA_FORMAT_SRGBA8:
 269             format = COLOR_8_8_8_8;
 270             comp_swap = SWAP_STD_REV;
 271             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 272             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 273             break;
 274     case MESA_FORMAT_SLA8:
 275             format = COLOR_8_8;
 276             comp_swap = SWAP_ALT_REV;
 277             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 278             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 279             break;
 280     case MESA_FORMAT_SL8:
 281             format = COLOR_8;
 282             comp_swap = SWAP_ALT_REV;
 283             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 284             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 285             break;
 286     default:
 287             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
 288             assert("Invalid format for US output\n");
 289             return;
 290     }
 291
 292     SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
 293              CB_COLOR0_INFO__FORMAT_mask);
 294     SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
 295
 296     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 297     R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
 298     R600_OUT_BATCH(cb_color0_base);
 299     R600_OUT_BATCH_RELOC(0,
 300                          bo,
 301                          0,
 302                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 303     END_BATCH();
 304
 305     if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 306         (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 307             BEGIN_BATCH_NO_AUTOSTATE(2);
 308             R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
 309             R600_OUT_BATCH((2 << id));
 310             END_BATCH();
 311     }
 312
 313     BEGIN_BATCH_NO_AUTOSTATE(18);
 314     R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
 315     R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
 316     R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
 317     R600_OUT_BATCH_REGVAL(CB_COLOR0_TILE + (4 * id), 0);
 318     R600_OUT_BATCH_REGVAL(CB_COLOR0_FRAG + (4 * id), 0);
 319     R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
 320     END_BATCH();
 321
 322     COMMIT_BATCH();
 323
 324 }
 325
 326 static inline void load_shaders(GLcontext * ctx)
 327 {
 328
 329     radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
 330     context_t *context = R700_CONTEXT(ctx);
 331     int i, size;
 332     uint32_t *shader;
 333
 334     if (context->blit_bo_loaded == 1)
 335         return;
 336
 337     size = 4096;
 338     context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
 339                                       size, 256, RADEON_GEM_DOMAIN_GTT, 0);
 340     radeon_bo_map(context->blit_bo, 1);
 341     shader = context->blit_bo->ptr;
 342
 343     for(i=0; i<sizeof(r6xx_vs)/4; i++) {
 344         shader[128+i] = r6xx_vs[i];
 345     }
 346     for(i=0; i<sizeof(r6xx_ps)/4; i++) {
 347         shader[256+i] = r6xx_ps[i];
 348     }
 349
 350     radeon_bo_unmap(context->blit_bo);
 351     context->blit_bo_loaded = 1;
 352
 353 }
 354
 355 static inline void
 356 set_shaders(context_t *context)
 357 {
 358     struct radeon_bo * pbo = context->blit_bo;
 359     BATCH_LOCALS(&context->radeon);
 360
 361     uint32_t sq_pgm_start_fs = (512 >> 8);
 362     uint32_t sq_pgm_resources_fs = 0;
 363     uint32_t sq_pgm_cf_offset_fs = 0;
 364
 365     uint32_t sq_pgm_start_vs = (512 >> 8);
 366     uint32_t sq_pgm_resources_vs = (1 << NUM_GPRS_shift);
 367     uint32_t sq_pgm_cf_offset_vs = 0;
 368
 369     uint32_t sq_pgm_start_ps = (1024 >> 8);
 370     uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
 371     uint32_t sq_pgm_cf_offset_ps = 0;
 372     uint32_t sq_pgm_exports_ps = (1 << 1);
 373
 374     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 375
 376     /* FS */
 377     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 378     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
 379     R600_OUT_BATCH(sq_pgm_start_fs);
 380     R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
 381                          pbo,
 382                          sq_pgm_start_fs,
 383                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 384     END_BATCH();
 385
 386     BEGIN_BATCH_NO_AUTOSTATE(6);
 387     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
 388     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, sq_pgm_cf_offset_fs);
 389     END_BATCH();
 390
 391     /* VS */
 392     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 393     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
 394     R600_OUT_BATCH(sq_pgm_start_vs);
 395     R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
 396                          pbo,
 397                          sq_pgm_start_vs,
 398                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 399     END_BATCH();
 400
 401     BEGIN_BATCH_NO_AUTOSTATE(6);
 402     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, sq_pgm_resources_vs);
 403     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, sq_pgm_cf_offset_vs);
 404     END_BATCH();
 405
 406     /* PS */
 407     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 408     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
 409     R600_OUT_BATCH(sq_pgm_start_ps);
 410     R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
 411                          pbo,
 412                          sq_pgm_start_ps,
 413                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 414     END_BATCH();
 415
 416     BEGIN_BATCH_NO_AUTOSTATE(9);
 417     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, sq_pgm_resources_ps);
 418     R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, sq_pgm_exports_ps);
 419     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, sq_pgm_cf_offset_ps);
 420     END_BATCH();
 421
 422     BEGIN_BATCH_NO_AUTOSTATE(18);
 423     R600_OUT_BATCH_REGVAL(SPI_VS_OUT_CONFIG, 0); //EXPORT_COUNT is - 1
 424     R600_OUT_BATCH_REGVAL(SPI_VS_OUT_ID_0, 0);
 425     R600_OUT_BATCH_REGVAL(SPI_PS_INPUT_CNTL_0, SEL_CENTROID_bit);
 426     R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_0, (1 << NUM_INTERP_shift));
 427     R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_1, 0);
 428     R600_OUT_BATCH_REGVAL(SPI_INTERP_CONTROL_0, 0);
 429     END_BATCH();
 430
 431     COMMIT_BATCH();
 432
 433 }
 434
 435 static inline void
 436 set_vtx_resource(context_t *context)
 437 {
 438     struct radeon_bo *bo = context->blit_bo;
 439     BATCH_LOCALS(&context->radeon);
 440
 441     BEGIN_BATCH_NO_AUTOSTATE(6);
 442     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 443     R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
 444     R600_OUT_BATCH(0);
 445
 446     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 447     R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
 448     R600_OUT_BATCH(0);
 449     END_BATCH();
 450     COMMIT_BATCH();
 451
 452     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 453         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 454         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
 455         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
 456         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
 457             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
 458     else
 459             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
 460
 461     BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 462
 463     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 464     R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
 465     R600_OUT_BATCH(0);
 466     R600_OUT_BATCH(48 - 1);
 467     R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
 468     R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
 469     R600_OUT_BATCH(0);
 470     R600_OUT_BATCH(0);
 471     R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
 472     R600_OUT_BATCH_RELOC(SQ_VTX_CONSTANT_WORD0_0,
 473                          bo,
 474                          SQ_VTX_CONSTANT_WORD0_0,
 475                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 476     END_BATCH();
 477     COMMIT_BATCH();
 478
 479 }
 480
 481 static inline void
 482 set_tex_resource(context_t * context,
 483                  gl_format mesa_format, struct radeon_bo *bo, int w, int h,
 484                  int pitch, intptr_t src_offset)
 485 {
 486     uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource6;
 487     int bpp = _mesa_get_format_bytes(mesa_format);
 488     int TexelPitch = pitch/bpp;
 489
 490     sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource6 = 0;
 491     BATCH_LOCALS(&context->radeon);
 492
 493     SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
 494     SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
 495                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 496                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 497
 498     switch (mesa_format) {
 499     case MESA_FORMAT_RGBA8888:
 500     case MESA_FORMAT_SIGNED_RGBA8888:
 501             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 502                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 503
 504             SETfield(sq_tex_resource4, SQ_SEL_W,
 505                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 506             SETfield(sq_tex_resource4, SQ_SEL_Z,
 507                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 508             SETfield(sq_tex_resource4, SQ_SEL_Y,
 509                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 510             SETfield(sq_tex_resource4, SQ_SEL_X,
 511                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 512             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
 513                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 514                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 515                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 516                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 517                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 518                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 519                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 520                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 521             }
 522             break;
 523     case MESA_FORMAT_RGBA8888_REV:
 524     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 525             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 526                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 527
 528             SETfield(sq_tex_resource4, SQ_SEL_X,
 529                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 530             SETfield(sq_tex_resource4, SQ_SEL_Y,
 531                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 532             SETfield(sq_tex_resource4, SQ_SEL_Z,
 533                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 534             SETfield(sq_tex_resource4, SQ_SEL_W,
 535                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 536             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
 537                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 538                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 539                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 540                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 541                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 542                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 543                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 544                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 545             }
 546             break;
 547     case MESA_FORMAT_ARGB8888:
 548             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 549                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 550
 551             SETfield(sq_tex_resource4, SQ_SEL_Z,
 552                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 553             SETfield(sq_tex_resource4, SQ_SEL_Y,
 554                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 555             SETfield(sq_tex_resource4, SQ_SEL_X,
 556                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 557             SETfield(sq_tex_resource4, SQ_SEL_W,
 558                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 559             break;
 560     case MESA_FORMAT_XRGB8888:
 561             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 562                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 563
 564             SETfield(sq_tex_resource4, SQ_SEL_Z,
 565                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 566             SETfield(sq_tex_resource4, SQ_SEL_Y,
 567                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 568             SETfield(sq_tex_resource4, SQ_SEL_X,
 569                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 570             SETfield(sq_tex_resource4, SQ_SEL_1,
 571                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 572             break;
 573     case MESA_FORMAT_ARGB8888_REV:
 574             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 575                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 576
 577             SETfield(sq_tex_resource4, SQ_SEL_Y,
 578                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 579             SETfield(sq_tex_resource4, SQ_SEL_Z,
 580                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 581             SETfield(sq_tex_resource4, SQ_SEL_W,
 582                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 583             SETfield(sq_tex_resource4, SQ_SEL_X,
 584                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 585             break;
 586     case MESA_FORMAT_XRGB8888_REV:
 587             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 588                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 589
 590             SETfield(sq_tex_resource4, SQ_SEL_1,
 591                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 592             SETfield(sq_tex_resource4, SQ_SEL_Z,
 593                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 594             SETfield(sq_tex_resource4, SQ_SEL_W,
 595                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 596             SETfield(sq_tex_resource4, SQ_SEL_X,
 597                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 598             break;
 599     case MESA_FORMAT_RGB565:
 600             SETfield(sq_tex_resource1, FMT_5_6_5,
 601                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 602
 603             SETfield(sq_tex_resource4, SQ_SEL_Z,
 604                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 605             SETfield(sq_tex_resource4, SQ_SEL_Y,
 606                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 607             SETfield(sq_tex_resource4, SQ_SEL_X,
 608                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 609             SETfield(sq_tex_resource4, SQ_SEL_1,
 610                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 611             break;
 612     case MESA_FORMAT_RGB565_REV:
 613             SETfield(sq_tex_resource1, FMT_5_6_5,
 614                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 615
 616             SETfield(sq_tex_resource4, SQ_SEL_X,
 617                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 618             SETfield(sq_tex_resource4, SQ_SEL_Y,
 619                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 620             SETfield(sq_tex_resource4, SQ_SEL_Z,
 621                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 622             SETfield(sq_tex_resource4, SQ_SEL_1,
 623                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 624             break;
 625     case MESA_FORMAT_ARGB4444:
 626             SETfield(sq_tex_resource1, FMT_4_4_4_4,
 627                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 628
 629             SETfield(sq_tex_resource4, SQ_SEL_Z,
 630                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 631             SETfield(sq_tex_resource4, SQ_SEL_Y,
 632                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 633             SETfield(sq_tex_resource4, SQ_SEL_X,
 634                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 635             SETfield(sq_tex_resource4, SQ_SEL_W,
 636                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 637             break;
 638     case MESA_FORMAT_ARGB4444_REV:
 639             SETfield(sq_tex_resource1, FMT_4_4_4_4,
 640                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 641
 642             SETfield(sq_tex_resource4, SQ_SEL_Y,
 643                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 644             SETfield(sq_tex_resource4, SQ_SEL_Z,
 645                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 646             SETfield(sq_tex_resource4, SQ_SEL_W,
 647                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 648             SETfield(sq_tex_resource4, SQ_SEL_X,
 649                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 650             break;
 651     case MESA_FORMAT_ARGB1555:
 652             SETfield(sq_tex_resource1, FMT_1_5_5_5,
 653                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 654
 655             SETfield(sq_tex_resource4, SQ_SEL_Z,
 656                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 657             SETfield(sq_tex_resource4, SQ_SEL_Y,
 658                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 659             SETfield(sq_tex_resource4, SQ_SEL_X,
 660                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 661             SETfield(sq_tex_resource4, SQ_SEL_W,
 662                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 663             break;
 664     case MESA_FORMAT_ARGB1555_REV:
 665             SETfield(sq_tex_resource1, FMT_1_5_5_5,
 666                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 667
 668             SETfield(sq_tex_resource4, SQ_SEL_Y,
 669                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 670             SETfield(sq_tex_resource4, SQ_SEL_Z,
 671                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 672             SETfield(sq_tex_resource4, SQ_SEL_W,
 673                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 674             SETfield(sq_tex_resource4, SQ_SEL_X,
 675                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 676             break;
 677     case MESA_FORMAT_AL88:
 678     case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
 679             SETfield(sq_tex_resource1, FMT_8_8,
 680                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 681
 682             SETfield(sq_tex_resource4, SQ_SEL_X,
 683                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 684             SETfield(sq_tex_resource4, SQ_SEL_X,
 685                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 686             SETfield(sq_tex_resource4, SQ_SEL_X,
 687                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 688             SETfield(sq_tex_resource4, SQ_SEL_Y,
 689                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 690             break;
 691     case MESA_FORMAT_RGB332:
 692             SETfield(sq_tex_resource1, FMT_3_3_2,
 693                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 694
 695             SETfield(sq_tex_resource4, SQ_SEL_Z,
 696                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 697             SETfield(sq_tex_resource4, SQ_SEL_Y,
 698                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 699             SETfield(sq_tex_resource4, SQ_SEL_X,
 700                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 701             SETfield(sq_tex_resource4, SQ_SEL_1,
 702                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 703             break;
 704     case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
 705             SETfield(sq_tex_resource1, FMT_8,
 706                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 707
 708             SETfield(sq_tex_resource4, SQ_SEL_0,
 709                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 710             SETfield(sq_tex_resource4, SQ_SEL_0,
 711                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 712             SETfield(sq_tex_resource4, SQ_SEL_0,
 713                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 714             SETfield(sq_tex_resource4, SQ_SEL_X,
 715                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 716             break;
 717     case MESA_FORMAT_L8: /* X, X, X, ONE */
 718             SETfield(sq_tex_resource1, FMT_8,
 719                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 720
 721             SETfield(sq_tex_resource4, SQ_SEL_X,
 722                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 723             SETfield(sq_tex_resource4, SQ_SEL_X,
 724                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 725             SETfield(sq_tex_resource4, SQ_SEL_X,
 726                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 727             SETfield(sq_tex_resource4, SQ_SEL_1,
 728                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 729             break;
 730     case MESA_FORMAT_I8: /* X, X, X, X */
 731     case MESA_FORMAT_CI8:
 732             SETfield(sq_tex_resource1, FMT_8,
 733                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 734
 735             SETfield(sq_tex_resource4, SQ_SEL_X,
 736                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 737             SETfield(sq_tex_resource4, SQ_SEL_X,
 738                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 739             SETfield(sq_tex_resource4, SQ_SEL_X,
 740                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 741             SETfield(sq_tex_resource4, SQ_SEL_X,
 742                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 743             break;
 744     case MESA_FORMAT_RGBA_FLOAT32:
 745             SETfield(sq_tex_resource1, FMT_32_32_32_32_FLOAT,
 746                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 747
 748             SETfield(sq_tex_resource4, SQ_SEL_X,
 749                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 750             SETfield(sq_tex_resource4, SQ_SEL_Y,
 751                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 752             SETfield(sq_tex_resource4, SQ_SEL_Z,
 753                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 754             SETfield(sq_tex_resource4, SQ_SEL_W,
 755                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 756             break;
 757     case MESA_FORMAT_RGBA_FLOAT16:
 758             SETfield(sq_tex_resource1, FMT_16_16_16_16_FLOAT,
 759                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 760
 761             SETfield(sq_tex_resource4, SQ_SEL_X,
 762                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 763             SETfield(sq_tex_resource4, SQ_SEL_Y,
 764                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 765             SETfield(sq_tex_resource4, SQ_SEL_Z,
 766                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 767             SETfield(sq_tex_resource4, SQ_SEL_W,
 768                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 769             break;
 770     case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
 771             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 772                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 773
 774             SETfield(sq_tex_resource4, SQ_SEL_0,
 775                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 776             SETfield(sq_tex_resource4, SQ_SEL_0,
 777                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 778             SETfield(sq_tex_resource4, SQ_SEL_0,
 779                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 780             SETfield(sq_tex_resource4, SQ_SEL_X,
 781                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 782             break;
 783     case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
 784             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 785                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 786
 787             SETfield(sq_tex_resource4, SQ_SEL_0,
 788                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 789             SETfield(sq_tex_resource4, SQ_SEL_0,
 790                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 791             SETfield(sq_tex_resource4, SQ_SEL_0,
 792                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 793             SETfield(sq_tex_resource4, SQ_SEL_X,
 794                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 795             break;
 796     case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
 797             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 798                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 799
 800             SETfield(sq_tex_resource4, SQ_SEL_X,
 801                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 802             SETfield(sq_tex_resource4, SQ_SEL_X,
 803                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 804             SETfield(sq_tex_resource4, SQ_SEL_X,
 805                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 806             SETfield(sq_tex_resource4, SQ_SEL_1,
 807                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 808             break;
 809     case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
 810             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 811                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 812
 813             SETfield(sq_tex_resource4, SQ_SEL_X,
 814                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 815             SETfield(sq_tex_resource4, SQ_SEL_X,
 816                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 817             SETfield(sq_tex_resource4, SQ_SEL_X,
 818                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 819             SETfield(sq_tex_resource4, SQ_SEL_1,
 820                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 821             break;
 822     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 823             SETfield(sq_tex_resource1, FMT_32_32_FLOAT,
 824                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 825
 826             SETfield(sq_tex_resource4, SQ_SEL_X,
 827                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 828             SETfield(sq_tex_resource4, SQ_SEL_X,
 829                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 830             SETfield(sq_tex_resource4, SQ_SEL_X,
 831                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 832             SETfield(sq_tex_resource4, SQ_SEL_Y,
 833                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 834             break;
 835     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 836             SETfield(sq_tex_resource1, FMT_16_16_FLOAT,
 837                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 838
 839             SETfield(sq_tex_resource4, SQ_SEL_X,
 840                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 841             SETfield(sq_tex_resource4, SQ_SEL_X,
 842                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 843             SETfield(sq_tex_resource4, SQ_SEL_X,
 844                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 845             SETfield(sq_tex_resource4, SQ_SEL_Y,
 846                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 847             break;
 848     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 849             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 850                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 851
 852             SETfield(sq_tex_resource4, SQ_SEL_X,
 853                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 854             SETfield(sq_tex_resource4, SQ_SEL_X,
 855                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 856             SETfield(sq_tex_resource4, SQ_SEL_X,
 857                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 858             SETfield(sq_tex_resource4, SQ_SEL_X,
 859                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 860             break;
 861     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 862             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 863                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 864
 865             SETfield(sq_tex_resource4, SQ_SEL_X,
 866                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 867             SETfield(sq_tex_resource4, SQ_SEL_X,
 868                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 869             SETfield(sq_tex_resource4, SQ_SEL_X,
 870                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 871             SETfield(sq_tex_resource4, SQ_SEL_X,
 872                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 873             break;
 874     case MESA_FORMAT_Z16:
 875             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 876             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 877                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 878                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 879             SETfield(sq_tex_resource1, FMT_16,
 880                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 881             SETfield(sq_tex_resource4, SQ_SEL_X,
 882                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 883             SETfield(sq_tex_resource4, SQ_SEL_X,
 884                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 885             SETfield(sq_tex_resource4, SQ_SEL_X,
 886                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 887             SETfield(sq_tex_resource4, SQ_SEL_X,
 888                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 889             break;
 890     case MESA_FORMAT_X8_Z24:
 891             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 892             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 893                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 894                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 895             SETfield(sq_tex_resource1, FMT_8_24,
 896                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 897             SETfield(sq_tex_resource4, SQ_SEL_X,
 898                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 899             SETfield(sq_tex_resource4, SQ_SEL_1,
 900                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 901             SETfield(sq_tex_resource4, SQ_SEL_0,
 902                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 903             SETfield(sq_tex_resource4, SQ_SEL_1,
 904                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 905             break;
 906     case MESA_FORMAT_S8_Z24:
 907             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 908             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 909                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 910                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 911             SETfield(sq_tex_resource1, FMT_8_24,
 912                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 913             SETfield(sq_tex_resource4, SQ_SEL_X,
 914                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 915             SETfield(sq_tex_resource4, SQ_SEL_Y,
 916                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 917             SETfield(sq_tex_resource4, SQ_SEL_0,
 918                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 919             SETfield(sq_tex_resource4, SQ_SEL_1,
 920                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 921             break;
 922     case MESA_FORMAT_Z24_S8:
 923             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 924             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 925                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 926                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 927             SETfield(sq_tex_resource1, FMT_24_8,
 928                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 929             SETfield(sq_tex_resource4, SQ_SEL_X,
 930                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 931             SETfield(sq_tex_resource4, SQ_SEL_Y,
 932                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 933             SETfield(sq_tex_resource4, SQ_SEL_0,
 934                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 935             SETfield(sq_tex_resource4, SQ_SEL_1,
 936                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 937             break;
 938     case MESA_FORMAT_Z32:
 939             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 940             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 941                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 942                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 943             SETfield(sq_tex_resource1, FMT_32,
 944                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 945             SETfield(sq_tex_resource4, SQ_SEL_X,
 946                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 947             SETfield(sq_tex_resource4, SQ_SEL_X,
 948                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 949             SETfield(sq_tex_resource4, SQ_SEL_X,
 950                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 951             SETfield(sq_tex_resource4, SQ_SEL_X,
 952                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 953             break;
 954     case MESA_FORMAT_S8:
 955             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 956             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 957                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 958                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 959             SETfield(sq_tex_resource1, FMT_8,
 960                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 961             SETfield(sq_tex_resource4, SQ_SEL_X,
 962                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 963             SETfield(sq_tex_resource4, SQ_SEL_X,
 964                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 965             SETfield(sq_tex_resource4, SQ_SEL_X,
 966                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 967             SETfield(sq_tex_resource4, SQ_SEL_X,
 968                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 969             break;
 970     case MESA_FORMAT_SRGBA8:
 971             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 972                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 973
 974             SETfield(sq_tex_resource4, SQ_SEL_W,
 975                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 976             SETfield(sq_tex_resource4, SQ_SEL_Z,
 977                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 978             SETfield(sq_tex_resource4, SQ_SEL_Y,
 979                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 980             SETfield(sq_tex_resource4, SQ_SEL_X,
 981                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 982             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
 983             break;
 984     case MESA_FORMAT_SLA8:
 985             SETfield(sq_tex_resource1, FMT_8_8,
 986                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 987
 988             SETfield(sq_tex_resource4, SQ_SEL_X,
 989                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 990             SETfield(sq_tex_resource4, SQ_SEL_X,
 991                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 992             SETfield(sq_tex_resource4, SQ_SEL_X,
 993                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 994             SETfield(sq_tex_resource4, SQ_SEL_Y,
 995                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 996             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
 997             break;
 998     case MESA_FORMAT_SL8: /* X, X, X, ONE */
 999             SETfield(sq_tex_resource1, FMT_8,
1000                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1001
1002             SETfield(sq_tex_resource4, SQ_SEL_X,
1003                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1004             SETfield(sq_tex_resource4, SQ_SEL_X,
1005                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1006             SETfield(sq_tex_resource4, SQ_SEL_X,
1007                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1008             SETfield(sq_tex_resource4, SQ_SEL_1,
1009                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1010             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1011             break;
1012     default:
1013             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
1014             assert("Invalid format for US output\n");
1015             return;
1016     };
1017
1018     SETfield(sq_tex_resource0, (TexelPitch/8)-1, PITCH_shift, PITCH_mask);
1019     SETfield(sq_tex_resource0, w - 1, TEX_WIDTH_shift, TEX_WIDTH_mask);
1020     SETfield(sq_tex_resource1, h - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask);
1021
1022     sq_tex_resource2 = src_offset / 256;
1023
1024     SETfield(sq_tex_resource6, SQ_TEX_VTX_VALID_TEXTURE,
1025              SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
1026              SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
1027
1028     r700SyncSurf(context, bo,
1029                  RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
1030                  0, TC_ACTION_ENA_bit);
1031
1032     BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
1033     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1034     R600_OUT_BATCH(0 * 7);
1035
1036     R600_OUT_BATCH(sq_tex_resource0);
1037     R600_OUT_BATCH(sq_tex_resource1);
1038     R600_OUT_BATCH(sq_tex_resource2);
1039     R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
1040     R600_OUT_BATCH(sq_tex_resource4);
1041     R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
1042     R600_OUT_BATCH(sq_tex_resource6);
1043     R600_OUT_BATCH_RELOC(0,
1044                      bo,
1045                      0,
1046                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1047     R600_OUT_BATCH_RELOC(0,
1048                      bo,
1049                      0,
1050                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1051     END_BATCH();
1052     COMMIT_BATCH();
1053 }
1054
1055 static inline void
1056 set_tex_sampler(context_t * context)
1057 {
1058     uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
1059     int i = 0;
1060
1061     SETbit(sq_tex_sampler_word2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
1062
1063     BATCH_LOCALS(&context->radeon);
1064
1065     BEGIN_BATCH_NO_AUTOSTATE(5);
1066     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
1067     R600_OUT_BATCH(i * 3);
1068     R600_OUT_BATCH(sq_tex_sampler_word0);
1069     R600_OUT_BATCH(sq_tex_sampler_word1);
1070     R600_OUT_BATCH(sq_tex_sampler_word2);
1071     END_BATCH();
1072
1073 }
1074
1075 static inline void
1076 set_scissors(context_t *context, int x1, int y1, int x2, int y2)
1077 {
1078     BATCH_LOCALS(&context->radeon);
1079
1080     BEGIN_BATCH_NO_AUTOSTATE(17);
1081     R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1082     R600_OUT_BATCH((x1 << 0) | (y1 << 16));
1083     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1084
1085     R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 3);
1086     R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1087     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
1088     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1089
1090     R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1091     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1092     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1093     END_BATCH();
1094
1095     /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1096     R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL, 2 );
1097     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1098     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1099     END_BATCH();
1100
1101     COMMIT_BATCH();
1102
1103 }
1104
1105 static inline void
1106 set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
1107             int w, int h, int src_h, unsigned flip_y)
1108 {
1109     float *vb;
1110     radeon_bo_map(context->blit_bo, 1);
1111     vb = context->blit_bo->ptr;
1112
1113     vb[0] = (float)(dst_x);
1114     vb[1] = (float)(dst_y);
1115     vb[2] = (float)(src_x);
1116     vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
1117
1118     vb[4] = (float)(dst_x);
1119     vb[5] = (float)(dst_y + h);
1120     vb[6] = (float)(src_x);
1121     vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1122
1123     vb[8] = (float)(dst_x + w);
1124     vb[9] = (float)(dst_y + h);
1125     vb[10] = (float)(src_x + w);
1126     vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1127
1128     radeon_bo_unmap(context->blit_bo);
1129
1130 }
1131
1132 static inline void
1133 draw_auto(context_t *context)
1134 {
1135     BATCH_LOCALS(&context->radeon);
1136     uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
1137
1138     SETfield(vgt_primitive_type, DI_PT_RECTLIST,
1139              VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
1140              VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
1141     SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
1142              INDEX_TYPE_mask);
1143     SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
1144              MAJOR_MODE_mask);
1145     SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
1146              SOURCE_SELECT_mask);
1147
1148     vgt_num_indices = 3;
1149
1150     BEGIN_BATCH_NO_AUTOSTATE(10);
1151     // prim
1152     R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
1153     R600_OUT_BATCH(vgt_primitive_type);
1154     // index type
1155     R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1156     R600_OUT_BATCH(vgt_index_type);
1157     // num instances
1158     R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1159     R600_OUT_BATCH(1);
1160     //
1161     R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1162     R600_OUT_BATCH(vgt_num_indices);
1163     R600_OUT_BATCH(vgt_draw_initiator);
1164
1165     END_BATCH();
1166     COMMIT_BATCH();
1167 }
1168
1169 static inline void
1170 set_default_state(context_t *context)
1171 {
1172     int ps_prio = 0;
1173     int vs_prio = 1;
1174     int gs_prio = 2;
1175     int es_prio = 3;
1176     int num_ps_gprs;
1177     int num_vs_gprs;
1178     int num_gs_gprs;
1179     int num_es_gprs;
1180     int num_temp_gprs;
1181     int num_ps_threads;
1182     int num_vs_threads;
1183     int num_gs_threads;
1184     int num_es_threads;
1185     int num_ps_stack_entries;
1186     int num_vs_stack_entries;
1187     int num_gs_stack_entries;
1188     int num_es_stack_entries;
1189     uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
1190     uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
1191     uint32_t ta_cntl_aux, db_watermarks, sq_dyn_gpr_cntl_ps_flush_req, db_debug;
1192     BATCH_LOCALS(&context->radeon);
1193
1194     switch (context->radeon.radeonScreen->chip_family) {
1195     case CHIP_FAMILY_R600:
1196             num_ps_gprs = 192;
1197             num_vs_gprs = 56;
1198             num_temp_gprs = 4;
1199             num_gs_gprs = 0;
1200             num_es_gprs = 0;
1201             num_ps_threads = 136;
1202             num_vs_threads = 48;
1203             num_gs_threads = 4;
1204             num_es_threads = 4;
1205             num_ps_stack_entries = 128;
1206             num_vs_stack_entries = 128;
1207             num_gs_stack_entries = 0;
1208             num_es_stack_entries = 0;
1209             break;
1210     case CHIP_FAMILY_RV630:
1211     case CHIP_FAMILY_RV635:
1212             num_ps_gprs = 84;
1213             num_vs_gprs = 36;
1214             num_temp_gprs = 4;
1215             num_gs_gprs = 0;
1216             num_es_gprs = 0;
1217             num_ps_threads = 144;
1218             num_vs_threads = 40;
1219             num_gs_threads = 4;
1220             num_es_threads = 4;
1221             num_ps_stack_entries = 40;
1222             num_vs_stack_entries = 40;
1223             num_gs_stack_entries = 32;
1224             num_es_stack_entries = 16;
1225             break;
1226     case CHIP_FAMILY_RV610:
1227     case CHIP_FAMILY_RV620:
1228     case CHIP_FAMILY_RS780:
1229     case CHIP_FAMILY_RS880:
1230     default:
1231             num_ps_gprs = 84;
1232             num_vs_gprs = 36;
1233             num_temp_gprs = 4;
1234             num_gs_gprs = 0;
1235             num_es_gprs = 0;
1236             num_ps_threads = 136;
1237             num_vs_threads = 48;
1238             num_gs_threads = 4;
1239             num_es_threads = 4;
1240             num_ps_stack_entries = 40;
1241             num_vs_stack_entries = 40;
1242             num_gs_stack_entries = 32;
1243             num_es_stack_entries = 16;
1244             break;
1245     case CHIP_FAMILY_RV670:
1246             num_ps_gprs = 144;
1247             num_vs_gprs = 40;
1248             num_temp_gprs = 4;
1249             num_gs_gprs = 0;
1250             num_es_gprs = 0;
1251             num_ps_threads = 136;
1252             num_vs_threads = 48;
1253             num_gs_threads = 4;
1254             num_es_threads = 4;
1255             num_ps_stack_entries = 40;
1256             num_vs_stack_entries = 40;
1257             num_gs_stack_entries = 32;
1258             num_es_stack_entries = 16;
1259             break;
1260     case CHIP_FAMILY_RV770:
1261             num_ps_gprs = 192;
1262             num_vs_gprs = 56;
1263             num_temp_gprs = 4;
1264             num_gs_gprs = 0;
1265             num_es_gprs = 0;
1266             num_ps_threads = 188;
1267             num_vs_threads = 60;
1268             num_gs_threads = 0;
1269             num_es_threads = 0;
1270             num_ps_stack_entries = 256;
1271             num_vs_stack_entries = 256;
1272             num_gs_stack_entries = 0;
1273             num_es_stack_entries = 0;
1274             break;
1275     case CHIP_FAMILY_RV730:
1276     case CHIP_FAMILY_RV740:
1277             num_ps_gprs = 84;
1278             num_vs_gprs = 36;
1279             num_temp_gprs = 4;
1280             num_gs_gprs = 0;
1281             num_es_gprs = 0;
1282             num_ps_threads = 188;
1283             num_vs_threads = 60;
1284             num_gs_threads = 0;
1285             num_es_threads = 0;
1286             num_ps_stack_entries = 128;
1287             num_vs_stack_entries = 128;
1288             num_gs_stack_entries = 0;
1289             num_es_stack_entries = 0;
1290             break;
1291     case CHIP_FAMILY_RV710:
1292             num_ps_gprs = 192;
1293             num_vs_gprs = 56;
1294             num_temp_gprs = 4;
1295             num_gs_gprs = 0;
1296             num_es_gprs = 0;
1297             num_ps_threads = 144;
1298             num_vs_threads = 48;
1299             num_gs_threads = 0;
1300             num_es_threads = 0;
1301             num_ps_stack_entries = 128;
1302             num_vs_stack_entries = 128;
1303             num_gs_stack_entries = 0;
1304             num_es_stack_entries = 0;
1305             break;
1306     }
1307
1308     sq_config = 0;
1309     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1310         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1311         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1312         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1313         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1314             CLEARbit(sq_config, VC_ENABLE_bit);
1315     else
1316             SETbit(sq_config, VC_ENABLE_bit);
1317     SETbit(sq_config, DX9_CONSTS_bit);
1318     SETbit(sq_config, ALU_INST_PREFER_VECTOR_bit);
1319     SETfield(sq_config, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1320     SETfield(sq_config, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
1321     SETfield(sq_config, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
1322     SETfield(sq_config, es_prio, ES_PRIO_shift, ES_PRIO_mask);
1323
1324     sq_gpr_resource_mgmt_1 = 0;
1325     SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1326     SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1327     SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
1328              NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1329
1330     sq_gpr_resource_mgmt_2 = 0;
1331     SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1332     SETfield(sq_gpr_resource_mgmt_2, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1333
1334     sq_thread_resource_mgmt = 0;
1335     SETfield(sq_thread_resource_mgmt, num_ps_threads,
1336              NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1337     SETfield(sq_thread_resource_mgmt, num_vs_threads,
1338              NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1339     SETfield(sq_thread_resource_mgmt, num_gs_threads,
1340              NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1341     SETfield(sq_thread_resource_mgmt, num_es_threads,
1342              NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1343
1344     sq_stack_resource_mgmt_1 = 0;
1345     SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
1346              NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1347     SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
1348              NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1349
1350     sq_stack_resource_mgmt_2 = 0;
1351     SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
1352              NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1353     SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
1354              NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1355
1356     ta_cntl_aux = 0;
1357     SETfield(ta_cntl_aux, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1358     db_watermarks = 0;
1359     SETfield(db_watermarks, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1360     SETfield(db_watermarks, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1361     SETfield(db_watermarks, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1362     SETfield(db_watermarks, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1363     sq_dyn_gpr_cntl_ps_flush_req = 0;
1364     db_debug = 0;
1365     if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1366             SETfield(ta_cntl_aux, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1367             db_debug = 0x82000000;
1368             SETfield(db_watermarks, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1369     } else {
1370             SETfield(ta_cntl_aux, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1371             SETfield(db_watermarks, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1372             SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
1373     }
1374
1375     BEGIN_BATCH_NO_AUTOSTATE(117);
1376     R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
1377     R600_OUT_BATCH(sq_config);
1378     R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
1379     R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
1380     R600_OUT_BATCH(sq_thread_resource_mgmt);
1381     R600_OUT_BATCH(sq_stack_resource_mgmt_1);
1382     R600_OUT_BATCH(sq_stack_resource_mgmt_2);
1383
1384     R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, ta_cntl_aux);
1385     R600_OUT_BATCH_REGVAL(VC_ENHANCE, 0);
1386     R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, sq_dyn_gpr_cntl_ps_flush_req);
1387     R600_OUT_BATCH_REGVAL(DB_DEBUG, db_debug);
1388     R600_OUT_BATCH_REGVAL(DB_WATERMARKS, db_watermarks);
1389
1390     R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
1391     R600_OUT_BATCH(0);
1392     R600_OUT_BATCH(0);
1393     R600_OUT_BATCH(0);
1394     R600_OUT_BATCH(0);
1395     R600_OUT_BATCH(0);
1396     R600_OUT_BATCH(0);
1397     R600_OUT_BATCH(0);
1398     R600_OUT_BATCH(0);
1399     R600_OUT_BATCH(0);
1400
1401     R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL,
1402                          (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
1403     R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
1404     R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
1405     R600_OUT_BATCH_REGVAL(DB_DEPTH_INFO, 0);
1406     R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
1407     R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
1408     R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
1409     R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
1410     R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, (0xcc << ROP3_shift));
1411
1412     R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, VTX_XY_FMT_bit);
1413     R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, 0);
1414     R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, CLIP_DISABLE_bit);
1415     R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, (FACE_bit) |
1416         (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) |
1417         (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift));
1418     R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL, (PIX_CENTER_bit) |
1419         (X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
1420         (X_1_256TH << QUANT_MODE_shift));
1421
1422     R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1423     R600_OUT_BATCH(2048);
1424     R600_OUT_BATCH(0);
1425     R600_OUT_BATCH(0);
1426     R600_OUT_BATCH(0);
1427
1428     R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1429     R600_OUT_BATCH(0);
1430     R600_OUT_BATCH(0);
1431     R600_OUT_BATCH(0);
1432     R600_OUT_BATCH(0);
1433     R600_OUT_BATCH(0);
1434     R600_OUT_BATCH(0);
1435     R600_OUT_BATCH(0);
1436     R600_OUT_BATCH(0);
1437     R600_OUT_BATCH(0);
1438     R600_OUT_BATCH(0);
1439     R600_OUT_BATCH(0);
1440     R600_OUT_BATCH(0);
1441     R600_OUT_BATCH(0);
1442
1443     R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, 0);
1444     R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, 0);
1445     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, 0);
1446     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, 0);
1447
1448     R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1449     R600_OUT_BATCH(0);
1450     R600_OUT_BATCH(0);
1451     R600_OUT_BATCH(0);
1452
1453     R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, 0);
1454
1455     END_BATCH();
1456     COMMIT_BATCH();
1457 }
1458
1459 static GLboolean validate_buffers(context_t *rmesa,
1460                                   struct radeon_bo *src_bo,
1461                                   struct radeon_bo *dst_bo)
1462 {
1463     int ret;
1464     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1465                                       src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
1466
1467     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1468                                       dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
1469
1470     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1471                                       rmesa->blit_bo, RADEON_GEM_DOMAIN_GTT, 0);
1472
1473     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1474                                         rmesa->blit_bo,
1475                                         RADEON_GEM_DOMAIN_GTT, 0);
1476     if (ret)
1477         return GL_FALSE;
1478
1479     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1480                                         first_elem(&rmesa->radeon.dma.reserved)->bo,
1481                                         RADEON_GEM_DOMAIN_GTT, 0);
1482     if (ret)
1483         return GL_FALSE;
1484
1485     return GL_TRUE;
1486 }
1487
1488 GLboolean r600_blit(context_t *context,
1489                     struct radeon_bo *src_bo,
1490                     intptr_t src_offset,
1491                     gl_format src_mesaformat,
1492                     unsigned src_pitch,
1493                     unsigned src_width,
1494                     unsigned src_height,
1495                     unsigned src_x,
1496                     unsigned src_y,
1497                     struct radeon_bo *dst_bo,
1498                     intptr_t dst_offset,
1499                     gl_format dst_mesaformat,
1500                     unsigned dst_pitch,
1501                     unsigned dst_width,
1502                     unsigned dst_height,
1503                     unsigned dst_x,
1504                     unsigned dst_y,
1505                     unsigned w,
1506                     unsigned h,
1507                     unsigned flip_y)
1508 {
1509     int id = 0;
1510
1511     /* not sure blit to depth works or not yet */
1512     if (_mesa_get_format_bits(src_mesaformat, GL_DEPTH_BITS) > 0)
1513             return GL_FALSE;
1514
1515     if (src_bo == dst_bo) {
1516         return GL_FALSE;
1517     }
1518
1519     if (0) {
1520         fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1521                 src_width, src_height, src_pitch,
1522                 _mesa_format_row_stride(src_mesaformat, src_width),
1523                 _mesa_get_format_name(src_mesaformat));
1524         fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
1525                 dst_width, dst_height,
1526                 _mesa_format_row_stride(dst_mesaformat, dst_width),
1527                 _mesa_get_format_name(dst_mesaformat));
1528     }
1529
1530     /* Flush is needed to make sure that source buffer has correct data */
1531     radeonFlush(context->radeon.glCtx);
1532
1533     rcommonEnsureCmdBufSpace(&context->radeon, 302, __FUNCTION__);
1534
1535     /* load shaders */
1536     load_shaders(context->radeon.glCtx);
1537
1538     if (!validate_buffers(context, src_bo, dst_bo))
1539         return GL_FALSE;
1540
1541     /* set clear state */
1542     /* 117 */
1543     set_default_state(context);
1544
1545     /* shaders */
1546     /* 72 */
1547     set_shaders(context);
1548
1549     /* src */
1550     /* 20 */
1551     set_tex_resource(context, src_mesaformat, src_bo,
1552                      src_width, src_height, src_pitch, src_offset);
1553
1554     /* 5 */
1555     set_tex_sampler(context);
1556
1557     /* dst */
1558     /* 25 */
1559     set_render_target(context, dst_bo, dst_mesaformat,
1560                       dst_pitch, dst_width, dst_height, dst_offset);
1561     /* scissors */
1562     /* 17 */
1563     set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
1564
1565     set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
1566     /* Vertex buffer setup */
1567     /* 24 */
1568     set_vtx_resource(context);
1569
1570     /* draw */
1571     /* 10 */
1572     draw_auto(context);
1573
1574     /* 7 */
1575     r700SyncSurf(context, dst_bo, 0,
1576                  RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
1577                  CB_ACTION_ENA_bit | (1 << (id + 6)));
1578
1579     /* 5 */
1580     r700WaitForIdleClean(context);
1581
1582     radeonFlush(context->radeon.glCtx);
1583
1584     return GL_TRUE;
1585 }