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r600c: add big endian support for r6xx/r7xx
[mesa.git] / src / mesa / drivers / dri / r600 / r600_blit.c
1 /*
2 * Copyright (C) 2009 Advanced Micro Devices, Inc.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #include "radeon_common.h"
29 #include "r600_context.h"
30
31 #include "r600_blit.h"
32 #include "r600_blit_shaders.h"
33 #include "r600_cmdbuf.h"
34
35 /* common formats supported as both textures and render targets */
36 unsigned r600_check_blit(gl_format mesa_format)
37 {
38 switch (mesa_format) {
39 case MESA_FORMAT_RGBA8888:
40 case MESA_FORMAT_SIGNED_RGBA8888:
41 case MESA_FORMAT_RGBA8888_REV:
42 case MESA_FORMAT_SIGNED_RGBA8888_REV:
43 case MESA_FORMAT_ARGB8888:
44 case MESA_FORMAT_XRGB8888:
45 case MESA_FORMAT_ARGB8888_REV:
46 case MESA_FORMAT_XRGB8888_REV:
47 case MESA_FORMAT_RGB565:
48 case MESA_FORMAT_RGB565_REV:
49 case MESA_FORMAT_ARGB4444:
50 case MESA_FORMAT_ARGB4444_REV:
51 case MESA_FORMAT_ARGB1555:
52 case MESA_FORMAT_ARGB1555_REV:
53 case MESA_FORMAT_AL88:
54 case MESA_FORMAT_AL88_REV:
55 case MESA_FORMAT_RGB332:
56 case MESA_FORMAT_A8:
57 case MESA_FORMAT_I8:
58 case MESA_FORMAT_CI8:
59 case MESA_FORMAT_L8:
60 case MESA_FORMAT_RGBA_FLOAT32:
61 case MESA_FORMAT_RGBA_FLOAT16:
62 case MESA_FORMAT_ALPHA_FLOAT32:
63 case MESA_FORMAT_ALPHA_FLOAT16:
64 case MESA_FORMAT_LUMINANCE_FLOAT32:
65 case MESA_FORMAT_LUMINANCE_FLOAT16:
66 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
67 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
68 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
69 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
70 case MESA_FORMAT_X8_Z24:
71 case MESA_FORMAT_S8_Z24:
72 case MESA_FORMAT_Z24_S8:
73 case MESA_FORMAT_Z16:
74 case MESA_FORMAT_Z32:
75 case MESA_FORMAT_SARGB8:
76 case MESA_FORMAT_SLA8:
77 case MESA_FORMAT_SL8:
78 break;
79 default:
80 return 0;
81 }
82
83 /* ??? */
84 /* not sure blit to depth works or not yet */
85 if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
86 return 0;
87
88 return 1;
89 }
90
91 static inline void
92 set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
93 int nPitchInPixel, int w, int h, intptr_t dst_offset)
94 {
95 uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
96 int id = 0;
97 uint32_t endian, comp_swap, format;
98 BATCH_LOCALS(&context->radeon);
99
100 cb_color0_base = dst_offset / 256;
101 endian = ENDIAN_NONE;
102
103 SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
104 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
105 SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
106 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
107
108 SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
109 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
110
111 SETbit(cb_color0_info, BLEND_BYPASS_bit);
112
113 switch(mesa_format) {
114 case MESA_FORMAT_RGBA8888:
115 #ifdef MESA_BIG_ENDIAN
116 endian = ENDIAN_8IN32;
117 #endif
118 format = COLOR_8_8_8_8;
119 comp_swap = SWAP_STD_REV;
120 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
121 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
122 break;
123 case MESA_FORMAT_SIGNED_RGBA8888:
124 #ifdef MESA_BIG_ENDIAN
125 endian = ENDIAN_8IN32;
126 #endif
127 format = COLOR_8_8_8_8;
128 comp_swap = SWAP_STD_REV;
129 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
130 SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
131 break;
132 case MESA_FORMAT_RGBA8888_REV:
133 #ifdef MESA_BIG_ENDIAN
134 endian = ENDIAN_8IN32;
135 #endif
136 format = COLOR_8_8_8_8;
137 comp_swap = SWAP_STD;
138 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
139 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
140 break;
141 case MESA_FORMAT_SIGNED_RGBA8888_REV:
142 #ifdef MESA_BIG_ENDIAN
143 endian = ENDIAN_8IN32;
144 #endif
145 format = COLOR_8_8_8_8;
146 comp_swap = SWAP_STD;
147 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
148 SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
149 break;
150 case MESA_FORMAT_ARGB8888:
151 case MESA_FORMAT_XRGB8888:
152 #ifdef MESA_BIG_ENDIAN
153 endian = ENDIAN_8IN32;
154 #endif
155 format = COLOR_8_8_8_8;
156 comp_swap = SWAP_ALT;
157 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
158 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
159 break;
160 case MESA_FORMAT_ARGB8888_REV:
161 case MESA_FORMAT_XRGB8888_REV:
162 #ifdef MESA_BIG_ENDIAN
163 endian = ENDIAN_8IN32;
164 #endif
165 format = COLOR_8_8_8_8;
166 comp_swap = SWAP_ALT_REV;
167 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
168 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
169 break;
170 case MESA_FORMAT_RGB565:
171 #ifdef MESA_BIG_ENDIAN
172 endian = ENDIAN_8IN16;
173 #endif
174 comp_swap = SWAP_STD_REV;
175 format = COLOR_5_6_5;
176 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
177 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
178 break;
179 case MESA_FORMAT_RGB565_REV:
180 #ifdef MESA_BIG_ENDIAN
181 endian = ENDIAN_8IN16;
182 #endif
183 comp_swap = SWAP_STD;
184 format = COLOR_5_6_5;
185 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
186 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
187 break;
188 case MESA_FORMAT_ARGB4444:
189 #ifdef MESA_BIG_ENDIAN
190 endian = ENDIAN_8IN16;
191 #endif
192 format = COLOR_4_4_4_4;
193 comp_swap = SWAP_ALT;
194 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
195 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
196 break;
197 case MESA_FORMAT_ARGB4444_REV:
198 #ifdef MESA_BIG_ENDIAN
199 endian = ENDIAN_8IN16;
200 #endif
201 format = COLOR_4_4_4_4;
202 comp_swap = SWAP_ALT_REV;
203 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
204 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
205 break;
206 case MESA_FORMAT_ARGB1555:
207 #ifdef MESA_BIG_ENDIAN
208 endian = ENDIAN_8IN16;
209 #endif
210 format = COLOR_1_5_5_5;
211 comp_swap = SWAP_ALT;
212 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
213 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
214 break;
215 case MESA_FORMAT_ARGB1555_REV:
216 #ifdef MESA_BIG_ENDIAN
217 endian = ENDIAN_8IN16;
218 #endif
219 format = COLOR_1_5_5_5;
220 comp_swap = SWAP_ALT_REV;
221 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
222 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
223 break;
224 case MESA_FORMAT_AL88:
225 #ifdef MESA_BIG_ENDIAN
226 endian = ENDIAN_8IN16;
227 #endif
228 format = COLOR_8_8;
229 comp_swap = SWAP_STD;
230 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
231 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
232 break;
233 case MESA_FORMAT_AL88_REV:
234 #ifdef MESA_BIG_ENDIAN
235 endian = ENDIAN_8IN16;
236 #endif
237 format = COLOR_8_8;
238 comp_swap = SWAP_STD_REV;
239 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
240 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
241 break;
242 case MESA_FORMAT_RGB332:
243 format = COLOR_3_3_2;
244 comp_swap = SWAP_STD_REV;
245 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
246 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
247 break;
248 case MESA_FORMAT_A8:
249 format = COLOR_8;
250 comp_swap = SWAP_ALT_REV;
251 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
252 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
253 break;
254 case MESA_FORMAT_I8:
255 case MESA_FORMAT_CI8:
256 format = COLOR_8;
257 comp_swap = SWAP_STD;
258 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
259 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
260 break;
261 case MESA_FORMAT_L8:
262 format = COLOR_8;
263 comp_swap = SWAP_ALT;
264 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
265 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
266 break;
267 case MESA_FORMAT_RGBA_FLOAT32:
268 #ifdef MESA_BIG_ENDIAN
269 endian = ENDIAN_8IN32;
270 #endif
271 format = COLOR_32_32_32_32_FLOAT;
272 comp_swap = SWAP_STD;
273 SETbit(cb_color0_info, BLEND_FLOAT32_bit);
274 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
275 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
276 break;
277 case MESA_FORMAT_RGBA_FLOAT16:
278 #ifdef MESA_BIG_ENDIAN
279 endian = ENDIAN_8IN16;
280 #endif
281 format = COLOR_16_16_16_16_FLOAT;
282 comp_swap = SWAP_STD;
283 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
284 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
285 break;
286 case MESA_FORMAT_ALPHA_FLOAT32:
287 #ifdef MESA_BIG_ENDIAN
288 endian = ENDIAN_8IN32;
289 #endif
290 format = COLOR_32_FLOAT;
291 comp_swap = SWAP_ALT_REV;
292 SETbit(cb_color0_info, BLEND_FLOAT32_bit);
293 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
294 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
295 break;
296 case MESA_FORMAT_ALPHA_FLOAT16:
297 #ifdef MESA_BIG_ENDIAN
298 endian = ENDIAN_8IN16;
299 #endif
300 format = COLOR_16_FLOAT;
301 comp_swap = SWAP_ALT_REV;
302 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
303 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
304 break;
305 case MESA_FORMAT_LUMINANCE_FLOAT32:
306 #ifdef MESA_BIG_ENDIAN
307 endian = ENDIAN_8IN32;
308 #endif
309 format = COLOR_32_FLOAT;
310 comp_swap = SWAP_ALT;
311 SETbit(cb_color0_info, BLEND_FLOAT32_bit);
312 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
313 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
314 break;
315 case MESA_FORMAT_LUMINANCE_FLOAT16:
316 #ifdef MESA_BIG_ENDIAN
317 endian = ENDIAN_8IN16;
318 #endif
319 format = COLOR_16_FLOAT;
320 comp_swap = SWAP_ALT;
321 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
322 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
323 break;
324 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
325 #ifdef MESA_BIG_ENDIAN
326 endian = ENDIAN_8IN32;
327 #endif
328 format = COLOR_32_32_FLOAT;
329 comp_swap = SWAP_ALT_REV;
330 SETbit(cb_color0_info, BLEND_FLOAT32_bit);
331 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
332 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
333 break;
334 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
335 #ifdef MESA_BIG_ENDIAN
336 endian = ENDIAN_8IN16;
337 #endif
338 format = COLOR_16_16_FLOAT;
339 comp_swap = SWAP_ALT_REV;
340 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
341 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
342 break;
343 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
344 #ifdef MESA_BIG_ENDIAN
345 endian = ENDIAN_8IN32;
346 #endif
347 format = COLOR_32_FLOAT;
348 comp_swap = SWAP_STD;
349 SETbit(cb_color0_info, BLEND_FLOAT32_bit);
350 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
351 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
352 break;
353 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
354 #ifdef MESA_BIG_ENDIAN
355 endian = ENDIAN_8IN16;
356 #endif
357 format = COLOR_16_FLOAT;
358 comp_swap = SWAP_STD;
359 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
360 SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
361 break;
362 case MESA_FORMAT_X8_Z24:
363 case MESA_FORMAT_S8_Z24:
364 #ifdef MESA_BIG_ENDIAN
365 endian = ENDIAN_8IN32;
366 #endif
367 format = COLOR_8_24;
368 comp_swap = SWAP_STD;
369 SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
370 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
371 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
372 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
373 break;
374 case MESA_FORMAT_Z24_S8:
375 #ifdef MESA_BIG_ENDIAN
376 endian = ENDIAN_8IN32;
377 #endif
378 format = COLOR_24_8;
379 comp_swap = SWAP_STD;
380 SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
381 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
382 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
383 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
384 break;
385 case MESA_FORMAT_Z16:
386 #ifdef MESA_BIG_ENDIAN
387 endian = ENDIAN_8IN16;
388 #endif
389 format = COLOR_16;
390 comp_swap = SWAP_STD;
391 SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
392 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
393 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
394 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
395 break;
396 case MESA_FORMAT_Z32:
397 #ifdef MESA_BIG_ENDIAN
398 endian = ENDIAN_8IN32;
399 #endif
400 format = COLOR_32;
401 comp_swap = SWAP_STD;
402 SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
403 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
404 CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
405 SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
406 break;
407 case MESA_FORMAT_SARGB8:
408 #ifdef MESA_BIG_ENDIAN
409 endian = ENDIAN_8IN32;
410 #endif
411 format = COLOR_8_8_8_8;
412 comp_swap = SWAP_ALT;
413 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
414 SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
415 break;
416 case MESA_FORMAT_SLA8:
417 #ifdef MESA_BIG_ENDIAN
418 endian = ENDIAN_8IN16;
419 #endif
420 format = COLOR_8_8;
421 comp_swap = SWAP_ALT_REV;
422 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
423 SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
424 break;
425 case MESA_FORMAT_SL8:
426 format = COLOR_8;
427 comp_swap = SWAP_ALT_REV;
428 SETbit(cb_color0_info, SOURCE_FORMAT_bit);
429 SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
430 break;
431 default:
432 fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
433 assert("Invalid format for US output\n");
434 return;
435 }
436
437 /* must be 0 on r7xx */
438 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
439 CLEARbit(cb_color0_info, BLEND_FLOAT32_bit);
440
441 SETfield(cb_color0_info, endian, ENDIAN_shift, ENDIAN_mask);
442 SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
443 CB_COLOR0_INFO__FORMAT_mask);
444 SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
445
446 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
447 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
448 R600_OUT_BATCH(cb_color0_base);
449 R600_OUT_BATCH_RELOC(0,
450 bo,
451 0,
452 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
453 END_BATCH();
454
455 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
456 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
457 BEGIN_BATCH_NO_AUTOSTATE(2);
458 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
459 R600_OUT_BATCH((2 << id));
460 END_BATCH();
461 }
462
463 /* Set CMASK & TILE buffer to the offset of color buffer as
464 * we don't use those this shouldn't cause any issue and we
465 * then have a valid cmd stream
466 */
467 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
468 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
469 R600_OUT_BATCH(cb_color0_base);
470 R600_OUT_BATCH_RELOC(0,
471 bo,
472 0,
473 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
474 END_BATCH();
475 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
476 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
477 R600_OUT_BATCH(cb_color0_base);
478 R600_OUT_BATCH_RELOC(0,
479 bo,
480 0,
481 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
482 END_BATCH();
483
484 BEGIN_BATCH_NO_AUTOSTATE(9);
485 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
486 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
487 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
488 END_BATCH();
489
490 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
491 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
492 R600_OUT_BATCH_RELOC(0,
493 bo,
494 0,
495 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
496 END_BATCH();
497
498 COMMIT_BATCH();
499
500 }
501
502 static inline void load_shaders(struct gl_context * ctx)
503 {
504
505 radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
506 context_t *context = R700_CONTEXT(ctx);
507 int i, size;
508 uint32_t *shader;
509
510 if (context->blit_bo_loaded == 1)
511 return;
512
513 size = 4096;
514 context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
515 size, 256, RADEON_GEM_DOMAIN_GTT, 0);
516 radeon_bo_map(context->blit_bo, 1);
517 shader = context->blit_bo->ptr;
518
519 for(i=0; i<sizeof(r6xx_vs)/4; i++) {
520 shader[128+i] = CPU_TO_LE32(r6xx_vs[i]);
521 }
522 for(i=0; i<sizeof(r6xx_ps)/4; i++) {
523 shader[256+i] = CPU_TO_LE32(r6xx_ps[i]);
524 }
525
526 radeon_bo_unmap(context->blit_bo);
527 context->blit_bo_loaded = 1;
528
529 }
530
531 static inline void
532 set_shaders(context_t *context)
533 {
534 struct radeon_bo * pbo = context->blit_bo;
535 BATCH_LOCALS(&context->radeon);
536
537 uint32_t sq_pgm_start_fs = (512 >> 8);
538 uint32_t sq_pgm_resources_fs = 0;
539 uint32_t sq_pgm_cf_offset_fs = 0;
540
541 uint32_t sq_pgm_start_vs = (512 >> 8);
542 uint32_t sq_pgm_resources_vs = (1 << NUM_GPRS_shift);
543 uint32_t sq_pgm_cf_offset_vs = 0;
544
545 uint32_t sq_pgm_start_ps = (1024 >> 8);
546 uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
547 uint32_t sq_pgm_cf_offset_ps = 0;
548 uint32_t sq_pgm_exports_ps = (1 << 1);
549
550 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
551
552 /* FS */
553 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
554 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
555 R600_OUT_BATCH(sq_pgm_start_fs);
556 R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
557 pbo,
558 sq_pgm_start_fs,
559 RADEON_GEM_DOMAIN_GTT, 0, 0);
560 END_BATCH();
561
562 BEGIN_BATCH_NO_AUTOSTATE(6);
563 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
564 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, sq_pgm_cf_offset_fs);
565 END_BATCH();
566
567 /* VS */
568 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
569 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
570 R600_OUT_BATCH(sq_pgm_start_vs);
571 R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
572 pbo,
573 sq_pgm_start_vs,
574 RADEON_GEM_DOMAIN_GTT, 0, 0);
575 END_BATCH();
576
577 BEGIN_BATCH_NO_AUTOSTATE(6);
578 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, sq_pgm_resources_vs);
579 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, sq_pgm_cf_offset_vs);
580 END_BATCH();
581
582 /* PS */
583 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
584 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
585 R600_OUT_BATCH(sq_pgm_start_ps);
586 R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
587 pbo,
588 sq_pgm_start_ps,
589 RADEON_GEM_DOMAIN_GTT, 0, 0);
590 END_BATCH();
591
592 BEGIN_BATCH_NO_AUTOSTATE(9);
593 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, sq_pgm_resources_ps);
594 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, sq_pgm_exports_ps);
595 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, sq_pgm_cf_offset_ps);
596 END_BATCH();
597
598 BEGIN_BATCH_NO_AUTOSTATE(18);
599 R600_OUT_BATCH_REGVAL(SPI_VS_OUT_CONFIG, 0); //EXPORT_COUNT is - 1
600 R600_OUT_BATCH_REGVAL(SPI_VS_OUT_ID_0, 0);
601 R600_OUT_BATCH_REGVAL(SPI_PS_INPUT_CNTL_0, SEL_CENTROID_bit);
602 R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_0, (1 << NUM_INTERP_shift));
603 R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_1, 0);
604 R600_OUT_BATCH_REGVAL(SPI_INTERP_CONTROL_0, 0);
605 END_BATCH();
606
607 COMMIT_BATCH();
608
609 }
610
611 static inline void
612 set_vtx_resource(context_t *context)
613 {
614 struct radeon_bo *bo = context->blit_bo;
615 uint32_t sq_vtx_constant_word2 = 0;
616
617 BATCH_LOCALS(&context->radeon);
618
619 BEGIN_BATCH_NO_AUTOSTATE(6);
620 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
621 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
622 R600_OUT_BATCH(0);
623
624 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
625 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
626 R600_OUT_BATCH(0);
627 END_BATCH();
628 COMMIT_BATCH();
629
630 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
631 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
632 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
633 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
634 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
635 r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
636 else
637 r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
638
639 sq_vtx_constant_word2 = 0
640 #ifdef MESA_BIG_ENDIAN
641 | (SQ_ENDIAN_8IN32 << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)
642 #endif
643 | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
644
645 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
646
647 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
648 R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
649 R600_OUT_BATCH(0);
650 R600_OUT_BATCH(48 - 1);
651 R600_OUT_BATCH(sq_vtx_constant_word2);
652 R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
653 R600_OUT_BATCH(0);
654 R600_OUT_BATCH(0);
655 R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
656 R600_OUT_BATCH_RELOC(0,
657 bo,
658 0,
659 RADEON_GEM_DOMAIN_GTT, 0, 0);
660 END_BATCH();
661 COMMIT_BATCH();
662
663 }
664
665 static inline void
666 set_tex_resource(context_t * context,
667 gl_format mesa_format, struct radeon_bo *bo, int w, int h,
668 int TexelPitch, intptr_t src_offset)
669 {
670 uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource6;
671
672 sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource6 = 0;
673 BATCH_LOCALS(&context->radeon);
674
675 SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
676 SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
677 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
678 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
679
680 switch (mesa_format) {
681 case MESA_FORMAT_RGBA8888:
682 case MESA_FORMAT_SIGNED_RGBA8888:
683 SETfield(sq_tex_resource1, FMT_8_8_8_8,
684 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
685
686 SETfield(sq_tex_resource4, SQ_SEL_W,
687 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
688 SETfield(sq_tex_resource4, SQ_SEL_Z,
689 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
690 SETfield(sq_tex_resource4, SQ_SEL_Y,
691 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
692 SETfield(sq_tex_resource4, SQ_SEL_X,
693 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
694 if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
695 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
696 FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
697 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
698 FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
699 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
700 FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
701 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
702 FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
703 }
704 break;
705 case MESA_FORMAT_RGBA8888_REV:
706 case MESA_FORMAT_SIGNED_RGBA8888_REV:
707 SETfield(sq_tex_resource1, FMT_8_8_8_8,
708 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
709
710 SETfield(sq_tex_resource4, SQ_SEL_X,
711 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
712 SETfield(sq_tex_resource4, SQ_SEL_Y,
713 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
714 SETfield(sq_tex_resource4, SQ_SEL_Z,
715 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
716 SETfield(sq_tex_resource4, SQ_SEL_W,
717 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
718 if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
719 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
720 FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
721 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
722 FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
723 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
724 FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
725 SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
726 FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
727 }
728 break;
729 case MESA_FORMAT_ARGB8888:
730 SETfield(sq_tex_resource1, FMT_8_8_8_8,
731 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
732
733 SETfield(sq_tex_resource4, SQ_SEL_Z,
734 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
735 SETfield(sq_tex_resource4, SQ_SEL_Y,
736 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
737 SETfield(sq_tex_resource4, SQ_SEL_X,
738 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
739 SETfield(sq_tex_resource4, SQ_SEL_W,
740 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
741 break;
742 case MESA_FORMAT_XRGB8888:
743 SETfield(sq_tex_resource1, FMT_8_8_8_8,
744 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
745
746 SETfield(sq_tex_resource4, SQ_SEL_Z,
747 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
748 SETfield(sq_tex_resource4, SQ_SEL_Y,
749 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
750 SETfield(sq_tex_resource4, SQ_SEL_X,
751 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
752 SETfield(sq_tex_resource4, SQ_SEL_1,
753 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
754 break;
755 case MESA_FORMAT_ARGB8888_REV:
756 SETfield(sq_tex_resource1, FMT_8_8_8_8,
757 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
758
759 SETfield(sq_tex_resource4, SQ_SEL_Y,
760 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
761 SETfield(sq_tex_resource4, SQ_SEL_Z,
762 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
763 SETfield(sq_tex_resource4, SQ_SEL_W,
764 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
765 SETfield(sq_tex_resource4, SQ_SEL_X,
766 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
767 break;
768 case MESA_FORMAT_XRGB8888_REV:
769 SETfield(sq_tex_resource1, FMT_8_8_8_8,
770 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
771
772 SETfield(sq_tex_resource4, SQ_SEL_Y,
773 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
774 SETfield(sq_tex_resource4, SQ_SEL_Z,
775 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
776 SETfield(sq_tex_resource4, SQ_SEL_1,
777 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
778 SETfield(sq_tex_resource4, SQ_SEL_X,
779 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
780 break;
781 case MESA_FORMAT_RGB565:
782 SETfield(sq_tex_resource1, FMT_5_6_5,
783 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
784
785 SETfield(sq_tex_resource4, SQ_SEL_Z,
786 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
787 SETfield(sq_tex_resource4, SQ_SEL_Y,
788 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
789 SETfield(sq_tex_resource4, SQ_SEL_X,
790 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
791 SETfield(sq_tex_resource4, SQ_SEL_1,
792 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
793 break;
794 case MESA_FORMAT_RGB565_REV:
795 SETfield(sq_tex_resource1, FMT_5_6_5,
796 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
797
798 SETfield(sq_tex_resource4, SQ_SEL_X,
799 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
800 SETfield(sq_tex_resource4, SQ_SEL_Y,
801 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
802 SETfield(sq_tex_resource4, SQ_SEL_Z,
803 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
804 SETfield(sq_tex_resource4, SQ_SEL_1,
805 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
806 break;
807 case MESA_FORMAT_ARGB4444:
808 SETfield(sq_tex_resource1, FMT_4_4_4_4,
809 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
810
811 SETfield(sq_tex_resource4, SQ_SEL_Z,
812 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
813 SETfield(sq_tex_resource4, SQ_SEL_Y,
814 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
815 SETfield(sq_tex_resource4, SQ_SEL_X,
816 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
817 SETfield(sq_tex_resource4, SQ_SEL_W,
818 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
819 break;
820 case MESA_FORMAT_ARGB4444_REV:
821 SETfield(sq_tex_resource1, FMT_4_4_4_4,
822 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
823
824 SETfield(sq_tex_resource4, SQ_SEL_Y,
825 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
826 SETfield(sq_tex_resource4, SQ_SEL_Z,
827 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
828 SETfield(sq_tex_resource4, SQ_SEL_W,
829 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
830 SETfield(sq_tex_resource4, SQ_SEL_X,
831 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
832 break;
833 case MESA_FORMAT_ARGB1555:
834 SETfield(sq_tex_resource1, FMT_1_5_5_5,
835 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
836
837 SETfield(sq_tex_resource4, SQ_SEL_Z,
838 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
839 SETfield(sq_tex_resource4, SQ_SEL_Y,
840 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
841 SETfield(sq_tex_resource4, SQ_SEL_X,
842 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
843 SETfield(sq_tex_resource4, SQ_SEL_W,
844 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
845 break;
846 case MESA_FORMAT_ARGB1555_REV:
847 SETfield(sq_tex_resource1, FMT_1_5_5_5,
848 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
849
850 SETfield(sq_tex_resource4, SQ_SEL_Y,
851 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
852 SETfield(sq_tex_resource4, SQ_SEL_Z,
853 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
854 SETfield(sq_tex_resource4, SQ_SEL_W,
855 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
856 SETfield(sq_tex_resource4, SQ_SEL_X,
857 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
858 break;
859 case MESA_FORMAT_AL88:
860 case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
861 SETfield(sq_tex_resource1, FMT_8_8,
862 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
863
864 SETfield(sq_tex_resource4, SQ_SEL_X,
865 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
866 SETfield(sq_tex_resource4, SQ_SEL_X,
867 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
868 SETfield(sq_tex_resource4, SQ_SEL_X,
869 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
870 SETfield(sq_tex_resource4, SQ_SEL_Y,
871 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
872 break;
873 case MESA_FORMAT_RGB332:
874 SETfield(sq_tex_resource1, FMT_3_3_2,
875 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
876
877 SETfield(sq_tex_resource4, SQ_SEL_Z,
878 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
879 SETfield(sq_tex_resource4, SQ_SEL_Y,
880 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
881 SETfield(sq_tex_resource4, SQ_SEL_X,
882 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
883 SETfield(sq_tex_resource4, SQ_SEL_1,
884 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
885 break;
886 case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
887 SETfield(sq_tex_resource1, FMT_8,
888 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
889
890 SETfield(sq_tex_resource4, SQ_SEL_0,
891 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
892 SETfield(sq_tex_resource4, SQ_SEL_0,
893 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
894 SETfield(sq_tex_resource4, SQ_SEL_0,
895 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
896 SETfield(sq_tex_resource4, SQ_SEL_X,
897 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
898 break;
899 case MESA_FORMAT_L8: /* X, X, X, ONE */
900 SETfield(sq_tex_resource1, FMT_8,
901 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
902
903 SETfield(sq_tex_resource4, SQ_SEL_X,
904 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
905 SETfield(sq_tex_resource4, SQ_SEL_X,
906 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
907 SETfield(sq_tex_resource4, SQ_SEL_X,
908 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
909 SETfield(sq_tex_resource4, SQ_SEL_1,
910 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
911 break;
912 case MESA_FORMAT_I8: /* X, X, X, X */
913 case MESA_FORMAT_CI8:
914 SETfield(sq_tex_resource1, FMT_8,
915 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
916
917 SETfield(sq_tex_resource4, SQ_SEL_X,
918 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
919 SETfield(sq_tex_resource4, SQ_SEL_X,
920 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
921 SETfield(sq_tex_resource4, SQ_SEL_X,
922 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
923 SETfield(sq_tex_resource4, SQ_SEL_X,
924 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
925 break;
926 case MESA_FORMAT_RGBA_FLOAT32:
927 SETfield(sq_tex_resource1, FMT_32_32_32_32_FLOAT,
928 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
929
930 SETfield(sq_tex_resource4, SQ_SEL_X,
931 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
932 SETfield(sq_tex_resource4, SQ_SEL_Y,
933 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
934 SETfield(sq_tex_resource4, SQ_SEL_Z,
935 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
936 SETfield(sq_tex_resource4, SQ_SEL_W,
937 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
938 break;
939 case MESA_FORMAT_RGBA_FLOAT16:
940 SETfield(sq_tex_resource1, FMT_16_16_16_16_FLOAT,
941 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
942
943 SETfield(sq_tex_resource4, SQ_SEL_X,
944 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
945 SETfield(sq_tex_resource4, SQ_SEL_Y,
946 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
947 SETfield(sq_tex_resource4, SQ_SEL_Z,
948 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
949 SETfield(sq_tex_resource4, SQ_SEL_W,
950 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
951 break;
952 case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
953 SETfield(sq_tex_resource1, FMT_32_FLOAT,
954 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
955
956 SETfield(sq_tex_resource4, SQ_SEL_0,
957 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
958 SETfield(sq_tex_resource4, SQ_SEL_0,
959 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
960 SETfield(sq_tex_resource4, SQ_SEL_0,
961 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
962 SETfield(sq_tex_resource4, SQ_SEL_X,
963 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
964 break;
965 case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
966 SETfield(sq_tex_resource1, FMT_16_FLOAT,
967 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
968
969 SETfield(sq_tex_resource4, SQ_SEL_0,
970 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
971 SETfield(sq_tex_resource4, SQ_SEL_0,
972 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
973 SETfield(sq_tex_resource4, SQ_SEL_0,
974 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
975 SETfield(sq_tex_resource4, SQ_SEL_X,
976 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
977 break;
978 case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
979 SETfield(sq_tex_resource1, FMT_32_FLOAT,
980 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
981
982 SETfield(sq_tex_resource4, SQ_SEL_X,
983 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
984 SETfield(sq_tex_resource4, SQ_SEL_X,
985 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
986 SETfield(sq_tex_resource4, SQ_SEL_X,
987 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
988 SETfield(sq_tex_resource4, SQ_SEL_1,
989 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
990 break;
991 case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
992 SETfield(sq_tex_resource1, FMT_16_FLOAT,
993 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
994
995 SETfield(sq_tex_resource4, SQ_SEL_X,
996 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
997 SETfield(sq_tex_resource4, SQ_SEL_X,
998 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
999 SETfield(sq_tex_resource4, SQ_SEL_X,
1000 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1001 SETfield(sq_tex_resource4, SQ_SEL_1,
1002 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1003 break;
1004 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
1005 SETfield(sq_tex_resource1, FMT_32_32_FLOAT,
1006 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1007
1008 SETfield(sq_tex_resource4, SQ_SEL_X,
1009 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1010 SETfield(sq_tex_resource4, SQ_SEL_X,
1011 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1012 SETfield(sq_tex_resource4, SQ_SEL_X,
1013 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1014 SETfield(sq_tex_resource4, SQ_SEL_Y,
1015 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1016 break;
1017 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
1018 SETfield(sq_tex_resource1, FMT_16_16_FLOAT,
1019 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1020
1021 SETfield(sq_tex_resource4, SQ_SEL_X,
1022 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1023 SETfield(sq_tex_resource4, SQ_SEL_X,
1024 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1025 SETfield(sq_tex_resource4, SQ_SEL_X,
1026 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1027 SETfield(sq_tex_resource4, SQ_SEL_Y,
1028 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1029 break;
1030 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
1031 SETfield(sq_tex_resource1, FMT_32_FLOAT,
1032 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1033
1034 SETfield(sq_tex_resource4, SQ_SEL_X,
1035 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1036 SETfield(sq_tex_resource4, SQ_SEL_X,
1037 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1038 SETfield(sq_tex_resource4, SQ_SEL_X,
1039 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1040 SETfield(sq_tex_resource4, SQ_SEL_X,
1041 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1042 break;
1043 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
1044 SETfield(sq_tex_resource1, FMT_16_FLOAT,
1045 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1046
1047 SETfield(sq_tex_resource4, SQ_SEL_X,
1048 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1049 SETfield(sq_tex_resource4, SQ_SEL_X,
1050 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1051 SETfield(sq_tex_resource4, SQ_SEL_X,
1052 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1053 SETfield(sq_tex_resource4, SQ_SEL_X,
1054 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1055 break;
1056 case MESA_FORMAT_Z16:
1057 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1058 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1059 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1060 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1061 SETfield(sq_tex_resource1, FMT_16,
1062 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1063 SETfield(sq_tex_resource4, SQ_SEL_X,
1064 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1065 SETfield(sq_tex_resource4, SQ_SEL_X,
1066 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1067 SETfield(sq_tex_resource4, SQ_SEL_X,
1068 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1069 SETfield(sq_tex_resource4, SQ_SEL_X,
1070 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1071 break;
1072 case MESA_FORMAT_X8_Z24:
1073 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1074 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1075 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1076 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1077 SETfield(sq_tex_resource1, FMT_8_24,
1078 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1079 SETfield(sq_tex_resource4, SQ_SEL_X,
1080 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1081 SETfield(sq_tex_resource4, SQ_SEL_1,
1082 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1083 SETfield(sq_tex_resource4, SQ_SEL_0,
1084 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1085 SETfield(sq_tex_resource4, SQ_SEL_1,
1086 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1087 break;
1088 case MESA_FORMAT_S8_Z24:
1089 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1090 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1091 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1092 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1093 SETfield(sq_tex_resource1, FMT_8_24,
1094 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1095 SETfield(sq_tex_resource4, SQ_SEL_X,
1096 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1097 SETfield(sq_tex_resource4, SQ_SEL_Y,
1098 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1099 SETfield(sq_tex_resource4, SQ_SEL_0,
1100 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1101 SETfield(sq_tex_resource4, SQ_SEL_1,
1102 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1103 break;
1104 case MESA_FORMAT_Z24_S8:
1105 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1106 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1107 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1108 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1109 SETfield(sq_tex_resource1, FMT_24_8,
1110 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1111 SETfield(sq_tex_resource4, SQ_SEL_X,
1112 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1113 SETfield(sq_tex_resource4, SQ_SEL_Y,
1114 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1115 SETfield(sq_tex_resource4, SQ_SEL_0,
1116 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1117 SETfield(sq_tex_resource4, SQ_SEL_1,
1118 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1119 break;
1120 case MESA_FORMAT_Z32:
1121 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1122 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1123 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1124 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1125 SETfield(sq_tex_resource1, FMT_32,
1126 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1127 SETfield(sq_tex_resource4, SQ_SEL_X,
1128 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1129 SETfield(sq_tex_resource4, SQ_SEL_X,
1130 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1131 SETfield(sq_tex_resource4, SQ_SEL_X,
1132 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1133 SETfield(sq_tex_resource4, SQ_SEL_X,
1134 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1135 break;
1136 case MESA_FORMAT_S8:
1137 SETbit(sq_tex_resource0, TILE_TYPE_bit);
1138 SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1139 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1140 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1141 SETfield(sq_tex_resource1, FMT_8,
1142 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1143 SETfield(sq_tex_resource4, SQ_SEL_X,
1144 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1145 SETfield(sq_tex_resource4, SQ_SEL_X,
1146 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1147 SETfield(sq_tex_resource4, SQ_SEL_X,
1148 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1149 SETfield(sq_tex_resource4, SQ_SEL_X,
1150 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1151 break;
1152 case MESA_FORMAT_SARGB8:
1153 SETfield(sq_tex_resource1, FMT_8_8_8_8,
1154 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1155
1156 SETfield(sq_tex_resource4, SQ_SEL_Z,
1157 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1158 SETfield(sq_tex_resource4, SQ_SEL_Y,
1159 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1160 SETfield(sq_tex_resource4, SQ_SEL_X,
1161 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1162 SETfield(sq_tex_resource4, SQ_SEL_W,
1163 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1164 SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1165 break;
1166 case MESA_FORMAT_SLA8:
1167 SETfield(sq_tex_resource1, FMT_8_8,
1168 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1169
1170 SETfield(sq_tex_resource4, SQ_SEL_X,
1171 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1172 SETfield(sq_tex_resource4, SQ_SEL_X,
1173 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1174 SETfield(sq_tex_resource4, SQ_SEL_X,
1175 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1176 SETfield(sq_tex_resource4, SQ_SEL_Y,
1177 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1178 SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1179 break;
1180 case MESA_FORMAT_SL8: /* X, X, X, ONE */
1181 SETfield(sq_tex_resource1, FMT_8,
1182 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1183
1184 SETfield(sq_tex_resource4, SQ_SEL_X,
1185 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1186 SETfield(sq_tex_resource4, SQ_SEL_X,
1187 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1188 SETfield(sq_tex_resource4, SQ_SEL_X,
1189 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1190 SETfield(sq_tex_resource4, SQ_SEL_1,
1191 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1192 SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1193 break;
1194 default:
1195 fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
1196 assert("Invalid format for US output\n");
1197 return;
1198 };
1199
1200 SETfield(sq_tex_resource0, (TexelPitch/8)-1, PITCH_shift, PITCH_mask);
1201 SETfield(sq_tex_resource0, w - 1, TEX_WIDTH_shift, TEX_WIDTH_mask);
1202 SETfield(sq_tex_resource1, h - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask);
1203
1204 sq_tex_resource2 = src_offset / 256;
1205
1206 SETfield(sq_tex_resource6, SQ_TEX_VTX_VALID_TEXTURE,
1207 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
1208 SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
1209
1210 r700SyncSurf(context, bo,
1211 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
1212 0, TC_ACTION_ENA_bit);
1213
1214 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
1215 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1216 R600_OUT_BATCH(0 * 7);
1217
1218 R600_OUT_BATCH(sq_tex_resource0);
1219 R600_OUT_BATCH(sq_tex_resource1);
1220 R600_OUT_BATCH(sq_tex_resource2);
1221 R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
1222 R600_OUT_BATCH(sq_tex_resource4);
1223 R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
1224 R600_OUT_BATCH(sq_tex_resource6);
1225 R600_OUT_BATCH_RELOC(0,
1226 bo,
1227 0,
1228 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1229 R600_OUT_BATCH_RELOC(0,
1230 bo,
1231 0,
1232 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1233 END_BATCH();
1234 COMMIT_BATCH();
1235 }
1236
1237 static inline void
1238 set_tex_sampler(context_t * context)
1239 {
1240 uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
1241 int i = 0;
1242
1243 SETbit(sq_tex_sampler_word2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
1244
1245 BATCH_LOCALS(&context->radeon);
1246
1247 BEGIN_BATCH_NO_AUTOSTATE(5);
1248 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
1249 R600_OUT_BATCH(i * 3);
1250 R600_OUT_BATCH(sq_tex_sampler_word0);
1251 R600_OUT_BATCH(sq_tex_sampler_word1);
1252 R600_OUT_BATCH(sq_tex_sampler_word2);
1253 END_BATCH();
1254
1255 }
1256
1257 static inline void
1258 set_scissors(context_t *context, int x1, int y1, int x2, int y2)
1259 {
1260 BATCH_LOCALS(&context->radeon);
1261
1262 BEGIN_BATCH_NO_AUTOSTATE(17);
1263 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1264 R600_OUT_BATCH((x1 << 0) | (y1 << 16));
1265 R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1266
1267 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 3);
1268 R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1269 R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
1270 R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1271
1272 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1273 R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1274 R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1275
1276 /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1277 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL, 2 );
1278 R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1279 R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1280 END_BATCH();
1281
1282 COMMIT_BATCH();
1283
1284 }
1285
1286 static inline void
1287 set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
1288 int w, int h, int src_h, unsigned flip_y)
1289 {
1290 float *vb;
1291 radeon_bo_map(context->blit_bo, 1);
1292 vb = context->blit_bo->ptr;
1293
1294 vb[0] = (float)(dst_x);
1295 vb[1] = (float)(dst_y);
1296 vb[2] = (float)(src_x);
1297 vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
1298
1299 vb[4] = (float)(dst_x);
1300 vb[5] = (float)(dst_y + h);
1301 vb[6] = (float)(src_x);
1302 vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1303
1304 vb[8] = (float)(dst_x + w);
1305 vb[9] = (float)(dst_y + h);
1306 vb[10] = (float)(src_x + w);
1307 vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1308
1309 radeon_bo_unmap(context->blit_bo);
1310
1311 }
1312
1313 static inline void
1314 draw_auto(context_t *context)
1315 {
1316 BATCH_LOCALS(&context->radeon);
1317 uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
1318
1319 SETfield(vgt_primitive_type, DI_PT_RECTLIST,
1320 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
1321 VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
1322 SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
1323 INDEX_TYPE_mask);
1324 SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
1325 MAJOR_MODE_mask);
1326 SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
1327 SOURCE_SELECT_mask);
1328
1329 vgt_num_indices = 3;
1330
1331 BEGIN_BATCH_NO_AUTOSTATE(10);
1332 // prim
1333 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
1334 R600_OUT_BATCH(vgt_primitive_type);
1335 // index type
1336 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1337 R600_OUT_BATCH(vgt_index_type);
1338 // num instances
1339 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1340 R600_OUT_BATCH(1);
1341 //
1342 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1343 R600_OUT_BATCH(vgt_num_indices);
1344 R600_OUT_BATCH(vgt_draw_initiator);
1345
1346 END_BATCH();
1347 COMMIT_BATCH();
1348 }
1349
1350 static inline void
1351 set_default_state(context_t *context)
1352 {
1353 int ps_prio = 0;
1354 int vs_prio = 1;
1355 int gs_prio = 2;
1356 int es_prio = 3;
1357 int num_ps_gprs;
1358 int num_vs_gprs;
1359 int num_gs_gprs;
1360 int num_es_gprs;
1361 int num_temp_gprs;
1362 int num_ps_threads;
1363 int num_vs_threads;
1364 int num_gs_threads;
1365 int num_es_threads;
1366 int num_ps_stack_entries;
1367 int num_vs_stack_entries;
1368 int num_gs_stack_entries;
1369 int num_es_stack_entries;
1370 uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
1371 uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
1372 uint32_t ta_cntl_aux, db_watermarks, sq_dyn_gpr_cntl_ps_flush_req, db_debug;
1373 BATCH_LOCALS(&context->radeon);
1374
1375 switch (context->radeon.radeonScreen->chip_family) {
1376 case CHIP_FAMILY_R600:
1377 num_ps_gprs = 192;
1378 num_vs_gprs = 56;
1379 num_temp_gprs = 4;
1380 num_gs_gprs = 0;
1381 num_es_gprs = 0;
1382 num_ps_threads = 136;
1383 num_vs_threads = 48;
1384 num_gs_threads = 4;
1385 num_es_threads = 4;
1386 num_ps_stack_entries = 128;
1387 num_vs_stack_entries = 128;
1388 num_gs_stack_entries = 0;
1389 num_es_stack_entries = 0;
1390 break;
1391 case CHIP_FAMILY_RV630:
1392 case CHIP_FAMILY_RV635:
1393 num_ps_gprs = 84;
1394 num_vs_gprs = 36;
1395 num_temp_gprs = 4;
1396 num_gs_gprs = 0;
1397 num_es_gprs = 0;
1398 num_ps_threads = 144;
1399 num_vs_threads = 40;
1400 num_gs_threads = 4;
1401 num_es_threads = 4;
1402 num_ps_stack_entries = 40;
1403 num_vs_stack_entries = 40;
1404 num_gs_stack_entries = 32;
1405 num_es_stack_entries = 16;
1406 break;
1407 case CHIP_FAMILY_RV610:
1408 case CHIP_FAMILY_RV620:
1409 case CHIP_FAMILY_RS780:
1410 case CHIP_FAMILY_RS880:
1411 default:
1412 num_ps_gprs = 84;
1413 num_vs_gprs = 36;
1414 num_temp_gprs = 4;
1415 num_gs_gprs = 0;
1416 num_es_gprs = 0;
1417 num_ps_threads = 136;
1418 num_vs_threads = 48;
1419 num_gs_threads = 4;
1420 num_es_threads = 4;
1421 num_ps_stack_entries = 40;
1422 num_vs_stack_entries = 40;
1423 num_gs_stack_entries = 32;
1424 num_es_stack_entries = 16;
1425 break;
1426 case CHIP_FAMILY_RV670:
1427 num_ps_gprs = 144;
1428 num_vs_gprs = 40;
1429 num_temp_gprs = 4;
1430 num_gs_gprs = 0;
1431 num_es_gprs = 0;
1432 num_ps_threads = 136;
1433 num_vs_threads = 48;
1434 num_gs_threads = 4;
1435 num_es_threads = 4;
1436 num_ps_stack_entries = 40;
1437 num_vs_stack_entries = 40;
1438 num_gs_stack_entries = 32;
1439 num_es_stack_entries = 16;
1440 break;
1441 case CHIP_FAMILY_RV770:
1442 num_ps_gprs = 192;
1443 num_vs_gprs = 56;
1444 num_temp_gprs = 4;
1445 num_gs_gprs = 0;
1446 num_es_gprs = 0;
1447 num_ps_threads = 188;
1448 num_vs_threads = 60;
1449 num_gs_threads = 0;
1450 num_es_threads = 0;
1451 num_ps_stack_entries = 256;
1452 num_vs_stack_entries = 256;
1453 num_gs_stack_entries = 0;
1454 num_es_stack_entries = 0;
1455 break;
1456 case CHIP_FAMILY_RV730:
1457 case CHIP_FAMILY_RV740:
1458 num_ps_gprs = 84;
1459 num_vs_gprs = 36;
1460 num_temp_gprs = 4;
1461 num_gs_gprs = 0;
1462 num_es_gprs = 0;
1463 num_ps_threads = 188;
1464 num_vs_threads = 60;
1465 num_gs_threads = 0;
1466 num_es_threads = 0;
1467 num_ps_stack_entries = 128;
1468 num_vs_stack_entries = 128;
1469 num_gs_stack_entries = 0;
1470 num_es_stack_entries = 0;
1471 break;
1472 case CHIP_FAMILY_RV710:
1473 num_ps_gprs = 192;
1474 num_vs_gprs = 56;
1475 num_temp_gprs = 4;
1476 num_gs_gprs = 0;
1477 num_es_gprs = 0;
1478 num_ps_threads = 144;
1479 num_vs_threads = 48;
1480 num_gs_threads = 0;
1481 num_es_threads = 0;
1482 num_ps_stack_entries = 128;
1483 num_vs_stack_entries = 128;
1484 num_gs_stack_entries = 0;
1485 num_es_stack_entries = 0;
1486 break;
1487 }
1488
1489 sq_config = 0;
1490 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1491 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1492 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1493 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1494 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1495 CLEARbit(sq_config, VC_ENABLE_bit);
1496 else
1497 SETbit(sq_config, VC_ENABLE_bit);
1498 SETbit(sq_config, DX9_CONSTS_bit);
1499 SETbit(sq_config, ALU_INST_PREFER_VECTOR_bit);
1500 SETfield(sq_config, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1501 SETfield(sq_config, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
1502 SETfield(sq_config, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
1503 SETfield(sq_config, es_prio, ES_PRIO_shift, ES_PRIO_mask);
1504
1505 sq_gpr_resource_mgmt_1 = 0;
1506 SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1507 SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1508 SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
1509 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1510
1511 sq_gpr_resource_mgmt_2 = 0;
1512 SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1513 SETfield(sq_gpr_resource_mgmt_2, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1514
1515 sq_thread_resource_mgmt = 0;
1516 SETfield(sq_thread_resource_mgmt, num_ps_threads,
1517 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1518 SETfield(sq_thread_resource_mgmt, num_vs_threads,
1519 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1520 SETfield(sq_thread_resource_mgmt, num_gs_threads,
1521 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1522 SETfield(sq_thread_resource_mgmt, num_es_threads,
1523 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1524
1525 sq_stack_resource_mgmt_1 = 0;
1526 SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
1527 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1528 SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
1529 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1530
1531 sq_stack_resource_mgmt_2 = 0;
1532 SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
1533 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1534 SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
1535 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1536
1537 ta_cntl_aux = 0;
1538 SETfield(ta_cntl_aux, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1539 db_watermarks = 0;
1540 SETfield(db_watermarks, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1541 SETfield(db_watermarks, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1542 SETfield(db_watermarks, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1543 SETfield(db_watermarks, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1544 sq_dyn_gpr_cntl_ps_flush_req = 0;
1545 db_debug = 0;
1546 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1547 SETfield(ta_cntl_aux, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1548 db_debug = 0x82000000;
1549 SETfield(db_watermarks, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1550 } else {
1551 SETfield(ta_cntl_aux, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1552 SETfield(db_watermarks, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1553 SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
1554 }
1555
1556 BEGIN_BATCH_NO_AUTOSTATE(120);
1557 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
1558 R600_OUT_BATCH(sq_config);
1559 R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
1560 R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
1561 R600_OUT_BATCH(sq_thread_resource_mgmt);
1562 R600_OUT_BATCH(sq_stack_resource_mgmt_1);
1563 R600_OUT_BATCH(sq_stack_resource_mgmt_2);
1564
1565 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, ta_cntl_aux);
1566 R600_OUT_BATCH_REGVAL(VC_ENHANCE, 0);
1567 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, sq_dyn_gpr_cntl_ps_flush_req);
1568 R600_OUT_BATCH_REGVAL(DB_DEBUG, db_debug);
1569 R600_OUT_BATCH_REGVAL(DB_WATERMARKS, db_watermarks);
1570
1571 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
1572 R600_OUT_BATCH(0);
1573 R600_OUT_BATCH(0);
1574 R600_OUT_BATCH(0);
1575 R600_OUT_BATCH(0);
1576 R600_OUT_BATCH(0);
1577 R600_OUT_BATCH(0);
1578 R600_OUT_BATCH(0);
1579 R600_OUT_BATCH(0);
1580 R600_OUT_BATCH(0);
1581
1582 R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL,
1583 (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
1584 R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
1585 R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
1586 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
1587 R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
1588 R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
1589 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
1590 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, (0xcc << ROP3_shift));
1591
1592 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, VTX_XY_FMT_bit);
1593 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, 0);
1594 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, CLIP_DISABLE_bit);
1595 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, (FACE_bit) |
1596 (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) |
1597 (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift));
1598 R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL, (PIX_CENTER_bit) |
1599 (X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
1600 (X_1_256TH << QUANT_MODE_shift));
1601 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, 0);
1602
1603 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1604 R600_OUT_BATCH(0xffffff);
1605 R600_OUT_BATCH(0);
1606 R600_OUT_BATCH(0);
1607 R600_OUT_BATCH(0);
1608
1609 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1610 R600_OUT_BATCH(0);
1611 R600_OUT_BATCH(0);
1612 R600_OUT_BATCH(0);
1613 R600_OUT_BATCH(0);
1614 R600_OUT_BATCH(0);
1615 R600_OUT_BATCH(0);
1616 R600_OUT_BATCH(0);
1617 R600_OUT_BATCH(0);
1618 R600_OUT_BATCH(0);
1619 R600_OUT_BATCH(0);
1620 R600_OUT_BATCH(0);
1621 R600_OUT_BATCH(0);
1622 R600_OUT_BATCH(0);
1623
1624 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, 0);
1625 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, 0);
1626 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, 0);
1627 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, 0);
1628
1629 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1630 R600_OUT_BATCH(0);
1631 R600_OUT_BATCH(0);
1632 R600_OUT_BATCH(0);
1633
1634 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, 0);
1635 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, 0);
1636
1637 END_BATCH();
1638 COMMIT_BATCH();
1639 }
1640
1641 static GLboolean validate_buffers(context_t *rmesa,
1642 struct radeon_bo *src_bo,
1643 struct radeon_bo *dst_bo)
1644 {
1645 int ret;
1646
1647 radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
1648
1649 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1650 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
1651 if (ret)
1652 return GL_FALSE;
1653
1654 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1655 dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
1656 if (ret)
1657 return GL_FALSE;
1658
1659 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1660 rmesa->blit_bo,
1661 RADEON_GEM_DOMAIN_GTT, 0);
1662 if (ret)
1663 return GL_FALSE;
1664
1665 return GL_TRUE;
1666 }
1667
1668 unsigned r600_blit(struct gl_context *ctx,
1669 struct radeon_bo *src_bo,
1670 intptr_t src_offset,
1671 gl_format src_mesaformat,
1672 unsigned src_pitch,
1673 unsigned src_width,
1674 unsigned src_height,
1675 unsigned src_x,
1676 unsigned src_y,
1677 struct radeon_bo *dst_bo,
1678 intptr_t dst_offset,
1679 gl_format dst_mesaformat,
1680 unsigned dst_pitch,
1681 unsigned dst_width,
1682 unsigned dst_height,
1683 unsigned dst_x,
1684 unsigned dst_y,
1685 unsigned w,
1686 unsigned h,
1687 unsigned flip_y)
1688 {
1689 context_t *context = R700_CONTEXT(ctx);
1690 int id = 0;
1691
1692 if (!r600_check_blit(dst_mesaformat))
1693 return GL_FALSE;
1694
1695 if (src_bo == dst_bo) {
1696 return GL_FALSE;
1697 }
1698
1699 if (src_offset % 256 || dst_offset % 256) {
1700 return GL_FALSE;
1701 }
1702
1703 if (0) {
1704 fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1705 src_width, src_height, src_pitch,
1706 _mesa_format_row_stride(src_mesaformat, src_width),
1707 _mesa_get_format_name(src_mesaformat));
1708 fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
1709 dst_width, dst_height,
1710 _mesa_format_row_stride(dst_mesaformat, dst_width),
1711 _mesa_get_format_name(dst_mesaformat));
1712 }
1713
1714 /* Flush is needed to make sure that source buffer has correct data */
1715 radeonFlush(ctx);
1716
1717 rcommonEnsureCmdBufSpace(&context->radeon, 311, __FUNCTION__);
1718
1719 /* load shaders */
1720 load_shaders(context->radeon.glCtx);
1721
1722 if (!validate_buffers(context, src_bo, dst_bo))
1723 return GL_FALSE;
1724
1725 /* set clear state */
1726 /* 120 */
1727 set_default_state(context);
1728
1729 /* shaders */
1730 /* 72 */
1731 set_shaders(context);
1732
1733 /* src */
1734 /* 20 */
1735 set_tex_resource(context, src_mesaformat, src_bo,
1736 src_width, src_height, src_pitch, src_offset);
1737
1738 /* 5 */
1739 set_tex_sampler(context);
1740
1741 /* dst */
1742 /* 31 */
1743 set_render_target(context, dst_bo, dst_mesaformat,
1744 dst_pitch, dst_width, dst_height, dst_offset);
1745 /* scissors */
1746 /* 17 */
1747 set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
1748
1749 set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
1750 /* Vertex buffer setup */
1751 /* 24 */
1752 set_vtx_resource(context);
1753
1754 /* draw */
1755 /* 10 */
1756 draw_auto(context);
1757
1758 /* 7 */
1759 r700SyncSurf(context, dst_bo, 0,
1760 RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
1761 CB_ACTION_ENA_bit | (1 << (id + 6)));
1762
1763 /* 5 */
1764 /* XXX drm should handle this in fence submit */
1765 r700WaitForIdleClean(context);
1766
1767 radeonFlush(ctx);
1768
1769 return GL_TRUE;
1770 }