src/mesa/drivers/dri/r600/r600_blit.c

   1 /*
   2  * Copyright (C) 2009 Advanced Micro Devices, Inc.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r600_context.h"
  30
  31 #include "r600_blit.h"
  32 #include "r600_blit_shaders.h"
  33 #include "r600_cmdbuf.h"
  34
  35 /* common formats supported as both textures and render targets */
  36 static unsigned is_blit_supported(gl_format mesa_format)
  37 {
  38     switch (mesa_format) {
  39     case MESA_FORMAT_RGBA8888:
  40     case MESA_FORMAT_SIGNED_RGBA8888:
  41     case MESA_FORMAT_RGBA8888_REV:
  42     case MESA_FORMAT_SIGNED_RGBA8888_REV:
  43     case MESA_FORMAT_ARGB8888:
  44     case MESA_FORMAT_XRGB8888:
  45     case MESA_FORMAT_ARGB8888_REV:
  46     case MESA_FORMAT_XRGB8888_REV:
  47     case MESA_FORMAT_RGB565:
  48     case MESA_FORMAT_RGB565_REV:
  49     case MESA_FORMAT_ARGB4444:
  50     case MESA_FORMAT_ARGB4444_REV:
  51     case MESA_FORMAT_ARGB1555:
  52     case MESA_FORMAT_ARGB1555_REV:
  53     case MESA_FORMAT_AL88:
  54     case MESA_FORMAT_AL88_REV:
  55     case MESA_FORMAT_RGB332:
  56     case MESA_FORMAT_A8:
  57     case MESA_FORMAT_I8:
  58     case MESA_FORMAT_CI8:
  59     case MESA_FORMAT_L8:
  60     case MESA_FORMAT_RGBA_FLOAT32:
  61     case MESA_FORMAT_RGBA_FLOAT16:
  62     case MESA_FORMAT_ALPHA_FLOAT32:
  63     case MESA_FORMAT_ALPHA_FLOAT16:
  64     case MESA_FORMAT_LUMINANCE_FLOAT32:
  65     case MESA_FORMAT_LUMINANCE_FLOAT16:
  66     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
  67     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
  68     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
  69     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
  70     case MESA_FORMAT_X8_Z24:
  71     case MESA_FORMAT_S8_Z24:
  72     case MESA_FORMAT_Z24_S8:
  73     case MESA_FORMAT_Z16:
  74     case MESA_FORMAT_Z32:
  75     case MESA_FORMAT_SRGBA8:
  76     case MESA_FORMAT_SLA8:
  77     case MESA_FORMAT_SL8:
  78             break;
  79     default:
  80             return 0;
  81     }
  82
  83     /* ??? */
  84     /* not sure blit to depth works or not yet */
  85     if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
  86             return 0;
  87
  88     return 1;
  89 }
  90
  91 static inline void
  92 set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
  93                   int pitch, int w, int h, intptr_t dst_offset)
  94 {
  95     uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
  96     int nPitchInPixel, id = 0;
  97     uint32_t comp_swap, format, bpp = _mesa_get_format_bytes(mesa_format);
  98     BATCH_LOCALS(&context->radeon);
  99
 100     cb_color0_base = dst_offset / 256;
 101
 102     nPitchInPixel = pitch/bpp;
 103     SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
 104              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
 105     SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
 106              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
 107
 108     SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
 109     SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
 110              CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 111
 112     SETbit(cb_color0_info, BLEND_BYPASS_bit);
 113
 114     switch(mesa_format) {
 115     case MESA_FORMAT_RGBA8888:
 116             format = COLOR_8_8_8_8;
 117             comp_swap = SWAP_STD_REV;
 118             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 119             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 120             break;
 121     case MESA_FORMAT_SIGNED_RGBA8888:
 122             format = COLOR_8_8_8_8;
 123             comp_swap = SWAP_STD_REV;
 124             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 125             SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 126             break;
 127     case MESA_FORMAT_RGBA8888_REV:
 128             format = COLOR_8_8_8_8;
 129             comp_swap = SWAP_STD;
 130             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 131             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 132             break;
 133     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 134             format = COLOR_8_8_8_8;
 135             comp_swap = SWAP_STD;
 136             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 137             SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 138             break;
 139     case MESA_FORMAT_ARGB8888:
 140     case MESA_FORMAT_XRGB8888:
 141             format = COLOR_8_8_8_8;
 142             comp_swap = SWAP_ALT;
 143             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 144             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 145             break;
 146     case MESA_FORMAT_ARGB8888_REV:
 147     case MESA_FORMAT_XRGB8888_REV:
 148             format = COLOR_8_8_8_8;
 149             comp_swap = SWAP_ALT_REV;
 150             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 151             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 152             break;
 153     case MESA_FORMAT_RGB565:
 154             format = COLOR_5_6_5;
 155             comp_swap = SWAP_STD_REV;
 156             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 157             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 158             break;
 159     case MESA_FORMAT_RGB565_REV:
 160             format = COLOR_5_6_5;
 161             comp_swap = SWAP_STD;
 162             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 163             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 164             break;
 165     case MESA_FORMAT_ARGB4444:
 166             format = COLOR_4_4_4_4;
 167             comp_swap = SWAP_ALT;
 168             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 169             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 170             break;
 171     case MESA_FORMAT_ARGB4444_REV:
 172             format = COLOR_4_4_4_4;
 173             comp_swap = SWAP_ALT_REV;
 174             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 175             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 176             break;
 177     case MESA_FORMAT_ARGB1555:
 178             format = COLOR_1_5_5_5;
 179             comp_swap = SWAP_ALT;
 180             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 181             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 182             break;
 183     case MESA_FORMAT_ARGB1555_REV:
 184             format = COLOR_1_5_5_5;
 185             comp_swap = SWAP_ALT_REV;
 186             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 187             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 188             break;
 189     case MESA_FORMAT_AL88:
 190             format = COLOR_8_8;
 191             comp_swap = SWAP_STD;
 192             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 193             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 194             break;
 195     case MESA_FORMAT_AL88_REV:
 196             format = COLOR_8_8;
 197             comp_swap = SWAP_STD_REV;
 198             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 199             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 200             break;
 201     case MESA_FORMAT_RGB332:
 202             format = COLOR_3_3_2;
 203             comp_swap = SWAP_STD_REV;
 204             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 205             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 206             break;
 207     case MESA_FORMAT_A8:
 208             format = COLOR_8;
 209             comp_swap = SWAP_ALT_REV;
 210             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 211             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 212             break;
 213     case MESA_FORMAT_I8:
 214     case MESA_FORMAT_CI8:
 215             format = COLOR_8;
 216             comp_swap = SWAP_STD;
 217             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 218             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 219             break;
 220     case MESA_FORMAT_L8:
 221             format = COLOR_8;
 222             comp_swap = SWAP_ALT;
 223             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 224             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 225             break;
 226     case MESA_FORMAT_RGBA_FLOAT32:
 227             format = COLOR_32_32_32_32_FLOAT;
 228             comp_swap = SWAP_STD_REV;
 229             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 230             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 231             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 232             break;
 233     case MESA_FORMAT_RGBA_FLOAT16:
 234             format = COLOR_16_16_16_16_FLOAT;
 235             comp_swap = SWAP_STD_REV;
 236             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 237             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 238             break;
 239     case MESA_FORMAT_ALPHA_FLOAT32:
 240             format = COLOR_32_FLOAT;
 241             comp_swap = SWAP_ALT_REV;
 242             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 243             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 244             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 245             break;
 246     case MESA_FORMAT_ALPHA_FLOAT16:
 247             format = COLOR_16_FLOAT;
 248             comp_swap = SWAP_ALT_REV;
 249             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 250             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 251             break;
 252     case MESA_FORMAT_LUMINANCE_FLOAT32:
 253             format = COLOR_32_FLOAT;
 254             comp_swap = SWAP_ALT;
 255             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 256             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 257             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 258             break;
 259     case MESA_FORMAT_LUMINANCE_FLOAT16:
 260             format = COLOR_16_FLOAT;
 261             comp_swap = SWAP_ALT;
 262             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 263             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 264             break;
 265     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 266             format = COLOR_32_32_FLOAT;
 267             comp_swap = SWAP_ALT_REV;
 268             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 269             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 270             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 271             break;
 272     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 273             format = COLOR_16_16_FLOAT;
 274             comp_swap = SWAP_ALT_REV;
 275             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 276             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 277             break;
 278     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 279             format = COLOR_32_FLOAT;
 280             comp_swap = SWAP_STD;
 281             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 282             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 283             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 284             break;
 285     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 286             format = COLOR_16_FLOAT;
 287             comp_swap = SWAP_STD;
 288             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 289             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 290             break;
 291     case MESA_FORMAT_X8_Z24:
 292     case MESA_FORMAT_S8_Z24:
 293             format = COLOR_8_24;
 294             comp_swap = SWAP_STD;
 295             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 296                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 297             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 298             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 299             break;
 300     case MESA_FORMAT_Z24_S8:
 301             format = COLOR_24_8;
 302             comp_swap = SWAP_STD;
 303             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 304                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 305             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 306             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 307             break;
 308     case MESA_FORMAT_Z16:
 309             format = COLOR_16;
 310             comp_swap = SWAP_STD;
 311             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 312                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 313             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 314             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 315             break;
 316     case MESA_FORMAT_Z32:
 317             format = COLOR_32;
 318             comp_swap = SWAP_STD;
 319             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 320                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 321             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 322             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 323             break;
 324     case MESA_FORMAT_SRGBA8:
 325             format = COLOR_8_8_8_8;
 326             comp_swap = SWAP_STD_REV;
 327             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 328             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 329             break;
 330     case MESA_FORMAT_SLA8:
 331             format = COLOR_8_8;
 332             comp_swap = SWAP_ALT_REV;
 333             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 334             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 335             break;
 336     case MESA_FORMAT_SL8:
 337             format = COLOR_8;
 338             comp_swap = SWAP_ALT_REV;
 339             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 340             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 341             break;
 342     default:
 343             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
 344             assert("Invalid format for US output\n");
 345             return;
 346     }
 347
 348     SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
 349              CB_COLOR0_INFO__FORMAT_mask);
 350     SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
 351
 352     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 353     R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
 354     R600_OUT_BATCH(cb_color0_base);
 355     R600_OUT_BATCH_RELOC(0,
 356                          bo,
 357                          0,
 358                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 359     END_BATCH();
 360
 361     if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 362         (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 363             BEGIN_BATCH_NO_AUTOSTATE(2);
 364             R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
 365             R600_OUT_BATCH((2 << id));
 366             END_BATCH();
 367     }
 368
 369     /* Set CMASK & TILE buffer to the offset of color buffer as
 370      * we don't use those this shouldn't cause any issue and we
 371      * then have a valid cmd stream
 372      */
 373     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 374     R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
 375     R600_OUT_BATCH(cb_color0_base);
 376     R600_OUT_BATCH_RELOC(0,
 377                          bo,
 378                          0,
 379                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 380     END_BATCH();
 381     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 382     R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
 383     R600_OUT_BATCH(cb_color0_base);
 384     R600_OUT_BATCH_RELOC(0,
 385                          bo,
 386                          0,
 387                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 388     END_BATCH();
 389
 390     BEGIN_BATCH_NO_AUTOSTATE(12);
 391     R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
 392     R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
 393     R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
 394     R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
 395     END_BATCH();
 396
 397     COMMIT_BATCH();
 398
 399 }
 400
 401 static inline void load_shaders(GLcontext * ctx)
 402 {
 403
 404     radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
 405     context_t *context = R700_CONTEXT(ctx);
 406     int i, size;
 407     uint32_t *shader;
 408
 409     if (context->blit_bo_loaded == 1)
 410         return;
 411
 412     size = 4096;
 413     context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
 414                                       size, 256, RADEON_GEM_DOMAIN_GTT, 0);
 415     radeon_bo_map(context->blit_bo, 1);
 416     shader = context->blit_bo->ptr;
 417
 418     for(i=0; i<sizeof(r6xx_vs)/4; i++) {
 419         shader[128+i] = r6xx_vs[i];
 420     }
 421     for(i=0; i<sizeof(r6xx_ps)/4; i++) {
 422         shader[256+i] = r6xx_ps[i];
 423     }
 424
 425     radeon_bo_unmap(context->blit_bo);
 426     context->blit_bo_loaded = 1;
 427
 428 }
 429
 430 static inline void
 431 set_shaders(context_t *context)
 432 {
 433     struct radeon_bo * pbo = context->blit_bo;
 434     BATCH_LOCALS(&context->radeon);
 435
 436     uint32_t sq_pgm_start_fs = (512 >> 8);
 437     uint32_t sq_pgm_resources_fs = 0;
 438     uint32_t sq_pgm_cf_offset_fs = 0;
 439
 440     uint32_t sq_pgm_start_vs = (512 >> 8);
 441     uint32_t sq_pgm_resources_vs = (1 << NUM_GPRS_shift);
 442     uint32_t sq_pgm_cf_offset_vs = 0;
 443
 444     uint32_t sq_pgm_start_ps = (1024 >> 8);
 445     uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
 446     uint32_t sq_pgm_cf_offset_ps = 0;
 447     uint32_t sq_pgm_exports_ps = (1 << 1);
 448
 449     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 450
 451     /* FS */
 452     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 453     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
 454     R600_OUT_BATCH(sq_pgm_start_fs);
 455     R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
 456                          pbo,
 457                          sq_pgm_start_fs,
 458                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 459     END_BATCH();
 460
 461     BEGIN_BATCH_NO_AUTOSTATE(6);
 462     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
 463     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, sq_pgm_cf_offset_fs);
 464     END_BATCH();
 465
 466     /* VS */
 467     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 468     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
 469     R600_OUT_BATCH(sq_pgm_start_vs);
 470     R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
 471                          pbo,
 472                          sq_pgm_start_vs,
 473                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 474     END_BATCH();
 475
 476     BEGIN_BATCH_NO_AUTOSTATE(6);
 477     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, sq_pgm_resources_vs);
 478     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, sq_pgm_cf_offset_vs);
 479     END_BATCH();
 480
 481     /* PS */
 482     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 483     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
 484     R600_OUT_BATCH(sq_pgm_start_ps);
 485     R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
 486                          pbo,
 487                          sq_pgm_start_ps,
 488                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 489     END_BATCH();
 490
 491     BEGIN_BATCH_NO_AUTOSTATE(9);
 492     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, sq_pgm_resources_ps);
 493     R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, sq_pgm_exports_ps);
 494     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, sq_pgm_cf_offset_ps);
 495     END_BATCH();
 496
 497     BEGIN_BATCH_NO_AUTOSTATE(18);
 498     R600_OUT_BATCH_REGVAL(SPI_VS_OUT_CONFIG, 0); //EXPORT_COUNT is - 1
 499     R600_OUT_BATCH_REGVAL(SPI_VS_OUT_ID_0, 0);
 500     R600_OUT_BATCH_REGVAL(SPI_PS_INPUT_CNTL_0, SEL_CENTROID_bit);
 501     R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_0, (1 << NUM_INTERP_shift));
 502     R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_1, 0);
 503     R600_OUT_BATCH_REGVAL(SPI_INTERP_CONTROL_0, 0);
 504     END_BATCH();
 505
 506     COMMIT_BATCH();
 507
 508 }
 509
 510 static inline void
 511 set_vtx_resource(context_t *context)
 512 {
 513     struct radeon_bo *bo = context->blit_bo;
 514     BATCH_LOCALS(&context->radeon);
 515
 516     BEGIN_BATCH_NO_AUTOSTATE(6);
 517     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 518     R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
 519     R600_OUT_BATCH(0);
 520
 521     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 522     R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
 523     R600_OUT_BATCH(0);
 524     END_BATCH();
 525     COMMIT_BATCH();
 526
 527     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 528         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 529         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
 530         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
 531         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
 532             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
 533     else
 534             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
 535
 536     BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 537
 538     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 539     R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
 540     R600_OUT_BATCH(0);
 541     R600_OUT_BATCH(48 - 1);
 542     R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
 543     R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
 544     R600_OUT_BATCH(0);
 545     R600_OUT_BATCH(0);
 546     R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
 547     R600_OUT_BATCH_RELOC(SQ_VTX_CONSTANT_WORD0_0,
 548                          bo,
 549                          SQ_VTX_CONSTANT_WORD0_0,
 550                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 551     END_BATCH();
 552     COMMIT_BATCH();
 553
 554 }
 555
 556 static inline void
 557 set_tex_resource(context_t * context,
 558                  gl_format mesa_format, struct radeon_bo *bo, int w, int h,
 559                  int pitch, intptr_t src_offset)
 560 {
 561     uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource6;
 562     int bpp = _mesa_get_format_bytes(mesa_format);
 563     int TexelPitch = pitch/bpp;
 564
 565     sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource6 = 0;
 566     BATCH_LOCALS(&context->radeon);
 567
 568     SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
 569     SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
 570                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 571                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 572
 573     switch (mesa_format) {
 574     case MESA_FORMAT_RGBA8888:
 575     case MESA_FORMAT_SIGNED_RGBA8888:
 576             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 577                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 578
 579             SETfield(sq_tex_resource4, SQ_SEL_W,
 580                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 581             SETfield(sq_tex_resource4, SQ_SEL_Z,
 582                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 583             SETfield(sq_tex_resource4, SQ_SEL_Y,
 584                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 585             SETfield(sq_tex_resource4, SQ_SEL_X,
 586                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 587             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
 588                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 589                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 590                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 591                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 592                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 593                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 594                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 595                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 596             }
 597             break;
 598     case MESA_FORMAT_RGBA8888_REV:
 599     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 600             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 601                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 602
 603             SETfield(sq_tex_resource4, SQ_SEL_X,
 604                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 605             SETfield(sq_tex_resource4, SQ_SEL_Y,
 606                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 607             SETfield(sq_tex_resource4, SQ_SEL_Z,
 608                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 609             SETfield(sq_tex_resource4, SQ_SEL_W,
 610                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 611             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
 612                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 613                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 614                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 615                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 616                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 617                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 618                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 619                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 620             }
 621             break;
 622     case MESA_FORMAT_ARGB8888:
 623             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 624                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 625
 626             SETfield(sq_tex_resource4, SQ_SEL_Z,
 627                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 628             SETfield(sq_tex_resource4, SQ_SEL_Y,
 629                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 630             SETfield(sq_tex_resource4, SQ_SEL_X,
 631                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 632             SETfield(sq_tex_resource4, SQ_SEL_W,
 633                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 634             break;
 635     case MESA_FORMAT_XRGB8888:
 636             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 637                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 638
 639             SETfield(sq_tex_resource4, SQ_SEL_Z,
 640                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 641             SETfield(sq_tex_resource4, SQ_SEL_Y,
 642                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 643             SETfield(sq_tex_resource4, SQ_SEL_X,
 644                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 645             SETfield(sq_tex_resource4, SQ_SEL_1,
 646                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 647             break;
 648     case MESA_FORMAT_ARGB8888_REV:
 649             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 650                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 651
 652             SETfield(sq_tex_resource4, SQ_SEL_Y,
 653                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 654             SETfield(sq_tex_resource4, SQ_SEL_Z,
 655                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 656             SETfield(sq_tex_resource4, SQ_SEL_W,
 657                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 658             SETfield(sq_tex_resource4, SQ_SEL_X,
 659                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 660             break;
 661     case MESA_FORMAT_XRGB8888_REV:
 662             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 663                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 664
 665             SETfield(sq_tex_resource4, SQ_SEL_1,
 666                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 667             SETfield(sq_tex_resource4, SQ_SEL_Z,
 668                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 669             SETfield(sq_tex_resource4, SQ_SEL_W,
 670                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 671             SETfield(sq_tex_resource4, SQ_SEL_X,
 672                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 673             break;
 674     case MESA_FORMAT_RGB565:
 675             SETfield(sq_tex_resource1, FMT_5_6_5,
 676                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 677
 678             SETfield(sq_tex_resource4, SQ_SEL_Z,
 679                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 680             SETfield(sq_tex_resource4, SQ_SEL_Y,
 681                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 682             SETfield(sq_tex_resource4, SQ_SEL_X,
 683                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 684             SETfield(sq_tex_resource4, SQ_SEL_1,
 685                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 686             break;
 687     case MESA_FORMAT_RGB565_REV:
 688             SETfield(sq_tex_resource1, FMT_5_6_5,
 689                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 690
 691             SETfield(sq_tex_resource4, SQ_SEL_X,
 692                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 693             SETfield(sq_tex_resource4, SQ_SEL_Y,
 694                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 695             SETfield(sq_tex_resource4, SQ_SEL_Z,
 696                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 697             SETfield(sq_tex_resource4, SQ_SEL_1,
 698                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 699             break;
 700     case MESA_FORMAT_ARGB4444:
 701             SETfield(sq_tex_resource1, FMT_4_4_4_4,
 702                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 703
 704             SETfield(sq_tex_resource4, SQ_SEL_Z,
 705                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 706             SETfield(sq_tex_resource4, SQ_SEL_Y,
 707                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 708             SETfield(sq_tex_resource4, SQ_SEL_X,
 709                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 710             SETfield(sq_tex_resource4, SQ_SEL_W,
 711                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 712             break;
 713     case MESA_FORMAT_ARGB4444_REV:
 714             SETfield(sq_tex_resource1, FMT_4_4_4_4,
 715                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 716
 717             SETfield(sq_tex_resource4, SQ_SEL_Y,
 718                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 719             SETfield(sq_tex_resource4, SQ_SEL_Z,
 720                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 721             SETfield(sq_tex_resource4, SQ_SEL_W,
 722                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 723             SETfield(sq_tex_resource4, SQ_SEL_X,
 724                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 725             break;
 726     case MESA_FORMAT_ARGB1555:
 727             SETfield(sq_tex_resource1, FMT_1_5_5_5,
 728                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 729
 730             SETfield(sq_tex_resource4, SQ_SEL_Z,
 731                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 732             SETfield(sq_tex_resource4, SQ_SEL_Y,
 733                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 734             SETfield(sq_tex_resource4, SQ_SEL_X,
 735                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 736             SETfield(sq_tex_resource4, SQ_SEL_W,
 737                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 738             break;
 739     case MESA_FORMAT_ARGB1555_REV:
 740             SETfield(sq_tex_resource1, FMT_1_5_5_5,
 741                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 742
 743             SETfield(sq_tex_resource4, SQ_SEL_Y,
 744                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 745             SETfield(sq_tex_resource4, SQ_SEL_Z,
 746                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 747             SETfield(sq_tex_resource4, SQ_SEL_W,
 748                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 749             SETfield(sq_tex_resource4, SQ_SEL_X,
 750                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 751             break;
 752     case MESA_FORMAT_AL88:
 753     case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
 754             SETfield(sq_tex_resource1, FMT_8_8,
 755                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 756
 757             SETfield(sq_tex_resource4, SQ_SEL_X,
 758                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 759             SETfield(sq_tex_resource4, SQ_SEL_X,
 760                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 761             SETfield(sq_tex_resource4, SQ_SEL_X,
 762                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 763             SETfield(sq_tex_resource4, SQ_SEL_Y,
 764                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 765             break;
 766     case MESA_FORMAT_RGB332:
 767             SETfield(sq_tex_resource1, FMT_3_3_2,
 768                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 769
 770             SETfield(sq_tex_resource4, SQ_SEL_Z,
 771                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 772             SETfield(sq_tex_resource4, SQ_SEL_Y,
 773                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 774             SETfield(sq_tex_resource4, SQ_SEL_X,
 775                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 776             SETfield(sq_tex_resource4, SQ_SEL_1,
 777                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 778             break;
 779     case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
 780             SETfield(sq_tex_resource1, FMT_8,
 781                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 782
 783             SETfield(sq_tex_resource4, SQ_SEL_0,
 784                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 785             SETfield(sq_tex_resource4, SQ_SEL_0,
 786                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 787             SETfield(sq_tex_resource4, SQ_SEL_0,
 788                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 789             SETfield(sq_tex_resource4, SQ_SEL_X,
 790                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 791             break;
 792     case MESA_FORMAT_L8: /* X, X, X, ONE */
 793             SETfield(sq_tex_resource1, FMT_8,
 794                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 795
 796             SETfield(sq_tex_resource4, SQ_SEL_X,
 797                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 798             SETfield(sq_tex_resource4, SQ_SEL_X,
 799                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 800             SETfield(sq_tex_resource4, SQ_SEL_X,
 801                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 802             SETfield(sq_tex_resource4, SQ_SEL_1,
 803                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 804             break;
 805     case MESA_FORMAT_I8: /* X, X, X, X */
 806     case MESA_FORMAT_CI8:
 807             SETfield(sq_tex_resource1, FMT_8,
 808                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 809
 810             SETfield(sq_tex_resource4, SQ_SEL_X,
 811                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 812             SETfield(sq_tex_resource4, SQ_SEL_X,
 813                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 814             SETfield(sq_tex_resource4, SQ_SEL_X,
 815                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 816             SETfield(sq_tex_resource4, SQ_SEL_X,
 817                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 818             break;
 819     case MESA_FORMAT_RGBA_FLOAT32:
 820             SETfield(sq_tex_resource1, FMT_32_32_32_32_FLOAT,
 821                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 822
 823             SETfield(sq_tex_resource4, SQ_SEL_X,
 824                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 825             SETfield(sq_tex_resource4, SQ_SEL_Y,
 826                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 827             SETfield(sq_tex_resource4, SQ_SEL_Z,
 828                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 829             SETfield(sq_tex_resource4, SQ_SEL_W,
 830                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 831             break;
 832     case MESA_FORMAT_RGBA_FLOAT16:
 833             SETfield(sq_tex_resource1, FMT_16_16_16_16_FLOAT,
 834                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 835
 836             SETfield(sq_tex_resource4, SQ_SEL_X,
 837                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 838             SETfield(sq_tex_resource4, SQ_SEL_Y,
 839                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 840             SETfield(sq_tex_resource4, SQ_SEL_Z,
 841                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 842             SETfield(sq_tex_resource4, SQ_SEL_W,
 843                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 844             break;
 845     case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
 846             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 847                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 848
 849             SETfield(sq_tex_resource4, SQ_SEL_0,
 850                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 851             SETfield(sq_tex_resource4, SQ_SEL_0,
 852                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 853             SETfield(sq_tex_resource4, SQ_SEL_0,
 854                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 855             SETfield(sq_tex_resource4, SQ_SEL_X,
 856                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 857             break;
 858     case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
 859             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 860                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 861
 862             SETfield(sq_tex_resource4, SQ_SEL_0,
 863                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 864             SETfield(sq_tex_resource4, SQ_SEL_0,
 865                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 866             SETfield(sq_tex_resource4, SQ_SEL_0,
 867                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 868             SETfield(sq_tex_resource4, SQ_SEL_X,
 869                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 870             break;
 871     case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
 872             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 873                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 874
 875             SETfield(sq_tex_resource4, SQ_SEL_X,
 876                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 877             SETfield(sq_tex_resource4, SQ_SEL_X,
 878                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 879             SETfield(sq_tex_resource4, SQ_SEL_X,
 880                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 881             SETfield(sq_tex_resource4, SQ_SEL_1,
 882                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 883             break;
 884     case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
 885             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 886                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 887
 888             SETfield(sq_tex_resource4, SQ_SEL_X,
 889                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 890             SETfield(sq_tex_resource4, SQ_SEL_X,
 891                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 892             SETfield(sq_tex_resource4, SQ_SEL_X,
 893                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 894             SETfield(sq_tex_resource4, SQ_SEL_1,
 895                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 896             break;
 897     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 898             SETfield(sq_tex_resource1, FMT_32_32_FLOAT,
 899                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 900
 901             SETfield(sq_tex_resource4, SQ_SEL_X,
 902                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 903             SETfield(sq_tex_resource4, SQ_SEL_X,
 904                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 905             SETfield(sq_tex_resource4, SQ_SEL_X,
 906                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 907             SETfield(sq_tex_resource4, SQ_SEL_Y,
 908                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 909             break;
 910     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 911             SETfield(sq_tex_resource1, FMT_16_16_FLOAT,
 912                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 913
 914             SETfield(sq_tex_resource4, SQ_SEL_X,
 915                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 916             SETfield(sq_tex_resource4, SQ_SEL_X,
 917                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 918             SETfield(sq_tex_resource4, SQ_SEL_X,
 919                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 920             SETfield(sq_tex_resource4, SQ_SEL_Y,
 921                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 922             break;
 923     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 924             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 925                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 926
 927             SETfield(sq_tex_resource4, SQ_SEL_X,
 928                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 929             SETfield(sq_tex_resource4, SQ_SEL_X,
 930                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 931             SETfield(sq_tex_resource4, SQ_SEL_X,
 932                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 933             SETfield(sq_tex_resource4, SQ_SEL_X,
 934                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 935             break;
 936     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 937             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 938                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 939
 940             SETfield(sq_tex_resource4, SQ_SEL_X,
 941                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 942             SETfield(sq_tex_resource4, SQ_SEL_X,
 943                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 944             SETfield(sq_tex_resource4, SQ_SEL_X,
 945                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 946             SETfield(sq_tex_resource4, SQ_SEL_X,
 947                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 948             break;
 949     case MESA_FORMAT_Z16:
 950             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 951             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 952                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 953                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 954             SETfield(sq_tex_resource1, FMT_16,
 955                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 956             SETfield(sq_tex_resource4, SQ_SEL_X,
 957                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 958             SETfield(sq_tex_resource4, SQ_SEL_X,
 959                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 960             SETfield(sq_tex_resource4, SQ_SEL_X,
 961                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 962             SETfield(sq_tex_resource4, SQ_SEL_X,
 963                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 964             break;
 965     case MESA_FORMAT_X8_Z24:
 966             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 967             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 968                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 969                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 970             SETfield(sq_tex_resource1, FMT_8_24,
 971                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 972             SETfield(sq_tex_resource4, SQ_SEL_X,
 973                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 974             SETfield(sq_tex_resource4, SQ_SEL_1,
 975                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 976             SETfield(sq_tex_resource4, SQ_SEL_0,
 977                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 978             SETfield(sq_tex_resource4, SQ_SEL_1,
 979                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 980             break;
 981     case MESA_FORMAT_S8_Z24:
 982             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 983             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 984                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 985                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 986             SETfield(sq_tex_resource1, FMT_8_24,
 987                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 988             SETfield(sq_tex_resource4, SQ_SEL_X,
 989                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 990             SETfield(sq_tex_resource4, SQ_SEL_Y,
 991                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 992             SETfield(sq_tex_resource4, SQ_SEL_0,
 993                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 994             SETfield(sq_tex_resource4, SQ_SEL_1,
 995                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 996             break;
 997     case MESA_FORMAT_Z24_S8:
 998             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 999             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1000                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1001                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1002             SETfield(sq_tex_resource1, FMT_24_8,
1003                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1004             SETfield(sq_tex_resource4, SQ_SEL_X,
1005                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1006             SETfield(sq_tex_resource4, SQ_SEL_Y,
1007                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1008             SETfield(sq_tex_resource4, SQ_SEL_0,
1009                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1010             SETfield(sq_tex_resource4, SQ_SEL_1,
1011                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1012             break;
1013     case MESA_FORMAT_Z32:
1014             SETbit(sq_tex_resource0, TILE_TYPE_bit);
1015             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1016                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1017                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1018             SETfield(sq_tex_resource1, FMT_32,
1019                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1020             SETfield(sq_tex_resource4, SQ_SEL_X,
1021                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1022             SETfield(sq_tex_resource4, SQ_SEL_X,
1023                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1024             SETfield(sq_tex_resource4, SQ_SEL_X,
1025                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1026             SETfield(sq_tex_resource4, SQ_SEL_X,
1027                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1028             break;
1029     case MESA_FORMAT_S8:
1030             SETbit(sq_tex_resource0, TILE_TYPE_bit);
1031             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1032                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1033                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1034             SETfield(sq_tex_resource1, FMT_8,
1035                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1036             SETfield(sq_tex_resource4, SQ_SEL_X,
1037                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1038             SETfield(sq_tex_resource4, SQ_SEL_X,
1039                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1040             SETfield(sq_tex_resource4, SQ_SEL_X,
1041                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1042             SETfield(sq_tex_resource4, SQ_SEL_X,
1043                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1044             break;
1045     case MESA_FORMAT_SRGBA8:
1046             SETfield(sq_tex_resource1, FMT_8_8_8_8,
1047                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1048
1049             SETfield(sq_tex_resource4, SQ_SEL_W,
1050                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1051             SETfield(sq_tex_resource4, SQ_SEL_Z,
1052                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1053             SETfield(sq_tex_resource4, SQ_SEL_Y,
1054                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1055             SETfield(sq_tex_resource4, SQ_SEL_X,
1056                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1057             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1058             break;
1059     case MESA_FORMAT_SLA8:
1060             SETfield(sq_tex_resource1, FMT_8_8,
1061                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1062
1063             SETfield(sq_tex_resource4, SQ_SEL_X,
1064                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1065             SETfield(sq_tex_resource4, SQ_SEL_X,
1066                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1067             SETfield(sq_tex_resource4, SQ_SEL_X,
1068                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1069             SETfield(sq_tex_resource4, SQ_SEL_Y,
1070                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1071             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1072             break;
1073     case MESA_FORMAT_SL8: /* X, X, X, ONE */
1074             SETfield(sq_tex_resource1, FMT_8,
1075                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1076
1077             SETfield(sq_tex_resource4, SQ_SEL_X,
1078                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1079             SETfield(sq_tex_resource4, SQ_SEL_X,
1080                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1081             SETfield(sq_tex_resource4, SQ_SEL_X,
1082                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1083             SETfield(sq_tex_resource4, SQ_SEL_1,
1084                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1085             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1086             break;
1087     default:
1088             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
1089             assert("Invalid format for US output\n");
1090             return;
1091     };
1092
1093     SETfield(sq_tex_resource0, (TexelPitch/8)-1, PITCH_shift, PITCH_mask);
1094     SETfield(sq_tex_resource0, w - 1, TEX_WIDTH_shift, TEX_WIDTH_mask);
1095     SETfield(sq_tex_resource1, h - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask);
1096
1097     sq_tex_resource2 = src_offset / 256;
1098
1099     SETfield(sq_tex_resource6, SQ_TEX_VTX_VALID_TEXTURE,
1100              SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
1101              SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
1102
1103     r700SyncSurf(context, bo,
1104                  RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
1105                  0, TC_ACTION_ENA_bit);
1106
1107     BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
1108     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1109     R600_OUT_BATCH(0 * 7);
1110
1111     R600_OUT_BATCH(sq_tex_resource0);
1112     R600_OUT_BATCH(sq_tex_resource1);
1113     R600_OUT_BATCH(sq_tex_resource2);
1114     R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
1115     R600_OUT_BATCH(sq_tex_resource4);
1116     R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
1117     R600_OUT_BATCH(sq_tex_resource6);
1118     R600_OUT_BATCH_RELOC(0,
1119                      bo,
1120                      0,
1121                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1122     R600_OUT_BATCH_RELOC(0,
1123                      bo,
1124                      0,
1125                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1126     END_BATCH();
1127     COMMIT_BATCH();
1128 }
1129
1130 static inline void
1131 set_tex_sampler(context_t * context)
1132 {
1133     uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
1134     int i = 0;
1135
1136     SETbit(sq_tex_sampler_word2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
1137
1138     BATCH_LOCALS(&context->radeon);
1139
1140     BEGIN_BATCH_NO_AUTOSTATE(5);
1141     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
1142     R600_OUT_BATCH(i * 3);
1143     R600_OUT_BATCH(sq_tex_sampler_word0);
1144     R600_OUT_BATCH(sq_tex_sampler_word1);
1145     R600_OUT_BATCH(sq_tex_sampler_word2);
1146     END_BATCH();
1147
1148 }
1149
1150 static inline void
1151 set_scissors(context_t *context, int x1, int y1, int x2, int y2)
1152 {
1153     BATCH_LOCALS(&context->radeon);
1154
1155     BEGIN_BATCH_NO_AUTOSTATE(17);
1156     R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1157     R600_OUT_BATCH((x1 << 0) | (y1 << 16));
1158     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1159
1160     R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 3);
1161     R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1162     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
1163     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1164
1165     R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1166     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1167     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1168
1169     /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1170     R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL, 2 );
1171     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1172     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1173     END_BATCH();
1174
1175     COMMIT_BATCH();
1176
1177 }
1178
1179 static inline void
1180 set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
1181             int w, int h, int src_h, unsigned flip_y)
1182 {
1183     float *vb;
1184     radeon_bo_map(context->blit_bo, 1);
1185     vb = context->blit_bo->ptr;
1186
1187     vb[0] = (float)(dst_x);
1188     vb[1] = (float)(dst_y);
1189     vb[2] = (float)(src_x);
1190     vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
1191
1192     vb[4] = (float)(dst_x);
1193     vb[5] = (float)(dst_y + h);
1194     vb[6] = (float)(src_x);
1195     vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1196
1197     vb[8] = (float)(dst_x + w);
1198     vb[9] = (float)(dst_y + h);
1199     vb[10] = (float)(src_x + w);
1200     vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1201
1202     radeon_bo_unmap(context->blit_bo);
1203
1204 }
1205
1206 static inline void
1207 draw_auto(context_t *context)
1208 {
1209     BATCH_LOCALS(&context->radeon);
1210     uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
1211
1212     SETfield(vgt_primitive_type, DI_PT_RECTLIST,
1213              VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
1214              VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
1215     SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
1216              INDEX_TYPE_mask);
1217     SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
1218              MAJOR_MODE_mask);
1219     SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
1220              SOURCE_SELECT_mask);
1221
1222     vgt_num_indices = 3;
1223
1224     BEGIN_BATCH_NO_AUTOSTATE(10);
1225     // prim
1226     R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
1227     R600_OUT_BATCH(vgt_primitive_type);
1228     // index type
1229     R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1230     R600_OUT_BATCH(vgt_index_type);
1231     // num instances
1232     R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1233     R600_OUT_BATCH(1);
1234     //
1235     R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1236     R600_OUT_BATCH(vgt_num_indices);
1237     R600_OUT_BATCH(vgt_draw_initiator);
1238
1239     END_BATCH();
1240     COMMIT_BATCH();
1241 }
1242
1243 static inline void
1244 set_default_state(context_t *context)
1245 {
1246     int ps_prio = 0;
1247     int vs_prio = 1;
1248     int gs_prio = 2;
1249     int es_prio = 3;
1250     int num_ps_gprs;
1251     int num_vs_gprs;
1252     int num_gs_gprs;
1253     int num_es_gprs;
1254     int num_temp_gprs;
1255     int num_ps_threads;
1256     int num_vs_threads;
1257     int num_gs_threads;
1258     int num_es_threads;
1259     int num_ps_stack_entries;
1260     int num_vs_stack_entries;
1261     int num_gs_stack_entries;
1262     int num_es_stack_entries;
1263     uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
1264     uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
1265     uint32_t ta_cntl_aux, db_watermarks, sq_dyn_gpr_cntl_ps_flush_req, db_debug;
1266     BATCH_LOCALS(&context->radeon);
1267
1268     switch (context->radeon.radeonScreen->chip_family) {
1269     case CHIP_FAMILY_R600:
1270             num_ps_gprs = 192;
1271             num_vs_gprs = 56;
1272             num_temp_gprs = 4;
1273             num_gs_gprs = 0;
1274             num_es_gprs = 0;
1275             num_ps_threads = 136;
1276             num_vs_threads = 48;
1277             num_gs_threads = 4;
1278             num_es_threads = 4;
1279             num_ps_stack_entries = 128;
1280             num_vs_stack_entries = 128;
1281             num_gs_stack_entries = 0;
1282             num_es_stack_entries = 0;
1283             break;
1284     case CHIP_FAMILY_RV630:
1285     case CHIP_FAMILY_RV635:
1286             num_ps_gprs = 84;
1287             num_vs_gprs = 36;
1288             num_temp_gprs = 4;
1289             num_gs_gprs = 0;
1290             num_es_gprs = 0;
1291             num_ps_threads = 144;
1292             num_vs_threads = 40;
1293             num_gs_threads = 4;
1294             num_es_threads = 4;
1295             num_ps_stack_entries = 40;
1296             num_vs_stack_entries = 40;
1297             num_gs_stack_entries = 32;
1298             num_es_stack_entries = 16;
1299             break;
1300     case CHIP_FAMILY_RV610:
1301     case CHIP_FAMILY_RV620:
1302     case CHIP_FAMILY_RS780:
1303     case CHIP_FAMILY_RS880:
1304     default:
1305             num_ps_gprs = 84;
1306             num_vs_gprs = 36;
1307             num_temp_gprs = 4;
1308             num_gs_gprs = 0;
1309             num_es_gprs = 0;
1310             num_ps_threads = 136;
1311             num_vs_threads = 48;
1312             num_gs_threads = 4;
1313             num_es_threads = 4;
1314             num_ps_stack_entries = 40;
1315             num_vs_stack_entries = 40;
1316             num_gs_stack_entries = 32;
1317             num_es_stack_entries = 16;
1318             break;
1319     case CHIP_FAMILY_RV670:
1320             num_ps_gprs = 144;
1321             num_vs_gprs = 40;
1322             num_temp_gprs = 4;
1323             num_gs_gprs = 0;
1324             num_es_gprs = 0;
1325             num_ps_threads = 136;
1326             num_vs_threads = 48;
1327             num_gs_threads = 4;
1328             num_es_threads = 4;
1329             num_ps_stack_entries = 40;
1330             num_vs_stack_entries = 40;
1331             num_gs_stack_entries = 32;
1332             num_es_stack_entries = 16;
1333             break;
1334     case CHIP_FAMILY_RV770:
1335             num_ps_gprs = 192;
1336             num_vs_gprs = 56;
1337             num_temp_gprs = 4;
1338             num_gs_gprs = 0;
1339             num_es_gprs = 0;
1340             num_ps_threads = 188;
1341             num_vs_threads = 60;
1342             num_gs_threads = 0;
1343             num_es_threads = 0;
1344             num_ps_stack_entries = 256;
1345             num_vs_stack_entries = 256;
1346             num_gs_stack_entries = 0;
1347             num_es_stack_entries = 0;
1348             break;
1349     case CHIP_FAMILY_RV730:
1350     case CHIP_FAMILY_RV740:
1351             num_ps_gprs = 84;
1352             num_vs_gprs = 36;
1353             num_temp_gprs = 4;
1354             num_gs_gprs = 0;
1355             num_es_gprs = 0;
1356             num_ps_threads = 188;
1357             num_vs_threads = 60;
1358             num_gs_threads = 0;
1359             num_es_threads = 0;
1360             num_ps_stack_entries = 128;
1361             num_vs_stack_entries = 128;
1362             num_gs_stack_entries = 0;
1363             num_es_stack_entries = 0;
1364             break;
1365     case CHIP_FAMILY_RV710:
1366             num_ps_gprs = 192;
1367             num_vs_gprs = 56;
1368             num_temp_gprs = 4;
1369             num_gs_gprs = 0;
1370             num_es_gprs = 0;
1371             num_ps_threads = 144;
1372             num_vs_threads = 48;
1373             num_gs_threads = 0;
1374             num_es_threads = 0;
1375             num_ps_stack_entries = 128;
1376             num_vs_stack_entries = 128;
1377             num_gs_stack_entries = 0;
1378             num_es_stack_entries = 0;
1379             break;
1380     }
1381
1382     sq_config = 0;
1383     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1384         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1385         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1386         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1387         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1388             CLEARbit(sq_config, VC_ENABLE_bit);
1389     else
1390             SETbit(sq_config, VC_ENABLE_bit);
1391     SETbit(sq_config, DX9_CONSTS_bit);
1392     SETbit(sq_config, ALU_INST_PREFER_VECTOR_bit);
1393     SETfield(sq_config, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1394     SETfield(sq_config, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
1395     SETfield(sq_config, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
1396     SETfield(sq_config, es_prio, ES_PRIO_shift, ES_PRIO_mask);
1397
1398     sq_gpr_resource_mgmt_1 = 0;
1399     SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1400     SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1401     SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
1402              NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1403
1404     sq_gpr_resource_mgmt_2 = 0;
1405     SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1406     SETfield(sq_gpr_resource_mgmt_2, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1407
1408     sq_thread_resource_mgmt = 0;
1409     SETfield(sq_thread_resource_mgmt, num_ps_threads,
1410              NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1411     SETfield(sq_thread_resource_mgmt, num_vs_threads,
1412              NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1413     SETfield(sq_thread_resource_mgmt, num_gs_threads,
1414              NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1415     SETfield(sq_thread_resource_mgmt, num_es_threads,
1416              NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1417
1418     sq_stack_resource_mgmt_1 = 0;
1419     SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
1420              NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1421     SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
1422              NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1423
1424     sq_stack_resource_mgmt_2 = 0;
1425     SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
1426              NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1427     SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
1428              NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1429
1430     ta_cntl_aux = 0;
1431     SETfield(ta_cntl_aux, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1432     db_watermarks = 0;
1433     SETfield(db_watermarks, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1434     SETfield(db_watermarks, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1435     SETfield(db_watermarks, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1436     SETfield(db_watermarks, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1437     sq_dyn_gpr_cntl_ps_flush_req = 0;
1438     db_debug = 0;
1439     if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1440             SETfield(ta_cntl_aux, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1441             db_debug = 0x82000000;
1442             SETfield(db_watermarks, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1443     } else {
1444             SETfield(ta_cntl_aux, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1445             SETfield(db_watermarks, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1446             SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
1447     }
1448
1449     BEGIN_BATCH_NO_AUTOSTATE(117);
1450     R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
1451     R600_OUT_BATCH(sq_config);
1452     R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
1453     R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
1454     R600_OUT_BATCH(sq_thread_resource_mgmt);
1455     R600_OUT_BATCH(sq_stack_resource_mgmt_1);
1456     R600_OUT_BATCH(sq_stack_resource_mgmt_2);
1457
1458     R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, ta_cntl_aux);
1459     R600_OUT_BATCH_REGVAL(VC_ENHANCE, 0);
1460     R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, sq_dyn_gpr_cntl_ps_flush_req);
1461     R600_OUT_BATCH_REGVAL(DB_DEBUG, db_debug);
1462     R600_OUT_BATCH_REGVAL(DB_WATERMARKS, db_watermarks);
1463
1464     R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
1465     R600_OUT_BATCH(0);
1466     R600_OUT_BATCH(0);
1467     R600_OUT_BATCH(0);
1468     R600_OUT_BATCH(0);
1469     R600_OUT_BATCH(0);
1470     R600_OUT_BATCH(0);
1471     R600_OUT_BATCH(0);
1472     R600_OUT_BATCH(0);
1473     R600_OUT_BATCH(0);
1474
1475     R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL,
1476                          (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
1477     R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
1478     R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
1479     R600_OUT_BATCH_REGVAL(DB_DEPTH_INFO, 0);
1480     R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
1481     R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
1482     R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
1483     R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
1484     R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, (0xcc << ROP3_shift));
1485
1486     R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, VTX_XY_FMT_bit);
1487     R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, 0);
1488     R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, CLIP_DISABLE_bit);
1489     R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, (FACE_bit) |
1490         (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) |
1491         (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift));
1492     R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL, (PIX_CENTER_bit) |
1493         (X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
1494         (X_1_256TH << QUANT_MODE_shift));
1495
1496     R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1497     R600_OUT_BATCH(2048);
1498     R600_OUT_BATCH(0);
1499     R600_OUT_BATCH(0);
1500     R600_OUT_BATCH(0);
1501
1502     R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1503     R600_OUT_BATCH(0);
1504     R600_OUT_BATCH(0);
1505     R600_OUT_BATCH(0);
1506     R600_OUT_BATCH(0);
1507     R600_OUT_BATCH(0);
1508     R600_OUT_BATCH(0);
1509     R600_OUT_BATCH(0);
1510     R600_OUT_BATCH(0);
1511     R600_OUT_BATCH(0);
1512     R600_OUT_BATCH(0);
1513     R600_OUT_BATCH(0);
1514     R600_OUT_BATCH(0);
1515     R600_OUT_BATCH(0);
1516
1517     R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, 0);
1518     R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, 0);
1519     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, 0);
1520     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, 0);
1521
1522     R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1523     R600_OUT_BATCH(0);
1524     R600_OUT_BATCH(0);
1525     R600_OUT_BATCH(0);
1526
1527     R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, 0);
1528
1529     END_BATCH();
1530     COMMIT_BATCH();
1531 }
1532
1533 static GLboolean validate_buffers(context_t *rmesa,
1534                                   struct radeon_bo *src_bo,
1535                                   struct radeon_bo *dst_bo)
1536 {
1537     int ret;
1538     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1539                                       src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
1540
1541     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1542                                       dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
1543
1544     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1545                                       rmesa->blit_bo, RADEON_GEM_DOMAIN_GTT, 0);
1546
1547     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1548                                         rmesa->blit_bo,
1549                                         RADEON_GEM_DOMAIN_GTT, 0);
1550     if (ret)
1551         return GL_FALSE;
1552
1553     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1554                                         first_elem(&rmesa->radeon.dma.reserved)->bo,
1555                                         RADEON_GEM_DOMAIN_GTT, 0);
1556     if (ret)
1557         return GL_FALSE;
1558
1559     return GL_TRUE;
1560 }
1561
1562 GLboolean r600_blit(GLcontext *ctx,
1563                     struct radeon_bo *src_bo,
1564                     intptr_t src_offset,
1565                     gl_format src_mesaformat,
1566                     unsigned src_pitch,
1567                     unsigned src_width,
1568                     unsigned src_height,
1569                     unsigned src_x,
1570                     unsigned src_y,
1571                     struct radeon_bo *dst_bo,
1572                     intptr_t dst_offset,
1573                     gl_format dst_mesaformat,
1574                     unsigned dst_pitch,
1575                     unsigned dst_width,
1576                     unsigned dst_height,
1577                     unsigned dst_x,
1578                     unsigned dst_y,
1579                     unsigned w,
1580                     unsigned h,
1581                     unsigned flip_y)
1582 {
1583     context_t *context = R700_CONTEXT(ctx);
1584     int id = 0;
1585
1586     if (!is_blit_supported(dst_mesaformat))
1587             return GL_FALSE;
1588
1589     if (src_bo == dst_bo) {
1590         return GL_FALSE;
1591     }
1592
1593     if (0) {
1594         fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1595                 src_width, src_height, src_pitch,
1596                 _mesa_format_row_stride(src_mesaformat, src_width),
1597                 _mesa_get_format_name(src_mesaformat));
1598         fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
1599                 dst_width, dst_height,
1600                 _mesa_format_row_stride(dst_mesaformat, dst_width),
1601                 _mesa_get_format_name(dst_mesaformat));
1602     }
1603
1604     /* Flush is needed to make sure that source buffer has correct data */
1605     radeonFlush(context->radeon.glCtx);
1606
1607     rcommonEnsureCmdBufSpace(&context->radeon, 304, __FUNCTION__);
1608
1609     /* load shaders */
1610     load_shaders(context->radeon.glCtx);
1611
1612     if (!validate_buffers(context, src_bo, dst_bo))
1613         return GL_FALSE;
1614
1615     /* set clear state */
1616     /* 117 */
1617     set_default_state(context);
1618
1619     /* shaders */
1620     /* 72 */
1621     set_shaders(context);
1622
1623     /* src */
1624     /* 20 */
1625     set_tex_resource(context, src_mesaformat, src_bo,
1626                      src_width, src_height, src_pitch, src_offset);
1627
1628     /* 5 */
1629     set_tex_sampler(context);
1630
1631     /* dst */
1632     /* 27 */
1633     set_render_target(context, dst_bo, dst_mesaformat,
1634                       dst_pitch, dst_width, dst_height, dst_offset);
1635     /* scissors */
1636     /* 17 */
1637     set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
1638
1639     set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
1640     /* Vertex buffer setup */
1641     /* 24 */
1642     set_vtx_resource(context);
1643
1644     /* draw */
1645     /* 10 */
1646     draw_auto(context);
1647
1648     /* 7 */
1649     r700SyncSurf(context, dst_bo, 0,
1650                  RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
1651                  CB_ACTION_ENA_bit | (1 << (id + 6)));
1652
1653     /* 5 */
1654     r700WaitForIdleClean(context);
1655
1656     radeonFlush(context->radeon.glCtx);
1657
1658     return GL_TRUE;
1659 }