src/mesa/drivers/dri/r600/r600_blit.c

   1 /*
   2  * Copyright (C) 2009 Advanced Micro Devices, Inc.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r600_context.h"
  30
  31 #include "r600_blit.h"
  32 #include "r600_blit_shaders.h"
  33 #include "r600_cmdbuf.h"
  34
  35 static inline void
  36 set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
  37                   int pitch, int w, int h, intptr_t dst_offset)
  38 {
  39     uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
  40     int nPitchInPixel, id = 0;
  41     uint32_t comp_swap, format, bpp = _mesa_get_format_bytes(mesa_format);
  42     BATCH_LOCALS(&context->radeon);
  43
  44     cb_color0_base = dst_offset / 256;
  45
  46     nPitchInPixel = pitch/bpp;
  47     SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
  48              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
  49     SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
  50              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
  51
  52     SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
  53     SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
  54              CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
  55
  56     SETbit(cb_color0_info, BLEND_BYPASS_bit);
  57
  58     switch(mesa_format) {
  59     case MESA_FORMAT_RGBA8888:
  60             format = COLOR_8_8_8_8;
  61             comp_swap = SWAP_STD_REV;
  62             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  63             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  64             break;
  65     case MESA_FORMAT_SIGNED_RGBA8888:
  66             format = COLOR_8_8_8_8;
  67             comp_swap = SWAP_STD_REV;
  68             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  69             SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  70             break;
  71     case MESA_FORMAT_RGBA8888_REV:
  72             format = COLOR_8_8_8_8;
  73             comp_swap = SWAP_STD;
  74             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  75             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  76             break;
  77     case MESA_FORMAT_SIGNED_RGBA8888_REV:
  78             format = COLOR_8_8_8_8;
  79             comp_swap = SWAP_STD;
  80             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  81             SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  82             break;
  83     case MESA_FORMAT_ARGB8888:
  84     case MESA_FORMAT_XRGB8888:
  85             format = COLOR_8_8_8_8;
  86             comp_swap = SWAP_ALT;
  87             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  88             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  89             break;
  90     case MESA_FORMAT_ARGB8888_REV:
  91     case MESA_FORMAT_XRGB8888_REV:
  92             format = COLOR_8_8_8_8;
  93             comp_swap = SWAP_ALT_REV;
  94             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  95             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  96             break;
  97     case MESA_FORMAT_RGB565:
  98             format = COLOR_5_6_5;
  99             comp_swap = SWAP_STD_REV;
 100             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 101             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 102             break;
 103     case MESA_FORMAT_RGB565_REV:
 104             format = COLOR_5_6_5;
 105             comp_swap = SWAP_STD;
 106             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 107             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 108             break;
 109     case MESA_FORMAT_ARGB4444:
 110             format = COLOR_4_4_4_4;
 111             comp_swap = SWAP_ALT;
 112             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 113             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 114             break;
 115     case MESA_FORMAT_ARGB4444_REV:
 116             format = COLOR_4_4_4_4;
 117             comp_swap = SWAP_ALT_REV;
 118             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 119             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 120             break;
 121     case MESA_FORMAT_ARGB1555:
 122             format = COLOR_1_5_5_5;
 123             comp_swap = SWAP_ALT;
 124             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 125             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 126             break;
 127     case MESA_FORMAT_ARGB1555_REV:
 128             format = COLOR_1_5_5_5;
 129             comp_swap = SWAP_ALT_REV;
 130             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 131             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 132             break;
 133     case MESA_FORMAT_AL88:
 134             format = COLOR_8_8;
 135             comp_swap = SWAP_STD;
 136             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 137             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 138             break;
 139     case MESA_FORMAT_AL88_REV:
 140             format = COLOR_8_8;
 141             comp_swap = SWAP_STD_REV;
 142             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 143             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 144             break;
 145     case MESA_FORMAT_RGB332:
 146             format = COLOR_3_3_2;
 147             comp_swap = SWAP_STD_REV;
 148             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 149             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 150             break;
 151     case MESA_FORMAT_A8:
 152             format = COLOR_8;
 153             comp_swap = SWAP_ALT_REV;
 154             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 155             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 156             break;
 157     case MESA_FORMAT_I8:
 158     case MESA_FORMAT_CI8:
 159             format = COLOR_8;
 160             comp_swap = SWAP_STD;
 161             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 162             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 163             break;
 164     case MESA_FORMAT_L8:
 165             format = COLOR_8;
 166             comp_swap = SWAP_ALT;
 167             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 168             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 169             break;
 170     case MESA_FORMAT_RGBA_FLOAT32:
 171             format = COLOR_32_32_32_32_FLOAT;
 172             comp_swap = SWAP_STD_REV;
 173             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 174             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 175             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 176             break;
 177     case MESA_FORMAT_RGBA_FLOAT16:
 178             format = COLOR_16_16_16_16_FLOAT;
 179             comp_swap = SWAP_STD_REV;
 180             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 181             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 182             break;
 183     case MESA_FORMAT_ALPHA_FLOAT32:
 184             format = COLOR_32_FLOAT;
 185             comp_swap = SWAP_ALT_REV;
 186             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 187             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 188             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 189             break;
 190     case MESA_FORMAT_ALPHA_FLOAT16:
 191             format = COLOR_16_FLOAT;
 192             comp_swap = SWAP_ALT_REV;
 193             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 194             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 195             break;
 196     case MESA_FORMAT_LUMINANCE_FLOAT32:
 197             format = COLOR_32_FLOAT;
 198             comp_swap = SWAP_ALT;
 199             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 200             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 201             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 202             break;
 203     case MESA_FORMAT_LUMINANCE_FLOAT16:
 204             format = COLOR_16_FLOAT;
 205             comp_swap = SWAP_ALT;
 206             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 207             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 208             break;
 209     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 210             format = COLOR_32_32_FLOAT;
 211             comp_swap = SWAP_ALT_REV;
 212             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 213             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 214             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 215             break;
 216     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 217             format = COLOR_16_16_FLOAT;
 218             comp_swap = SWAP_ALT_REV;
 219             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 220             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 221             break;
 222     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 223             format = COLOR_32_FLOAT;
 224             comp_swap = SWAP_STD;
 225             SETbit(cb_color0_info, BLEND_FLOAT32_bit);
 226             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 227             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 228             break;
 229     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 230             format = COLOR_16_FLOAT;
 231             comp_swap = SWAP_STD;
 232             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 233             SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 234             break;
 235     case MESA_FORMAT_X8_Z24:
 236     case MESA_FORMAT_S8_Z24:
 237             format = COLOR_8_24;
 238             comp_swap = SWAP_STD;
 239             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 240                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 241             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 242             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 243             break;
 244     case MESA_FORMAT_Z24_S8:
 245             format = COLOR_24_8;
 246             comp_swap = SWAP_STD;
 247             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 248                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 249             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 250             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 251             break;
 252     case MESA_FORMAT_Z16:
 253             format = COLOR_16;
 254             comp_swap = SWAP_STD;
 255             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 256                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 257             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 258             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 259             break;
 260     case MESA_FORMAT_Z32:
 261             format = COLOR_32;
 262             comp_swap = SWAP_STD;
 263             SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
 264                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 265             CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
 266             SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 267             break;
 268     case MESA_FORMAT_SRGBA8:
 269             format = COLOR_8_8_8_8;
 270             comp_swap = SWAP_STD_REV;
 271             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 272             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 273             break;
 274     case MESA_FORMAT_SLA8:
 275             format = COLOR_8_8;
 276             comp_swap = SWAP_ALT_REV;
 277             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 278             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 279             break;
 280     case MESA_FORMAT_SL8:
 281             format = COLOR_8;
 282             comp_swap = SWAP_ALT_REV;
 283             SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 284             SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 285             break;
 286     default:
 287             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
 288             assert("Invalid format for US output\n");
 289             return;
 290     }
 291
 292     SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
 293              CB_COLOR0_INFO__FORMAT_mask);
 294     SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
 295
 296     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 297     R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
 298     R600_OUT_BATCH(cb_color0_base);
 299     R600_OUT_BATCH_RELOC(0,
 300                          bo,
 301                          0,
 302                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 303     END_BATCH();
 304
 305     if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 306         (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 307             BEGIN_BATCH_NO_AUTOSTATE(2);
 308             R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
 309             R600_OUT_BATCH((2 << id));
 310             END_BATCH();
 311     }
 312
 313     /* Set CMASK & TILE buffer to the offset of color buffer as
 314      * we don't use those this shouldn't cause any issue and we
 315      * then have a valid cmd stream
 316      */
 317     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 318     R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
 319     R600_OUT_BATCH(cb_color0_base);
 320     R600_OUT_BATCH_RELOC(0,
 321                          bo,
 322                          0,
 323                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 324     END_BATCH();
 325     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 326     R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
 327     R600_OUT_BATCH(cb_color0_base);
 328     R600_OUT_BATCH_RELOC(0,
 329                          bo,
 330                          0,
 331                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 332     END_BATCH();
 333
 334     BEGIN_BATCH_NO_AUTOSTATE(12);
 335     R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
 336     R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
 337     R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
 338     R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
 339     END_BATCH();
 340
 341     COMMIT_BATCH();
 342
 343 }
 344
 345 static inline void load_shaders(GLcontext * ctx)
 346 {
 347
 348     radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
 349     context_t *context = R700_CONTEXT(ctx);
 350     int i, size;
 351     uint32_t *shader;
 352
 353     if (context->blit_bo_loaded == 1)
 354         return;
 355
 356     size = 4096;
 357     context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
 358                                       size, 256, RADEON_GEM_DOMAIN_GTT, 0);
 359     radeon_bo_map(context->blit_bo, 1);
 360     shader = context->blit_bo->ptr;
 361
 362     for(i=0; i<sizeof(r6xx_vs)/4; i++) {
 363         shader[128+i] = r6xx_vs[i];
 364     }
 365     for(i=0; i<sizeof(r6xx_ps)/4; i++) {
 366         shader[256+i] = r6xx_ps[i];
 367     }
 368
 369     radeon_bo_unmap(context->blit_bo);
 370     context->blit_bo_loaded = 1;
 371
 372 }
 373
 374 static inline void
 375 set_shaders(context_t *context)
 376 {
 377     struct radeon_bo * pbo = context->blit_bo;
 378     BATCH_LOCALS(&context->radeon);
 379
 380     uint32_t sq_pgm_start_fs = (512 >> 8);
 381     uint32_t sq_pgm_resources_fs = 0;
 382     uint32_t sq_pgm_cf_offset_fs = 0;
 383
 384     uint32_t sq_pgm_start_vs = (512 >> 8);
 385     uint32_t sq_pgm_resources_vs = (1 << NUM_GPRS_shift);
 386     uint32_t sq_pgm_cf_offset_vs = 0;
 387
 388     uint32_t sq_pgm_start_ps = (1024 >> 8);
 389     uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
 390     uint32_t sq_pgm_cf_offset_ps = 0;
 391     uint32_t sq_pgm_exports_ps = (1 << 1);
 392
 393     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 394
 395     /* FS */
 396     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 397     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
 398     R600_OUT_BATCH(sq_pgm_start_fs);
 399     R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
 400                          pbo,
 401                          sq_pgm_start_fs,
 402                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 403     END_BATCH();
 404
 405     BEGIN_BATCH_NO_AUTOSTATE(6);
 406     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
 407     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, sq_pgm_cf_offset_fs);
 408     END_BATCH();
 409
 410     /* VS */
 411     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 412     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
 413     R600_OUT_BATCH(sq_pgm_start_vs);
 414     R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
 415                          pbo,
 416                          sq_pgm_start_vs,
 417                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 418     END_BATCH();
 419
 420     BEGIN_BATCH_NO_AUTOSTATE(6);
 421     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, sq_pgm_resources_vs);
 422     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, sq_pgm_cf_offset_vs);
 423     END_BATCH();
 424
 425     /* PS */
 426     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 427     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
 428     R600_OUT_BATCH(sq_pgm_start_ps);
 429     R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
 430                          pbo,
 431                          sq_pgm_start_ps,
 432                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 433     END_BATCH();
 434
 435     BEGIN_BATCH_NO_AUTOSTATE(9);
 436     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, sq_pgm_resources_ps);
 437     R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, sq_pgm_exports_ps);
 438     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, sq_pgm_cf_offset_ps);
 439     END_BATCH();
 440
 441     BEGIN_BATCH_NO_AUTOSTATE(18);
 442     R600_OUT_BATCH_REGVAL(SPI_VS_OUT_CONFIG, 0); //EXPORT_COUNT is - 1
 443     R600_OUT_BATCH_REGVAL(SPI_VS_OUT_ID_0, 0);
 444     R600_OUT_BATCH_REGVAL(SPI_PS_INPUT_CNTL_0, SEL_CENTROID_bit);
 445     R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_0, (1 << NUM_INTERP_shift));
 446     R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_1, 0);
 447     R600_OUT_BATCH_REGVAL(SPI_INTERP_CONTROL_0, 0);
 448     END_BATCH();
 449
 450     COMMIT_BATCH();
 451
 452 }
 453
 454 static inline void
 455 set_vtx_resource(context_t *context)
 456 {
 457     struct radeon_bo *bo = context->blit_bo;
 458     BATCH_LOCALS(&context->radeon);
 459
 460     BEGIN_BATCH_NO_AUTOSTATE(6);
 461     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 462     R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
 463     R600_OUT_BATCH(0);
 464
 465     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 466     R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
 467     R600_OUT_BATCH(0);
 468     END_BATCH();
 469     COMMIT_BATCH();
 470
 471     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 472         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 473         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
 474         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
 475         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
 476             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
 477     else
 478             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
 479
 480     BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 481
 482     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 483     R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
 484     R600_OUT_BATCH(0);
 485     R600_OUT_BATCH(48 - 1);
 486     R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
 487     R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
 488     R600_OUT_BATCH(0);
 489     R600_OUT_BATCH(0);
 490     R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
 491     R600_OUT_BATCH_RELOC(SQ_VTX_CONSTANT_WORD0_0,
 492                          bo,
 493                          SQ_VTX_CONSTANT_WORD0_0,
 494                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 495     END_BATCH();
 496     COMMIT_BATCH();
 497
 498 }
 499
 500 static inline void
 501 set_tex_resource(context_t * context,
 502                  gl_format mesa_format, struct radeon_bo *bo, int w, int h,
 503                  int pitch, intptr_t src_offset)
 504 {
 505     uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource6;
 506     int bpp = _mesa_get_format_bytes(mesa_format);
 507     int TexelPitch = pitch/bpp;
 508
 509     sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource6 = 0;
 510     BATCH_LOCALS(&context->radeon);
 511
 512     SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
 513     SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
 514                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 515                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 516
 517     switch (mesa_format) {
 518     case MESA_FORMAT_RGBA8888:
 519     case MESA_FORMAT_SIGNED_RGBA8888:
 520             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 521                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 522
 523             SETfield(sq_tex_resource4, SQ_SEL_W,
 524                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 525             SETfield(sq_tex_resource4, SQ_SEL_Z,
 526                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 527             SETfield(sq_tex_resource4, SQ_SEL_Y,
 528                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 529             SETfield(sq_tex_resource4, SQ_SEL_X,
 530                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 531             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
 532                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 533                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 534                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 535                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 536                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 537                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 538                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 539                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 540             }
 541             break;
 542     case MESA_FORMAT_RGBA8888_REV:
 543     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 544             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 545                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 546
 547             SETfield(sq_tex_resource4, SQ_SEL_X,
 548                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 549             SETfield(sq_tex_resource4, SQ_SEL_Y,
 550                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 551             SETfield(sq_tex_resource4, SQ_SEL_Z,
 552                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 553             SETfield(sq_tex_resource4, SQ_SEL_W,
 554                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 555             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
 556                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 557                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 558                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 559                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 560                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 561                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 562                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 563                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 564             }
 565             break;
 566     case MESA_FORMAT_ARGB8888:
 567             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 568                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 569
 570             SETfield(sq_tex_resource4, SQ_SEL_Z,
 571                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 572             SETfield(sq_tex_resource4, SQ_SEL_Y,
 573                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 574             SETfield(sq_tex_resource4, SQ_SEL_X,
 575                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 576             SETfield(sq_tex_resource4, SQ_SEL_W,
 577                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 578             break;
 579     case MESA_FORMAT_XRGB8888:
 580             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 581                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 582
 583             SETfield(sq_tex_resource4, SQ_SEL_Z,
 584                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 585             SETfield(sq_tex_resource4, SQ_SEL_Y,
 586                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 587             SETfield(sq_tex_resource4, SQ_SEL_X,
 588                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 589             SETfield(sq_tex_resource4, SQ_SEL_1,
 590                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 591             break;
 592     case MESA_FORMAT_ARGB8888_REV:
 593             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 594                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 595
 596             SETfield(sq_tex_resource4, SQ_SEL_Y,
 597                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 598             SETfield(sq_tex_resource4, SQ_SEL_Z,
 599                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 600             SETfield(sq_tex_resource4, SQ_SEL_W,
 601                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 602             SETfield(sq_tex_resource4, SQ_SEL_X,
 603                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 604             break;
 605     case MESA_FORMAT_XRGB8888_REV:
 606             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 607                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 608
 609             SETfield(sq_tex_resource4, SQ_SEL_1,
 610                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 611             SETfield(sq_tex_resource4, SQ_SEL_Z,
 612                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 613             SETfield(sq_tex_resource4, SQ_SEL_W,
 614                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 615             SETfield(sq_tex_resource4, SQ_SEL_X,
 616                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 617             break;
 618     case MESA_FORMAT_RGB565:
 619             SETfield(sq_tex_resource1, FMT_5_6_5,
 620                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 621
 622             SETfield(sq_tex_resource4, SQ_SEL_Z,
 623                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 624             SETfield(sq_tex_resource4, SQ_SEL_Y,
 625                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 626             SETfield(sq_tex_resource4, SQ_SEL_X,
 627                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 628             SETfield(sq_tex_resource4, SQ_SEL_1,
 629                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 630             break;
 631     case MESA_FORMAT_RGB565_REV:
 632             SETfield(sq_tex_resource1, FMT_5_6_5,
 633                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 634
 635             SETfield(sq_tex_resource4, SQ_SEL_X,
 636                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 637             SETfield(sq_tex_resource4, SQ_SEL_Y,
 638                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 639             SETfield(sq_tex_resource4, SQ_SEL_Z,
 640                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 641             SETfield(sq_tex_resource4, SQ_SEL_1,
 642                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 643             break;
 644     case MESA_FORMAT_ARGB4444:
 645             SETfield(sq_tex_resource1, FMT_4_4_4_4,
 646                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 647
 648             SETfield(sq_tex_resource4, SQ_SEL_Z,
 649                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 650             SETfield(sq_tex_resource4, SQ_SEL_Y,
 651                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 652             SETfield(sq_tex_resource4, SQ_SEL_X,
 653                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 654             SETfield(sq_tex_resource4, SQ_SEL_W,
 655                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 656             break;
 657     case MESA_FORMAT_ARGB4444_REV:
 658             SETfield(sq_tex_resource1, FMT_4_4_4_4,
 659                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 660
 661             SETfield(sq_tex_resource4, SQ_SEL_Y,
 662                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 663             SETfield(sq_tex_resource4, SQ_SEL_Z,
 664                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 665             SETfield(sq_tex_resource4, SQ_SEL_W,
 666                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 667             SETfield(sq_tex_resource4, SQ_SEL_X,
 668                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 669             break;
 670     case MESA_FORMAT_ARGB1555:
 671             SETfield(sq_tex_resource1, FMT_1_5_5_5,
 672                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 673
 674             SETfield(sq_tex_resource4, SQ_SEL_Z,
 675                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 676             SETfield(sq_tex_resource4, SQ_SEL_Y,
 677                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 678             SETfield(sq_tex_resource4, SQ_SEL_X,
 679                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 680             SETfield(sq_tex_resource4, SQ_SEL_W,
 681                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 682             break;
 683     case MESA_FORMAT_ARGB1555_REV:
 684             SETfield(sq_tex_resource1, FMT_1_5_5_5,
 685                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 686
 687             SETfield(sq_tex_resource4, SQ_SEL_Y,
 688                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 689             SETfield(sq_tex_resource4, SQ_SEL_Z,
 690                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 691             SETfield(sq_tex_resource4, SQ_SEL_W,
 692                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 693             SETfield(sq_tex_resource4, SQ_SEL_X,
 694                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 695             break;
 696     case MESA_FORMAT_AL88:
 697     case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
 698             SETfield(sq_tex_resource1, FMT_8_8,
 699                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 700
 701             SETfield(sq_tex_resource4, SQ_SEL_X,
 702                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 703             SETfield(sq_tex_resource4, SQ_SEL_X,
 704                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 705             SETfield(sq_tex_resource4, SQ_SEL_X,
 706                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 707             SETfield(sq_tex_resource4, SQ_SEL_Y,
 708                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 709             break;
 710     case MESA_FORMAT_RGB332:
 711             SETfield(sq_tex_resource1, FMT_3_3_2,
 712                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 713
 714             SETfield(sq_tex_resource4, SQ_SEL_Z,
 715                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 716             SETfield(sq_tex_resource4, SQ_SEL_Y,
 717                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 718             SETfield(sq_tex_resource4, SQ_SEL_X,
 719                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 720             SETfield(sq_tex_resource4, SQ_SEL_1,
 721                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 722             break;
 723     case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
 724             SETfield(sq_tex_resource1, FMT_8,
 725                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 726
 727             SETfield(sq_tex_resource4, SQ_SEL_0,
 728                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 729             SETfield(sq_tex_resource4, SQ_SEL_0,
 730                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 731             SETfield(sq_tex_resource4, SQ_SEL_0,
 732                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 733             SETfield(sq_tex_resource4, SQ_SEL_X,
 734                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 735             break;
 736     case MESA_FORMAT_L8: /* X, X, X, ONE */
 737             SETfield(sq_tex_resource1, FMT_8,
 738                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 739
 740             SETfield(sq_tex_resource4, SQ_SEL_X,
 741                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 742             SETfield(sq_tex_resource4, SQ_SEL_X,
 743                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 744             SETfield(sq_tex_resource4, SQ_SEL_X,
 745                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 746             SETfield(sq_tex_resource4, SQ_SEL_1,
 747                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 748             break;
 749     case MESA_FORMAT_I8: /* X, X, X, X */
 750     case MESA_FORMAT_CI8:
 751             SETfield(sq_tex_resource1, FMT_8,
 752                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 753
 754             SETfield(sq_tex_resource4, SQ_SEL_X,
 755                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 756             SETfield(sq_tex_resource4, SQ_SEL_X,
 757                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 758             SETfield(sq_tex_resource4, SQ_SEL_X,
 759                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 760             SETfield(sq_tex_resource4, SQ_SEL_X,
 761                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 762             break;
 763     case MESA_FORMAT_RGBA_FLOAT32:
 764             SETfield(sq_tex_resource1, FMT_32_32_32_32_FLOAT,
 765                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 766
 767             SETfield(sq_tex_resource4, SQ_SEL_X,
 768                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 769             SETfield(sq_tex_resource4, SQ_SEL_Y,
 770                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 771             SETfield(sq_tex_resource4, SQ_SEL_Z,
 772                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 773             SETfield(sq_tex_resource4, SQ_SEL_W,
 774                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 775             break;
 776     case MESA_FORMAT_RGBA_FLOAT16:
 777             SETfield(sq_tex_resource1, FMT_16_16_16_16_FLOAT,
 778                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 779
 780             SETfield(sq_tex_resource4, SQ_SEL_X,
 781                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 782             SETfield(sq_tex_resource4, SQ_SEL_Y,
 783                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 784             SETfield(sq_tex_resource4, SQ_SEL_Z,
 785                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 786             SETfield(sq_tex_resource4, SQ_SEL_W,
 787                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 788             break;
 789     case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
 790             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 791                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 792
 793             SETfield(sq_tex_resource4, SQ_SEL_0,
 794                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 795             SETfield(sq_tex_resource4, SQ_SEL_0,
 796                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 797             SETfield(sq_tex_resource4, SQ_SEL_0,
 798                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 799             SETfield(sq_tex_resource4, SQ_SEL_X,
 800                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 801             break;
 802     case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
 803             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 804                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 805
 806             SETfield(sq_tex_resource4, SQ_SEL_0,
 807                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 808             SETfield(sq_tex_resource4, SQ_SEL_0,
 809                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 810             SETfield(sq_tex_resource4, SQ_SEL_0,
 811                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 812             SETfield(sq_tex_resource4, SQ_SEL_X,
 813                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 814             break;
 815     case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
 816             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 817                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 818
 819             SETfield(sq_tex_resource4, SQ_SEL_X,
 820                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 821             SETfield(sq_tex_resource4, SQ_SEL_X,
 822                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 823             SETfield(sq_tex_resource4, SQ_SEL_X,
 824                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 825             SETfield(sq_tex_resource4, SQ_SEL_1,
 826                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 827             break;
 828     case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
 829             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 830                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 831
 832             SETfield(sq_tex_resource4, SQ_SEL_X,
 833                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 834             SETfield(sq_tex_resource4, SQ_SEL_X,
 835                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 836             SETfield(sq_tex_resource4, SQ_SEL_X,
 837                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 838             SETfield(sq_tex_resource4, SQ_SEL_1,
 839                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 840             break;
 841     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 842             SETfield(sq_tex_resource1, FMT_32_32_FLOAT,
 843                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 844
 845             SETfield(sq_tex_resource4, SQ_SEL_X,
 846                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 847             SETfield(sq_tex_resource4, SQ_SEL_X,
 848                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 849             SETfield(sq_tex_resource4, SQ_SEL_X,
 850                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 851             SETfield(sq_tex_resource4, SQ_SEL_Y,
 852                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 853             break;
 854     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 855             SETfield(sq_tex_resource1, FMT_16_16_FLOAT,
 856                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 857
 858             SETfield(sq_tex_resource4, SQ_SEL_X,
 859                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 860             SETfield(sq_tex_resource4, SQ_SEL_X,
 861                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 862             SETfield(sq_tex_resource4, SQ_SEL_X,
 863                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 864             SETfield(sq_tex_resource4, SQ_SEL_Y,
 865                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 866             break;
 867     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 868             SETfield(sq_tex_resource1, FMT_32_FLOAT,
 869                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 870
 871             SETfield(sq_tex_resource4, SQ_SEL_X,
 872                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 873             SETfield(sq_tex_resource4, SQ_SEL_X,
 874                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 875             SETfield(sq_tex_resource4, SQ_SEL_X,
 876                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 877             SETfield(sq_tex_resource4, SQ_SEL_X,
 878                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 879             break;
 880     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 881             SETfield(sq_tex_resource1, FMT_16_FLOAT,
 882                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 883
 884             SETfield(sq_tex_resource4, SQ_SEL_X,
 885                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 886             SETfield(sq_tex_resource4, SQ_SEL_X,
 887                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 888             SETfield(sq_tex_resource4, SQ_SEL_X,
 889                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 890             SETfield(sq_tex_resource4, SQ_SEL_X,
 891                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 892             break;
 893     case MESA_FORMAT_Z16:
 894             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 895             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 896                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 897                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 898             SETfield(sq_tex_resource1, FMT_16,
 899                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 900             SETfield(sq_tex_resource4, SQ_SEL_X,
 901                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 902             SETfield(sq_tex_resource4, SQ_SEL_X,
 903                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 904             SETfield(sq_tex_resource4, SQ_SEL_X,
 905                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 906             SETfield(sq_tex_resource4, SQ_SEL_X,
 907                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 908             break;
 909     case MESA_FORMAT_X8_Z24:
 910             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 911             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 912                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 913                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 914             SETfield(sq_tex_resource1, FMT_8_24,
 915                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 916             SETfield(sq_tex_resource4, SQ_SEL_X,
 917                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 918             SETfield(sq_tex_resource4, SQ_SEL_1,
 919                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 920             SETfield(sq_tex_resource4, SQ_SEL_0,
 921                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 922             SETfield(sq_tex_resource4, SQ_SEL_1,
 923                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 924             break;
 925     case MESA_FORMAT_S8_Z24:
 926             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 927             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 928                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 929                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 930             SETfield(sq_tex_resource1, FMT_8_24,
 931                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 932             SETfield(sq_tex_resource4, SQ_SEL_X,
 933                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 934             SETfield(sq_tex_resource4, SQ_SEL_Y,
 935                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 936             SETfield(sq_tex_resource4, SQ_SEL_0,
 937                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 938             SETfield(sq_tex_resource4, SQ_SEL_1,
 939                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 940             break;
 941     case MESA_FORMAT_Z24_S8:
 942             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 943             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 944                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 945                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 946             SETfield(sq_tex_resource1, FMT_24_8,
 947                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 948             SETfield(sq_tex_resource4, SQ_SEL_X,
 949                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 950             SETfield(sq_tex_resource4, SQ_SEL_Y,
 951                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 952             SETfield(sq_tex_resource4, SQ_SEL_0,
 953                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 954             SETfield(sq_tex_resource4, SQ_SEL_1,
 955                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 956             break;
 957     case MESA_FORMAT_Z32:
 958             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 959             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 960                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 961                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 962             SETfield(sq_tex_resource1, FMT_32,
 963                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 964             SETfield(sq_tex_resource4, SQ_SEL_X,
 965                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 966             SETfield(sq_tex_resource4, SQ_SEL_X,
 967                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 968             SETfield(sq_tex_resource4, SQ_SEL_X,
 969                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 970             SETfield(sq_tex_resource4, SQ_SEL_X,
 971                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 972             break;
 973     case MESA_FORMAT_S8:
 974             SETbit(sq_tex_resource0, TILE_TYPE_bit);
 975             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
 976                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 977                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 978             SETfield(sq_tex_resource1, FMT_8,
 979                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 980             SETfield(sq_tex_resource4, SQ_SEL_X,
 981                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 982             SETfield(sq_tex_resource4, SQ_SEL_X,
 983                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 984             SETfield(sq_tex_resource4, SQ_SEL_X,
 985                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 986             SETfield(sq_tex_resource4, SQ_SEL_X,
 987                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 988             break;
 989     case MESA_FORMAT_SRGBA8:
 990             SETfield(sq_tex_resource1, FMT_8_8_8_8,
 991                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 992
 993             SETfield(sq_tex_resource4, SQ_SEL_W,
 994                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 995             SETfield(sq_tex_resource4, SQ_SEL_Z,
 996                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 997             SETfield(sq_tex_resource4, SQ_SEL_Y,
 998                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 999             SETfield(sq_tex_resource4, SQ_SEL_X,
1000                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1001             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1002             break;
1003     case MESA_FORMAT_SLA8:
1004             SETfield(sq_tex_resource1, FMT_8_8,
1005                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1006
1007             SETfield(sq_tex_resource4, SQ_SEL_X,
1008                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1009             SETfield(sq_tex_resource4, SQ_SEL_X,
1010                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1011             SETfield(sq_tex_resource4, SQ_SEL_X,
1012                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1013             SETfield(sq_tex_resource4, SQ_SEL_Y,
1014                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1015             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1016             break;
1017     case MESA_FORMAT_SL8: /* X, X, X, ONE */
1018             SETfield(sq_tex_resource1, FMT_8,
1019                      SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
1020
1021             SETfield(sq_tex_resource4, SQ_SEL_X,
1022                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1023             SETfield(sq_tex_resource4, SQ_SEL_X,
1024                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1025             SETfield(sq_tex_resource4, SQ_SEL_X,
1026                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1027             SETfield(sq_tex_resource4, SQ_SEL_1,
1028                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1029             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1030             break;
1031     default:
1032             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
1033             assert("Invalid format for US output\n");
1034             return;
1035     };
1036
1037     SETfield(sq_tex_resource0, (TexelPitch/8)-1, PITCH_shift, PITCH_mask);
1038     SETfield(sq_tex_resource0, w - 1, TEX_WIDTH_shift, TEX_WIDTH_mask);
1039     SETfield(sq_tex_resource1, h - 1, TEX_HEIGHT_shift, TEX_HEIGHT_mask);
1040
1041     sq_tex_resource2 = src_offset / 256;
1042
1043     SETfield(sq_tex_resource6, SQ_TEX_VTX_VALID_TEXTURE,
1044              SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
1045              SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
1046
1047     r700SyncSurf(context, bo,
1048                  RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
1049                  0, TC_ACTION_ENA_bit);
1050
1051     BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
1052     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
1053     R600_OUT_BATCH(0 * 7);
1054
1055     R600_OUT_BATCH(sq_tex_resource0);
1056     R600_OUT_BATCH(sq_tex_resource1);
1057     R600_OUT_BATCH(sq_tex_resource2);
1058     R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
1059     R600_OUT_BATCH(sq_tex_resource4);
1060     R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
1061     R600_OUT_BATCH(sq_tex_resource6);
1062     R600_OUT_BATCH_RELOC(0,
1063                      bo,
1064                      0,
1065                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1066     R600_OUT_BATCH_RELOC(0,
1067                      bo,
1068                      0,
1069                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1070     END_BATCH();
1071     COMMIT_BATCH();
1072 }
1073
1074 static inline void
1075 set_tex_sampler(context_t * context)
1076 {
1077     uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
1078     int i = 0;
1079
1080     SETbit(sq_tex_sampler_word2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
1081
1082     BATCH_LOCALS(&context->radeon);
1083
1084     BEGIN_BATCH_NO_AUTOSTATE(5);
1085     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
1086     R600_OUT_BATCH(i * 3);
1087     R600_OUT_BATCH(sq_tex_sampler_word0);
1088     R600_OUT_BATCH(sq_tex_sampler_word1);
1089     R600_OUT_BATCH(sq_tex_sampler_word2);
1090     END_BATCH();
1091
1092 }
1093
1094 static inline void
1095 set_scissors(context_t *context, int x1, int y1, int x2, int y2)
1096 {
1097     BATCH_LOCALS(&context->radeon);
1098
1099     BEGIN_BATCH_NO_AUTOSTATE(17);
1100     R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1101     R600_OUT_BATCH((x1 << 0) | (y1 << 16));
1102     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1103
1104     R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 3);
1105     R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1106     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
1107     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1108
1109     R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1110     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1111     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1112
1113     /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1114     R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL, 2 );
1115     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1116     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1117     END_BATCH();
1118
1119     COMMIT_BATCH();
1120
1121 }
1122
1123 static inline void
1124 set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
1125             int w, int h, int src_h, unsigned flip_y)
1126 {
1127     float *vb;
1128     radeon_bo_map(context->blit_bo, 1);
1129     vb = context->blit_bo->ptr;
1130
1131     vb[0] = (float)(dst_x);
1132     vb[1] = (float)(dst_y);
1133     vb[2] = (float)(src_x);
1134     vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
1135
1136     vb[4] = (float)(dst_x);
1137     vb[5] = (float)(dst_y + h);
1138     vb[6] = (float)(src_x);
1139     vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1140
1141     vb[8] = (float)(dst_x + w);
1142     vb[9] = (float)(dst_y + h);
1143     vb[10] = (float)(src_x + w);
1144     vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1145
1146     radeon_bo_unmap(context->blit_bo);
1147
1148 }
1149
1150 static inline void
1151 draw_auto(context_t *context)
1152 {
1153     BATCH_LOCALS(&context->radeon);
1154     uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
1155
1156     SETfield(vgt_primitive_type, DI_PT_RECTLIST,
1157              VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
1158              VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
1159     SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
1160              INDEX_TYPE_mask);
1161     SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
1162              MAJOR_MODE_mask);
1163     SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
1164              SOURCE_SELECT_mask);
1165
1166     vgt_num_indices = 3;
1167
1168     BEGIN_BATCH_NO_AUTOSTATE(10);
1169     // prim
1170     R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
1171     R600_OUT_BATCH(vgt_primitive_type);
1172     // index type
1173     R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1174     R600_OUT_BATCH(vgt_index_type);
1175     // num instances
1176     R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1177     R600_OUT_BATCH(1);
1178     //
1179     R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1180     R600_OUT_BATCH(vgt_num_indices);
1181     R600_OUT_BATCH(vgt_draw_initiator);
1182
1183     END_BATCH();
1184     COMMIT_BATCH();
1185 }
1186
1187 static inline void
1188 set_default_state(context_t *context)
1189 {
1190     int ps_prio = 0;
1191     int vs_prio = 1;
1192     int gs_prio = 2;
1193     int es_prio = 3;
1194     int num_ps_gprs;
1195     int num_vs_gprs;
1196     int num_gs_gprs;
1197     int num_es_gprs;
1198     int num_temp_gprs;
1199     int num_ps_threads;
1200     int num_vs_threads;
1201     int num_gs_threads;
1202     int num_es_threads;
1203     int num_ps_stack_entries;
1204     int num_vs_stack_entries;
1205     int num_gs_stack_entries;
1206     int num_es_stack_entries;
1207     uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
1208     uint32_t sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
1209     uint32_t ta_cntl_aux, db_watermarks, sq_dyn_gpr_cntl_ps_flush_req, db_debug;
1210     BATCH_LOCALS(&context->radeon);
1211
1212     switch (context->radeon.radeonScreen->chip_family) {
1213     case CHIP_FAMILY_R600:
1214             num_ps_gprs = 192;
1215             num_vs_gprs = 56;
1216             num_temp_gprs = 4;
1217             num_gs_gprs = 0;
1218             num_es_gprs = 0;
1219             num_ps_threads = 136;
1220             num_vs_threads = 48;
1221             num_gs_threads = 4;
1222             num_es_threads = 4;
1223             num_ps_stack_entries = 128;
1224             num_vs_stack_entries = 128;
1225             num_gs_stack_entries = 0;
1226             num_es_stack_entries = 0;
1227             break;
1228     case CHIP_FAMILY_RV630:
1229     case CHIP_FAMILY_RV635:
1230             num_ps_gprs = 84;
1231             num_vs_gprs = 36;
1232             num_temp_gprs = 4;
1233             num_gs_gprs = 0;
1234             num_es_gprs = 0;
1235             num_ps_threads = 144;
1236             num_vs_threads = 40;
1237             num_gs_threads = 4;
1238             num_es_threads = 4;
1239             num_ps_stack_entries = 40;
1240             num_vs_stack_entries = 40;
1241             num_gs_stack_entries = 32;
1242             num_es_stack_entries = 16;
1243             break;
1244     case CHIP_FAMILY_RV610:
1245     case CHIP_FAMILY_RV620:
1246     case CHIP_FAMILY_RS780:
1247     case CHIP_FAMILY_RS880:
1248     default:
1249             num_ps_gprs = 84;
1250             num_vs_gprs = 36;
1251             num_temp_gprs = 4;
1252             num_gs_gprs = 0;
1253             num_es_gprs = 0;
1254             num_ps_threads = 136;
1255             num_vs_threads = 48;
1256             num_gs_threads = 4;
1257             num_es_threads = 4;
1258             num_ps_stack_entries = 40;
1259             num_vs_stack_entries = 40;
1260             num_gs_stack_entries = 32;
1261             num_es_stack_entries = 16;
1262             break;
1263     case CHIP_FAMILY_RV670:
1264             num_ps_gprs = 144;
1265             num_vs_gprs = 40;
1266             num_temp_gprs = 4;
1267             num_gs_gprs = 0;
1268             num_es_gprs = 0;
1269             num_ps_threads = 136;
1270             num_vs_threads = 48;
1271             num_gs_threads = 4;
1272             num_es_threads = 4;
1273             num_ps_stack_entries = 40;
1274             num_vs_stack_entries = 40;
1275             num_gs_stack_entries = 32;
1276             num_es_stack_entries = 16;
1277             break;
1278     case CHIP_FAMILY_RV770:
1279             num_ps_gprs = 192;
1280             num_vs_gprs = 56;
1281             num_temp_gprs = 4;
1282             num_gs_gprs = 0;
1283             num_es_gprs = 0;
1284             num_ps_threads = 188;
1285             num_vs_threads = 60;
1286             num_gs_threads = 0;
1287             num_es_threads = 0;
1288             num_ps_stack_entries = 256;
1289             num_vs_stack_entries = 256;
1290             num_gs_stack_entries = 0;
1291             num_es_stack_entries = 0;
1292             break;
1293     case CHIP_FAMILY_RV730:
1294     case CHIP_FAMILY_RV740:
1295             num_ps_gprs = 84;
1296             num_vs_gprs = 36;
1297             num_temp_gprs = 4;
1298             num_gs_gprs = 0;
1299             num_es_gprs = 0;
1300             num_ps_threads = 188;
1301             num_vs_threads = 60;
1302             num_gs_threads = 0;
1303             num_es_threads = 0;
1304             num_ps_stack_entries = 128;
1305             num_vs_stack_entries = 128;
1306             num_gs_stack_entries = 0;
1307             num_es_stack_entries = 0;
1308             break;
1309     case CHIP_FAMILY_RV710:
1310             num_ps_gprs = 192;
1311             num_vs_gprs = 56;
1312             num_temp_gprs = 4;
1313             num_gs_gprs = 0;
1314             num_es_gprs = 0;
1315             num_ps_threads = 144;
1316             num_vs_threads = 48;
1317             num_gs_threads = 0;
1318             num_es_threads = 0;
1319             num_ps_stack_entries = 128;
1320             num_vs_stack_entries = 128;
1321             num_gs_stack_entries = 0;
1322             num_es_stack_entries = 0;
1323             break;
1324     }
1325
1326     sq_config = 0;
1327     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1328         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1329         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1330         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1331         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1332             CLEARbit(sq_config, VC_ENABLE_bit);
1333     else
1334             SETbit(sq_config, VC_ENABLE_bit);
1335     SETbit(sq_config, DX9_CONSTS_bit);
1336     SETbit(sq_config, ALU_INST_PREFER_VECTOR_bit);
1337     SETfield(sq_config, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1338     SETfield(sq_config, vs_prio, VS_PRIO_shift, VS_PRIO_mask);
1339     SETfield(sq_config, gs_prio, GS_PRIO_shift, GS_PRIO_mask);
1340     SETfield(sq_config, es_prio, ES_PRIO_shift, ES_PRIO_mask);
1341
1342     sq_gpr_resource_mgmt_1 = 0;
1343     SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1344     SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1345     SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
1346              NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1347
1348     sq_gpr_resource_mgmt_2 = 0;
1349     SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1350     SETfield(sq_gpr_resource_mgmt_2, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1351
1352     sq_thread_resource_mgmt = 0;
1353     SETfield(sq_thread_resource_mgmt, num_ps_threads,
1354              NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1355     SETfield(sq_thread_resource_mgmt, num_vs_threads,
1356              NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1357     SETfield(sq_thread_resource_mgmt, num_gs_threads,
1358              NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1359     SETfield(sq_thread_resource_mgmt, num_es_threads,
1360              NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1361
1362     sq_stack_resource_mgmt_1 = 0;
1363     SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
1364              NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1365     SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
1366              NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1367
1368     sq_stack_resource_mgmt_2 = 0;
1369     SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
1370              NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1371     SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
1372              NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1373
1374     ta_cntl_aux = 0;
1375     SETfield(ta_cntl_aux, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1376     db_watermarks = 0;
1377     SETfield(db_watermarks, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1378     SETfield(db_watermarks, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1379     SETfield(db_watermarks, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1380     SETfield(db_watermarks, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1381     sq_dyn_gpr_cntl_ps_flush_req = 0;
1382     db_debug = 0;
1383     if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1384             SETfield(ta_cntl_aux, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1385             db_debug = 0x82000000;
1386             SETfield(db_watermarks, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1387     } else {
1388             SETfield(ta_cntl_aux, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1389             SETfield(db_watermarks, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1390             SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
1391     }
1392
1393     BEGIN_BATCH_NO_AUTOSTATE(117);
1394     R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
1395     R600_OUT_BATCH(sq_config);
1396     R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
1397     R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
1398     R600_OUT_BATCH(sq_thread_resource_mgmt);
1399     R600_OUT_BATCH(sq_stack_resource_mgmt_1);
1400     R600_OUT_BATCH(sq_stack_resource_mgmt_2);
1401
1402     R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, ta_cntl_aux);
1403     R600_OUT_BATCH_REGVAL(VC_ENHANCE, 0);
1404     R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, sq_dyn_gpr_cntl_ps_flush_req);
1405     R600_OUT_BATCH_REGVAL(DB_DEBUG, db_debug);
1406     R600_OUT_BATCH_REGVAL(DB_WATERMARKS, db_watermarks);
1407
1408     R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
1409     R600_OUT_BATCH(0);
1410     R600_OUT_BATCH(0);
1411     R600_OUT_BATCH(0);
1412     R600_OUT_BATCH(0);
1413     R600_OUT_BATCH(0);
1414     R600_OUT_BATCH(0);
1415     R600_OUT_BATCH(0);
1416     R600_OUT_BATCH(0);
1417     R600_OUT_BATCH(0);
1418
1419     R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL,
1420                          (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
1421     R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
1422     R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
1423     R600_OUT_BATCH_REGVAL(DB_DEPTH_INFO, 0);
1424     R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
1425     R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
1426     R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
1427     R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
1428     R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, (0xcc << ROP3_shift));
1429
1430     R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, VTX_XY_FMT_bit);
1431     R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, 0);
1432     R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, CLIP_DISABLE_bit);
1433     R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, (FACE_bit) |
1434         (POLYMODE_PTYPE__TRIANGLES << POLYMODE_FRONT_PTYPE_shift) |
1435         (POLYMODE_PTYPE__TRIANGLES << POLYMODE_BACK_PTYPE_shift));
1436     R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL, (PIX_CENTER_bit) |
1437         (X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
1438         (X_1_256TH << QUANT_MODE_shift));
1439
1440     R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1441     R600_OUT_BATCH(2048);
1442     R600_OUT_BATCH(0);
1443     R600_OUT_BATCH(0);
1444     R600_OUT_BATCH(0);
1445
1446     R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1447     R600_OUT_BATCH(0);
1448     R600_OUT_BATCH(0);
1449     R600_OUT_BATCH(0);
1450     R600_OUT_BATCH(0);
1451     R600_OUT_BATCH(0);
1452     R600_OUT_BATCH(0);
1453     R600_OUT_BATCH(0);
1454     R600_OUT_BATCH(0);
1455     R600_OUT_BATCH(0);
1456     R600_OUT_BATCH(0);
1457     R600_OUT_BATCH(0);
1458     R600_OUT_BATCH(0);
1459     R600_OUT_BATCH(0);
1460
1461     R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, 0);
1462     R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, 0);
1463     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, 0);
1464     R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, 0);
1465
1466     R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1467     R600_OUT_BATCH(0);
1468     R600_OUT_BATCH(0);
1469     R600_OUT_BATCH(0);
1470
1471     R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, 0);
1472
1473     END_BATCH();
1474     COMMIT_BATCH();
1475 }
1476
1477 static GLboolean validate_buffers(context_t *rmesa,
1478                                   struct radeon_bo *src_bo,
1479                                   struct radeon_bo *dst_bo)
1480 {
1481     int ret;
1482     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1483                                       src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
1484
1485     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1486                                       dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
1487
1488     radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
1489                                       rmesa->blit_bo, RADEON_GEM_DOMAIN_GTT, 0);
1490
1491     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1492                                         rmesa->blit_bo,
1493                                         RADEON_GEM_DOMAIN_GTT, 0);
1494     if (ret)
1495         return GL_FALSE;
1496
1497     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1498                                         first_elem(&rmesa->radeon.dma.reserved)->bo,
1499                                         RADEON_GEM_DOMAIN_GTT, 0);
1500     if (ret)
1501         return GL_FALSE;
1502
1503     return GL_TRUE;
1504 }
1505
1506 GLboolean r600_blit(context_t *context,
1507                     struct radeon_bo *src_bo,
1508                     intptr_t src_offset,
1509                     gl_format src_mesaformat,
1510                     unsigned src_pitch,
1511                     unsigned src_width,
1512                     unsigned src_height,
1513                     unsigned src_x,
1514                     unsigned src_y,
1515                     struct radeon_bo *dst_bo,
1516                     intptr_t dst_offset,
1517                     gl_format dst_mesaformat,
1518                     unsigned dst_pitch,
1519                     unsigned dst_width,
1520                     unsigned dst_height,
1521                     unsigned dst_x,
1522                     unsigned dst_y,
1523                     unsigned w,
1524                     unsigned h,
1525                     unsigned flip_y)
1526 {
1527     int id = 0;
1528
1529     /* not sure blit to depth works or not yet */
1530     if (_mesa_get_format_bits(src_mesaformat, GL_DEPTH_BITS) > 0)
1531             return GL_FALSE;
1532
1533     if (src_bo == dst_bo) {
1534         return GL_FALSE;
1535     }
1536
1537     if (0) {
1538         fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1539                 src_width, src_height, src_pitch,
1540                 _mesa_format_row_stride(src_mesaformat, src_width),
1541                 _mesa_get_format_name(src_mesaformat));
1542         fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
1543                 dst_width, dst_height,
1544                 _mesa_format_row_stride(dst_mesaformat, dst_width),
1545                 _mesa_get_format_name(dst_mesaformat));
1546     }
1547
1548     /* Flush is needed to make sure that source buffer has correct data */
1549     radeonFlush(context->radeon.glCtx);
1550
1551     rcommonEnsureCmdBufSpace(&context->radeon, 304, __FUNCTION__);
1552
1553     /* load shaders */
1554     load_shaders(context->radeon.glCtx);
1555
1556     if (!validate_buffers(context, src_bo, dst_bo))
1557         return GL_FALSE;
1558
1559     /* set clear state */
1560     /* 117 */
1561     set_default_state(context);
1562
1563     /* shaders */
1564     /* 72 */
1565     set_shaders(context);
1566
1567     /* src */
1568     /* 20 */
1569     set_tex_resource(context, src_mesaformat, src_bo,
1570                      src_width, src_height, src_pitch, src_offset);
1571
1572     /* 5 */
1573     set_tex_sampler(context);
1574
1575     /* dst */
1576     /* 27 */
1577     set_render_target(context, dst_bo, dst_mesaformat,
1578                       dst_pitch, dst_width, dst_height, dst_offset);
1579     /* scissors */
1580     /* 17 */
1581     set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
1582
1583     set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
1584     /* Vertex buffer setup */
1585     /* 24 */
1586     set_vtx_resource(context);
1587
1588     /* draw */
1589     /* 10 */
1590     draw_auto(context);
1591
1592     /* 7 */
1593     r700SyncSurf(context, dst_bo, 0,
1594                  RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
1595                  CB_ACTION_ENA_bit | (1 << (id + 6)));
1596
1597     /* 5 */
1598     r700WaitForIdleClean(context);
1599
1600     radeonFlush(context->radeon.glCtx);
1601
1602     return GL_TRUE;
1603 }