2 * Copyright (C) 2009 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "r600_context.h"
31 #include "r600_blit.h"
32 #include "r600_blit_shaders.h"
33 #include "r600_cmdbuf.h"
35 /* common formats supported as both textures and render targets */
36 unsigned r600_check_blit(gl_format mesa_format
)
38 switch (mesa_format
) {
39 case MESA_FORMAT_RGBA8888
:
40 case MESA_FORMAT_SIGNED_RGBA8888
:
41 case MESA_FORMAT_RGBA8888_REV
:
42 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
43 case MESA_FORMAT_ARGB8888
:
44 case MESA_FORMAT_XRGB8888
:
45 case MESA_FORMAT_ARGB8888_REV
:
46 case MESA_FORMAT_XRGB8888_REV
:
47 case MESA_FORMAT_RGB565
:
48 case MESA_FORMAT_RGB565_REV
:
49 case MESA_FORMAT_ARGB4444
:
50 case MESA_FORMAT_ARGB4444_REV
:
51 case MESA_FORMAT_ARGB1555
:
52 case MESA_FORMAT_ARGB1555_REV
:
53 case MESA_FORMAT_AL88
:
54 case MESA_FORMAT_AL88_REV
:
55 case MESA_FORMAT_RGB332
:
59 case MESA_FORMAT_RGBA_FLOAT32
:
60 case MESA_FORMAT_RGBA_FLOAT16
:
61 case MESA_FORMAT_ALPHA_FLOAT32
:
62 case MESA_FORMAT_ALPHA_FLOAT16
:
63 case MESA_FORMAT_LUMINANCE_FLOAT32
:
64 case MESA_FORMAT_LUMINANCE_FLOAT16
:
65 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
66 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
67 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
68 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
69 case MESA_FORMAT_X8_Z24
:
70 case MESA_FORMAT_S8_Z24
:
71 case MESA_FORMAT_Z24_S8
:
74 case MESA_FORMAT_SARGB8
:
75 case MESA_FORMAT_SLA8
:
83 /* not sure blit to depth works or not yet */
84 if (_mesa_get_format_bits(mesa_format
, GL_DEPTH_BITS
) > 0)
91 set_render_target(context_t
*context
, struct radeon_bo
*bo
, gl_format mesa_format
,
92 int nPitchInPixel
, int w
, int h
, intptr_t dst_offset
)
94 uint32_t cb_color0_base
, cb_color0_size
= 0, cb_color0_info
= 0, cb_color0_view
= 0;
96 uint32_t endian
, comp_swap
, format
;
97 BATCH_LOCALS(&context
->radeon
);
99 cb_color0_base
= dst_offset
/ 256;
100 endian
= ENDIAN_NONE
;
102 SETfield(cb_color0_size
, (nPitchInPixel
/ 8) - 1,
103 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
104 SETfield(cb_color0_size
, ((nPitchInPixel
* h
) / 64) - 1,
105 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
);
107 SETfield(cb_color0_info
, ARRAY_LINEAR_GENERAL
,
108 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
110 SETbit(cb_color0_info
, BLEND_BYPASS_bit
);
112 switch(mesa_format
) {
113 case MESA_FORMAT_RGBA8888
:
114 #ifdef MESA_BIG_ENDIAN
115 endian
= ENDIAN_8IN32
;
117 format
= COLOR_8_8_8_8
;
118 comp_swap
= SWAP_STD_REV
;
119 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
120 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
122 case MESA_FORMAT_SIGNED_RGBA8888
:
123 #ifdef MESA_BIG_ENDIAN
124 endian
= ENDIAN_8IN32
;
126 format
= COLOR_8_8_8_8
;
127 comp_swap
= SWAP_STD_REV
;
128 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
129 SETfield(cb_color0_info
, NUMBER_SNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
131 case MESA_FORMAT_RGBA8888_REV
:
132 #ifdef MESA_BIG_ENDIAN
133 endian
= ENDIAN_8IN32
;
135 format
= COLOR_8_8_8_8
;
136 comp_swap
= SWAP_STD
;
137 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
138 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
140 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
141 #ifdef MESA_BIG_ENDIAN
142 endian
= ENDIAN_8IN32
;
144 format
= COLOR_8_8_8_8
;
145 comp_swap
= SWAP_STD
;
146 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
147 SETfield(cb_color0_info
, NUMBER_SNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
149 case MESA_FORMAT_ARGB8888
:
150 case MESA_FORMAT_XRGB8888
:
151 #ifdef MESA_BIG_ENDIAN
152 endian
= ENDIAN_8IN32
;
154 format
= COLOR_8_8_8_8
;
155 comp_swap
= SWAP_ALT
;
156 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
157 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
159 case MESA_FORMAT_ARGB8888_REV
:
160 case MESA_FORMAT_XRGB8888_REV
:
161 #ifdef MESA_BIG_ENDIAN
162 endian
= ENDIAN_8IN32
;
164 format
= COLOR_8_8_8_8
;
165 comp_swap
= SWAP_ALT_REV
;
166 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
167 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
169 case MESA_FORMAT_RGB565
:
170 #ifdef MESA_BIG_ENDIAN
171 endian
= ENDIAN_8IN16
;
173 comp_swap
= SWAP_STD_REV
;
174 format
= COLOR_5_6_5
;
175 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
176 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
178 case MESA_FORMAT_RGB565_REV
:
179 #ifdef MESA_BIG_ENDIAN
180 endian
= ENDIAN_8IN16
;
182 comp_swap
= SWAP_STD
;
183 format
= COLOR_5_6_5
;
184 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
185 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
187 case MESA_FORMAT_ARGB4444
:
188 #ifdef MESA_BIG_ENDIAN
189 endian
= ENDIAN_8IN16
;
191 format
= COLOR_4_4_4_4
;
192 comp_swap
= SWAP_ALT
;
193 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
194 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
196 case MESA_FORMAT_ARGB4444_REV
:
197 #ifdef MESA_BIG_ENDIAN
198 endian
= ENDIAN_8IN16
;
200 format
= COLOR_4_4_4_4
;
201 comp_swap
= SWAP_ALT_REV
;
202 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
203 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
205 case MESA_FORMAT_ARGB1555
:
206 #ifdef MESA_BIG_ENDIAN
207 endian
= ENDIAN_8IN16
;
209 format
= COLOR_1_5_5_5
;
210 comp_swap
= SWAP_ALT
;
211 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
212 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
214 case MESA_FORMAT_ARGB1555_REV
:
215 #ifdef MESA_BIG_ENDIAN
216 endian
= ENDIAN_8IN16
;
218 format
= COLOR_1_5_5_5
;
219 comp_swap
= SWAP_ALT_REV
;
220 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
221 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
223 case MESA_FORMAT_AL88
:
224 #ifdef MESA_BIG_ENDIAN
225 endian
= ENDIAN_8IN16
;
228 comp_swap
= SWAP_STD
;
229 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
230 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
232 case MESA_FORMAT_AL88_REV
:
233 #ifdef MESA_BIG_ENDIAN
234 endian
= ENDIAN_8IN16
;
237 comp_swap
= SWAP_STD_REV
;
238 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
239 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
241 case MESA_FORMAT_RGB332
:
242 format
= COLOR_3_3_2
;
243 comp_swap
= SWAP_STD_REV
;
244 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
245 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
249 comp_swap
= SWAP_ALT_REV
;
250 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
251 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
255 comp_swap
= SWAP_STD
;
256 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
257 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
261 comp_swap
= SWAP_ALT
;
262 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
263 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
265 case MESA_FORMAT_RGBA_FLOAT32
:
266 #ifdef MESA_BIG_ENDIAN
267 endian
= ENDIAN_8IN32
;
269 format
= COLOR_32_32_32_32_FLOAT
;
270 comp_swap
= SWAP_STD
;
271 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
272 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
273 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
275 case MESA_FORMAT_RGBA_FLOAT16
:
276 #ifdef MESA_BIG_ENDIAN
277 endian
= ENDIAN_8IN16
;
279 format
= COLOR_16_16_16_16_FLOAT
;
280 comp_swap
= SWAP_STD
;
281 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
282 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
284 case MESA_FORMAT_ALPHA_FLOAT32
:
285 #ifdef MESA_BIG_ENDIAN
286 endian
= ENDIAN_8IN32
;
288 format
= COLOR_32_FLOAT
;
289 comp_swap
= SWAP_ALT_REV
;
290 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
291 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
292 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
294 case MESA_FORMAT_ALPHA_FLOAT16
:
295 #ifdef MESA_BIG_ENDIAN
296 endian
= ENDIAN_8IN16
;
298 format
= COLOR_16_FLOAT
;
299 comp_swap
= SWAP_ALT_REV
;
300 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
301 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
303 case MESA_FORMAT_LUMINANCE_FLOAT32
:
304 #ifdef MESA_BIG_ENDIAN
305 endian
= ENDIAN_8IN32
;
307 format
= COLOR_32_FLOAT
;
308 comp_swap
= SWAP_ALT
;
309 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
310 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
311 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
313 case MESA_FORMAT_LUMINANCE_FLOAT16
:
314 #ifdef MESA_BIG_ENDIAN
315 endian
= ENDIAN_8IN16
;
317 format
= COLOR_16_FLOAT
;
318 comp_swap
= SWAP_ALT
;
319 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
320 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
322 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
323 #ifdef MESA_BIG_ENDIAN
324 endian
= ENDIAN_8IN32
;
326 format
= COLOR_32_32_FLOAT
;
327 comp_swap
= SWAP_ALT_REV
;
328 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
329 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
330 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
332 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
333 #ifdef MESA_BIG_ENDIAN
334 endian
= ENDIAN_8IN16
;
336 format
= COLOR_16_16_FLOAT
;
337 comp_swap
= SWAP_ALT_REV
;
338 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
339 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
341 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
342 #ifdef MESA_BIG_ENDIAN
343 endian
= ENDIAN_8IN32
;
345 format
= COLOR_32_FLOAT
;
346 comp_swap
= SWAP_STD
;
347 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
348 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
349 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
351 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
352 #ifdef MESA_BIG_ENDIAN
353 endian
= ENDIAN_8IN16
;
355 format
= COLOR_16_FLOAT
;
356 comp_swap
= SWAP_STD
;
357 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
358 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
360 case MESA_FORMAT_X8_Z24
:
361 case MESA_FORMAT_S8_Z24
:
362 #ifdef MESA_BIG_ENDIAN
363 endian
= ENDIAN_8IN32
;
366 comp_swap
= SWAP_STD
;
367 SETfield(cb_color0_info
, ARRAY_1D_TILED_THIN1
,
368 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
369 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
370 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
372 case MESA_FORMAT_Z24_S8
:
373 #ifdef MESA_BIG_ENDIAN
374 endian
= ENDIAN_8IN32
;
377 comp_swap
= SWAP_STD
;
378 SETfield(cb_color0_info
, ARRAY_1D_TILED_THIN1
,
379 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
380 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
381 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
383 case MESA_FORMAT_Z16
:
384 #ifdef MESA_BIG_ENDIAN
385 endian
= ENDIAN_8IN16
;
388 comp_swap
= SWAP_STD
;
389 SETfield(cb_color0_info
, ARRAY_1D_TILED_THIN1
,
390 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
391 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
392 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
394 case MESA_FORMAT_Z32
:
395 #ifdef MESA_BIG_ENDIAN
396 endian
= ENDIAN_8IN32
;
399 comp_swap
= SWAP_STD
;
400 SETfield(cb_color0_info
, ARRAY_1D_TILED_THIN1
,
401 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
402 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
403 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
405 case MESA_FORMAT_SARGB8
:
406 #ifdef MESA_BIG_ENDIAN
407 endian
= ENDIAN_8IN32
;
409 format
= COLOR_8_8_8_8
;
410 comp_swap
= SWAP_ALT
;
411 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
412 SETfield(cb_color0_info
, NUMBER_SRGB
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
414 case MESA_FORMAT_SLA8
:
415 #ifdef MESA_BIG_ENDIAN
416 endian
= ENDIAN_8IN16
;
419 comp_swap
= SWAP_ALT_REV
;
420 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
421 SETfield(cb_color0_info
, NUMBER_SRGB
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
423 case MESA_FORMAT_SL8
:
425 comp_swap
= SWAP_ALT_REV
;
426 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
427 SETfield(cb_color0_info
, NUMBER_SRGB
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
430 fprintf(stderr
,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format
));
431 assert("Invalid format for US output\n");
435 /* must be 0 on r7xx */
436 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
437 CLEARbit(cb_color0_info
, BLEND_FLOAT32_bit
);
439 SETfield(cb_color0_info
, endian
, ENDIAN_shift
, ENDIAN_mask
);
440 SETfield(cb_color0_info
, format
, CB_COLOR0_INFO__FORMAT_shift
,
441 CB_COLOR0_INFO__FORMAT_mask
);
442 SETfield(cb_color0_info
, comp_swap
, COMP_SWAP_shift
, COMP_SWAP_mask
);
444 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
445 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE
+ (4 * id
), 1);
446 R600_OUT_BATCH(cb_color0_base
);
447 R600_OUT_BATCH_RELOC(0,
450 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
453 if ((context
->radeon
.radeonScreen
->chip_family
> CHIP_FAMILY_R600
) &&
454 (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)) {
455 BEGIN_BATCH_NO_AUTOSTATE(2);
456 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE
, 0));
457 R600_OUT_BATCH((2 << id
));
461 /* Set CMASK & TILE buffer to the offset of color buffer as
462 * we don't use those this shouldn't cause any issue and we
463 * then have a valid cmd stream
465 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
466 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE
+ (4 * id
), 1);
467 R600_OUT_BATCH(cb_color0_base
);
468 R600_OUT_BATCH_RELOC(0,
471 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
473 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
474 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG
+ (4 * id
), 1);
475 R600_OUT_BATCH(cb_color0_base
);
476 R600_OUT_BATCH_RELOC(0,
479 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
482 BEGIN_BATCH_NO_AUTOSTATE(9);
483 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE
+ (4 * id
), cb_color0_size
);
484 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW
+ (4 * id
), cb_color0_view
);
485 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK
+ (4 * id
), 0);
488 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
489 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO
+ (4 * id
), cb_color0_info
);
490 R600_OUT_BATCH_RELOC(0,
493 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
500 static inline void load_shaders(struct gl_context
* ctx
)
503 radeonContextPtr radeonctx
= RADEON_CONTEXT(ctx
);
504 context_t
*context
= R700_CONTEXT(ctx
);
508 if (context
->blit_bo_loaded
== 1)
512 context
->blit_bo
= radeon_bo_open(radeonctx
->radeonScreen
->bom
, 0,
513 size
, 256, RADEON_GEM_DOMAIN_GTT
, 0);
514 radeon_bo_map(context
->blit_bo
, 1);
515 shader
= context
->blit_bo
->ptr
;
517 for(i
=0; i
<sizeof(r6xx_vs
)/4; i
++) {
518 shader
[128+i
] = CPU_TO_LE32(r6xx_vs
[i
]);
520 for(i
=0; i
<sizeof(r6xx_ps
)/4; i
++) {
521 shader
[256+i
] = CPU_TO_LE32(r6xx_ps
[i
]);
524 radeon_bo_unmap(context
->blit_bo
);
525 context
->blit_bo_loaded
= 1;
530 set_shaders(context_t
*context
)
532 struct radeon_bo
* pbo
= context
->blit_bo
;
533 BATCH_LOCALS(&context
->radeon
);
535 uint32_t sq_pgm_start_fs
= (512 >> 8);
536 uint32_t sq_pgm_resources_fs
= 0;
537 uint32_t sq_pgm_cf_offset_fs
= 0;
539 uint32_t sq_pgm_start_vs
= (512 >> 8);
540 uint32_t sq_pgm_resources_vs
= (1 << NUM_GPRS_shift
);
541 uint32_t sq_pgm_cf_offset_vs
= 0;
543 uint32_t sq_pgm_start_ps
= (1024 >> 8);
544 uint32_t sq_pgm_resources_ps
= (1 << NUM_GPRS_shift
);
545 uint32_t sq_pgm_cf_offset_ps
= 0;
546 uint32_t sq_pgm_exports_ps
= (1 << 1);
548 r700SyncSurf(context
, pbo
, RADEON_GEM_DOMAIN_GTT
, 0, SH_ACTION_ENA_bit
);
551 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
552 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS
, 1);
553 R600_OUT_BATCH(sq_pgm_start_fs
);
554 R600_OUT_BATCH_RELOC(sq_pgm_start_fs
,
557 RADEON_GEM_DOMAIN_GTT
, 0, 0);
560 BEGIN_BATCH_NO_AUTOSTATE(6);
561 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS
, sq_pgm_resources_fs
);
562 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS
, sq_pgm_cf_offset_fs
);
566 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
567 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS
, 1);
568 R600_OUT_BATCH(sq_pgm_start_vs
);
569 R600_OUT_BATCH_RELOC(sq_pgm_start_vs
,
572 RADEON_GEM_DOMAIN_GTT
, 0, 0);
575 BEGIN_BATCH_NO_AUTOSTATE(6);
576 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS
, sq_pgm_resources_vs
);
577 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS
, sq_pgm_cf_offset_vs
);
581 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
582 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS
, 1);
583 R600_OUT_BATCH(sq_pgm_start_ps
);
584 R600_OUT_BATCH_RELOC(sq_pgm_start_ps
,
587 RADEON_GEM_DOMAIN_GTT
, 0, 0);
590 BEGIN_BATCH_NO_AUTOSTATE(9);
591 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS
, sq_pgm_resources_ps
);
592 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS
, sq_pgm_exports_ps
);
593 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS
, sq_pgm_cf_offset_ps
);
596 BEGIN_BATCH_NO_AUTOSTATE(18);
597 R600_OUT_BATCH_REGVAL(SPI_VS_OUT_CONFIG
, 0); //EXPORT_COUNT is - 1
598 R600_OUT_BATCH_REGVAL(SPI_VS_OUT_ID_0
, 0);
599 R600_OUT_BATCH_REGVAL(SPI_PS_INPUT_CNTL_0
, SEL_CENTROID_bit
);
600 R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_0
, (1 << NUM_INTERP_shift
));
601 R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_1
, 0);
602 R600_OUT_BATCH_REGVAL(SPI_INTERP_CONTROL_0
, 0);
610 set_vtx_resource(context_t
*context
)
612 struct radeon_bo
*bo
= context
->blit_bo
;
613 uint32_t sq_vtx_constant_word2
= 0;
615 BATCH_LOCALS(&context
->radeon
);
617 BEGIN_BATCH_NO_AUTOSTATE(6);
618 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 1));
619 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
622 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 1));
623 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
628 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
629 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
630 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
631 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
632 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
633 r700SyncSurf(context
, bo
, RADEON_GEM_DOMAIN_GTT
, 0, TC_ACTION_ENA_bit
);
635 r700SyncSurf(context
, bo
, RADEON_GEM_DOMAIN_GTT
, 0, VC_ACTION_ENA_bit
);
637 sq_vtx_constant_word2
= 0
638 #ifdef MESA_BIG_ENDIAN
639 | (SQ_ENDIAN_8IN32
<< SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift
)
641 | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift
);
643 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
645 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE
, 7));
646 R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET
* FETCH_RESOURCE_STRIDE
);
648 R600_OUT_BATCH(48 - 1);
649 R600_OUT_BATCH(sq_vtx_constant_word2
);
650 R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift
);
653 R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER
<< SQ_TEX_RESOURCE_WORD6_0__TYPE_shift
);
654 R600_OUT_BATCH_RELOC(0,
657 RADEON_GEM_DOMAIN_GTT
, 0, 0);
664 set_tex_resource(context_t
* context
,
665 gl_format mesa_format
, struct radeon_bo
*bo
, int w
, int h
,
666 int TexelPitch
, intptr_t src_offset
)
668 uint32_t sq_tex_resource0
, sq_tex_resource1
, sq_tex_resource2
, sq_tex_resource4
, sq_tex_resource6
;
670 sq_tex_resource0
= sq_tex_resource1
= sq_tex_resource2
= sq_tex_resource4
= sq_tex_resource6
= 0;
671 BATCH_LOCALS(&context
->radeon
);
673 SETfield(sq_tex_resource0
, SQ_TEX_DIM_2D
, DIM_shift
, DIM_mask
);
674 SETfield(sq_tex_resource0
, ARRAY_LINEAR_GENERAL
,
675 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
676 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
678 switch (mesa_format
) {
679 case MESA_FORMAT_RGBA8888
:
680 case MESA_FORMAT_SIGNED_RGBA8888
:
681 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
682 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
684 SETfield(sq_tex_resource4
, SQ_SEL_W
,
685 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
686 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
687 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
688 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
689 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
690 SETfield(sq_tex_resource4
, SQ_SEL_X
,
691 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
692 if (mesa_format
== MESA_FORMAT_SIGNED_RGBA8888
) {
693 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
694 FORMAT_COMP_X_shift
, FORMAT_COMP_X_mask
);
695 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
696 FORMAT_COMP_Y_shift
, FORMAT_COMP_Y_mask
);
697 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
698 FORMAT_COMP_Z_shift
, FORMAT_COMP_Z_mask
);
699 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
700 FORMAT_COMP_W_shift
, FORMAT_COMP_W_mask
);
703 case MESA_FORMAT_RGBA8888_REV
:
704 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
705 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
706 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
708 SETfield(sq_tex_resource4
, SQ_SEL_X
,
709 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
710 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
711 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
712 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
713 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
714 SETfield(sq_tex_resource4
, SQ_SEL_W
,
715 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
716 if (mesa_format
== MESA_FORMAT_SIGNED_RGBA8888_REV
) {
717 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
718 FORMAT_COMP_X_shift
, FORMAT_COMP_X_mask
);
719 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
720 FORMAT_COMP_Y_shift
, FORMAT_COMP_Y_mask
);
721 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
722 FORMAT_COMP_Z_shift
, FORMAT_COMP_Z_mask
);
723 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
724 FORMAT_COMP_W_shift
, FORMAT_COMP_W_mask
);
727 case MESA_FORMAT_ARGB8888
:
728 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
729 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
731 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
732 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
733 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
734 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
735 SETfield(sq_tex_resource4
, SQ_SEL_X
,
736 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
737 SETfield(sq_tex_resource4
, SQ_SEL_W
,
738 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
740 case MESA_FORMAT_XRGB8888
:
741 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
742 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
744 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
745 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
746 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
747 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
748 SETfield(sq_tex_resource4
, SQ_SEL_X
,
749 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
750 SETfield(sq_tex_resource4
, SQ_SEL_1
,
751 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
753 case MESA_FORMAT_ARGB8888_REV
:
754 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
755 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
757 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
758 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
759 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
760 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
761 SETfield(sq_tex_resource4
, SQ_SEL_W
,
762 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
763 SETfield(sq_tex_resource4
, SQ_SEL_X
,
764 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
766 case MESA_FORMAT_XRGB8888_REV
:
767 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
768 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
770 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
771 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
772 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
773 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
774 SETfield(sq_tex_resource4
, SQ_SEL_1
,
775 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
776 SETfield(sq_tex_resource4
, SQ_SEL_X
,
777 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
779 case MESA_FORMAT_RGB565
:
780 SETfield(sq_tex_resource1
, FMT_5_6_5
,
781 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
783 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
784 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
785 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
786 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
787 SETfield(sq_tex_resource4
, SQ_SEL_X
,
788 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
789 SETfield(sq_tex_resource4
, SQ_SEL_1
,
790 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
792 case MESA_FORMAT_RGB565_REV
:
793 SETfield(sq_tex_resource1
, FMT_5_6_5
,
794 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
796 SETfield(sq_tex_resource4
, SQ_SEL_X
,
797 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
798 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
799 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
800 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
801 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
802 SETfield(sq_tex_resource4
, SQ_SEL_1
,
803 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
805 case MESA_FORMAT_ARGB4444
:
806 SETfield(sq_tex_resource1
, FMT_4_4_4_4
,
807 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
809 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
810 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
811 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
812 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
813 SETfield(sq_tex_resource4
, SQ_SEL_X
,
814 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
815 SETfield(sq_tex_resource4
, SQ_SEL_W
,
816 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
818 case MESA_FORMAT_ARGB4444_REV
:
819 SETfield(sq_tex_resource1
, FMT_4_4_4_4
,
820 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
822 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
823 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
824 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
825 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
826 SETfield(sq_tex_resource4
, SQ_SEL_W
,
827 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
828 SETfield(sq_tex_resource4
, SQ_SEL_X
,
829 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
831 case MESA_FORMAT_ARGB1555
:
832 SETfield(sq_tex_resource1
, FMT_1_5_5_5
,
833 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
835 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
836 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
837 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
838 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
839 SETfield(sq_tex_resource4
, SQ_SEL_X
,
840 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
841 SETfield(sq_tex_resource4
, SQ_SEL_W
,
842 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
844 case MESA_FORMAT_ARGB1555_REV
:
845 SETfield(sq_tex_resource1
, FMT_1_5_5_5
,
846 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
848 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
849 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
850 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
851 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
852 SETfield(sq_tex_resource4
, SQ_SEL_W
,
853 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
854 SETfield(sq_tex_resource4
, SQ_SEL_X
,
855 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
857 case MESA_FORMAT_AL88
:
858 case MESA_FORMAT_AL88_REV
: /* TODO : Check this. */
859 SETfield(sq_tex_resource1
, FMT_8_8
,
860 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
862 SETfield(sq_tex_resource4
, SQ_SEL_X
,
863 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
864 SETfield(sq_tex_resource4
, SQ_SEL_X
,
865 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
866 SETfield(sq_tex_resource4
, SQ_SEL_X
,
867 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
868 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
869 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
871 case MESA_FORMAT_RGB332
:
872 SETfield(sq_tex_resource1
, FMT_3_3_2
,
873 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
875 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
876 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
877 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
878 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
879 SETfield(sq_tex_resource4
, SQ_SEL_X
,
880 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
881 SETfield(sq_tex_resource4
, SQ_SEL_1
,
882 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
884 case MESA_FORMAT_A8
: /* ZERO, ZERO, ZERO, X */
885 SETfield(sq_tex_resource1
, FMT_8
,
886 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
888 SETfield(sq_tex_resource4
, SQ_SEL_0
,
889 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
890 SETfield(sq_tex_resource4
, SQ_SEL_0
,
891 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
892 SETfield(sq_tex_resource4
, SQ_SEL_0
,
893 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
894 SETfield(sq_tex_resource4
, SQ_SEL_X
,
895 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
897 case MESA_FORMAT_L8
: /* X, X, X, ONE */
898 SETfield(sq_tex_resource1
, FMT_8
,
899 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
901 SETfield(sq_tex_resource4
, SQ_SEL_X
,
902 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
903 SETfield(sq_tex_resource4
, SQ_SEL_X
,
904 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
905 SETfield(sq_tex_resource4
, SQ_SEL_X
,
906 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
907 SETfield(sq_tex_resource4
, SQ_SEL_1
,
908 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
910 case MESA_FORMAT_I8
: /* X, X, X, X */
911 SETfield(sq_tex_resource1
, FMT_8
,
912 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
914 SETfield(sq_tex_resource4
, SQ_SEL_X
,
915 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
916 SETfield(sq_tex_resource4
, SQ_SEL_X
,
917 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
918 SETfield(sq_tex_resource4
, SQ_SEL_X
,
919 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
920 SETfield(sq_tex_resource4
, SQ_SEL_X
,
921 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
923 case MESA_FORMAT_RGBA_FLOAT32
:
924 SETfield(sq_tex_resource1
, FMT_32_32_32_32_FLOAT
,
925 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
927 SETfield(sq_tex_resource4
, SQ_SEL_X
,
928 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
929 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
930 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
931 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
932 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
933 SETfield(sq_tex_resource4
, SQ_SEL_W
,
934 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
936 case MESA_FORMAT_RGBA_FLOAT16
:
937 SETfield(sq_tex_resource1
, FMT_16_16_16_16_FLOAT
,
938 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
940 SETfield(sq_tex_resource4
, SQ_SEL_X
,
941 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
942 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
943 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
944 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
945 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
946 SETfield(sq_tex_resource4
, SQ_SEL_W
,
947 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
949 case MESA_FORMAT_ALPHA_FLOAT32
: /* ZERO, ZERO, ZERO, X */
950 SETfield(sq_tex_resource1
, FMT_32_FLOAT
,
951 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
953 SETfield(sq_tex_resource4
, SQ_SEL_0
,
954 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
955 SETfield(sq_tex_resource4
, SQ_SEL_0
,
956 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
957 SETfield(sq_tex_resource4
, SQ_SEL_0
,
958 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
959 SETfield(sq_tex_resource4
, SQ_SEL_X
,
960 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
962 case MESA_FORMAT_ALPHA_FLOAT16
: /* ZERO, ZERO, ZERO, X */
963 SETfield(sq_tex_resource1
, FMT_16_FLOAT
,
964 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
966 SETfield(sq_tex_resource4
, SQ_SEL_0
,
967 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
968 SETfield(sq_tex_resource4
, SQ_SEL_0
,
969 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
970 SETfield(sq_tex_resource4
, SQ_SEL_0
,
971 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
972 SETfield(sq_tex_resource4
, SQ_SEL_X
,
973 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
975 case MESA_FORMAT_LUMINANCE_FLOAT32
: /* X, X, X, ONE */
976 SETfield(sq_tex_resource1
, FMT_32_FLOAT
,
977 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
979 SETfield(sq_tex_resource4
, SQ_SEL_X
,
980 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
981 SETfield(sq_tex_resource4
, SQ_SEL_X
,
982 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
983 SETfield(sq_tex_resource4
, SQ_SEL_X
,
984 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
985 SETfield(sq_tex_resource4
, SQ_SEL_1
,
986 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
988 case MESA_FORMAT_LUMINANCE_FLOAT16
: /* X, X, X, ONE */
989 SETfield(sq_tex_resource1
, FMT_16_FLOAT
,
990 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
992 SETfield(sq_tex_resource4
, SQ_SEL_X
,
993 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
994 SETfield(sq_tex_resource4
, SQ_SEL_X
,
995 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
996 SETfield(sq_tex_resource4
, SQ_SEL_X
,
997 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
998 SETfield(sq_tex_resource4
, SQ_SEL_1
,
999 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1001 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
1002 SETfield(sq_tex_resource1
, FMT_32_32_FLOAT
,
1003 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1005 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1006 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1007 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1008 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1009 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1010 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1011 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1012 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1014 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
1015 SETfield(sq_tex_resource1
, FMT_16_16_FLOAT
,
1016 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1018 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1019 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1020 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1021 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1022 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1023 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1024 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1025 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1027 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
1028 SETfield(sq_tex_resource1
, FMT_32_FLOAT
,
1029 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1031 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1032 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1033 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1034 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1035 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1036 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1037 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1038 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1040 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
1041 SETfield(sq_tex_resource1
, FMT_16_FLOAT
,
1042 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1044 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1045 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1046 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1047 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1048 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1049 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1050 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1051 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1053 case MESA_FORMAT_Z16
:
1054 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1055 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1056 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1057 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1058 SETfield(sq_tex_resource1
, FMT_16
,
1059 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1060 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1061 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1062 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1063 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1064 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1065 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1066 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1067 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1069 case MESA_FORMAT_X8_Z24
:
1070 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1071 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1072 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1073 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1074 SETfield(sq_tex_resource1
, FMT_8_24
,
1075 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1076 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1077 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1078 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1079 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1080 SETfield(sq_tex_resource4
, SQ_SEL_0
,
1081 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1082 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1083 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1085 case MESA_FORMAT_S8_Z24
:
1086 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1087 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1088 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1089 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1090 SETfield(sq_tex_resource1
, FMT_8_24
,
1091 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1092 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1093 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1094 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1095 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1096 SETfield(sq_tex_resource4
, SQ_SEL_0
,
1097 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1098 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1099 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1101 case MESA_FORMAT_Z24_S8
:
1102 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1103 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1104 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1105 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1106 SETfield(sq_tex_resource1
, FMT_24_8
,
1107 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1108 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1109 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1110 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1111 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1112 SETfield(sq_tex_resource4
, SQ_SEL_0
,
1113 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1114 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1115 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1117 case MESA_FORMAT_Z32
:
1118 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1119 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1120 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1121 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1122 SETfield(sq_tex_resource1
, FMT_32
,
1123 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1124 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1125 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1126 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1127 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1128 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1129 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1130 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1131 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1133 case MESA_FORMAT_S8
:
1134 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1135 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1136 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1137 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1138 SETfield(sq_tex_resource1
, FMT_8
,
1139 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1140 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1141 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1142 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1143 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1144 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1145 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1146 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1147 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1149 case MESA_FORMAT_SARGB8
:
1150 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
1151 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1153 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
1154 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1155 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1156 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1157 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1158 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1159 SETfield(sq_tex_resource4
, SQ_SEL_W
,
1160 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1161 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1163 case MESA_FORMAT_SLA8
:
1164 SETfield(sq_tex_resource1
, FMT_8_8
,
1165 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1167 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1168 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1169 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1170 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1171 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1172 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1173 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1174 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1175 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1177 case MESA_FORMAT_SL8
: /* X, X, X, ONE */
1178 SETfield(sq_tex_resource1
, FMT_8
,
1179 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1181 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1182 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1183 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1184 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1185 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1186 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1187 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1188 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1189 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1192 fprintf(stderr
,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format
));
1193 assert("Invalid format for US output\n");
1197 SETfield(sq_tex_resource0
, (TexelPitch
/8)-1, PITCH_shift
, PITCH_mask
);
1198 SETfield(sq_tex_resource0
, w
- 1, TEX_WIDTH_shift
, TEX_WIDTH_mask
);
1199 SETfield(sq_tex_resource1
, h
- 1, TEX_HEIGHT_shift
, TEX_HEIGHT_mask
);
1201 sq_tex_resource2
= src_offset
/ 256;
1203 SETfield(sq_tex_resource6
, SQ_TEX_VTX_VALID_TEXTURE
,
1204 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift
,
1205 SQ_TEX_RESOURCE_WORD6_0__TYPE_mask
);
1207 r700SyncSurf(context
, bo
,
1208 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
,
1209 0, TC_ACTION_ENA_bit
);
1211 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
1212 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE
, 7));
1213 R600_OUT_BATCH(0 * 7);
1215 R600_OUT_BATCH(sq_tex_resource0
);
1216 R600_OUT_BATCH(sq_tex_resource1
);
1217 R600_OUT_BATCH(sq_tex_resource2
);
1218 R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
1219 R600_OUT_BATCH(sq_tex_resource4
);
1220 R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
1221 R600_OUT_BATCH(sq_tex_resource6
);
1222 R600_OUT_BATCH_RELOC(0,
1225 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
1226 R600_OUT_BATCH_RELOC(0,
1229 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
1235 set_tex_sampler(context_t
* context
)
1237 uint32_t sq_tex_sampler_word0
= 0, sq_tex_sampler_word1
= 0, sq_tex_sampler_word2
= 0;
1240 SETbit(sq_tex_sampler_word2
, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit
);
1242 BATCH_LOCALS(&context
->radeon
);
1244 BEGIN_BATCH_NO_AUTOSTATE(5);
1245 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER
, 3));
1246 R600_OUT_BATCH(i
* 3);
1247 R600_OUT_BATCH(sq_tex_sampler_word0
);
1248 R600_OUT_BATCH(sq_tex_sampler_word1
);
1249 R600_OUT_BATCH(sq_tex_sampler_word2
);
1255 set_scissors(context_t
*context
, int x1
, int y1
, int x2
, int y2
)
1257 BATCH_LOCALS(&context
->radeon
);
1259 BEGIN_BATCH_NO_AUTOSTATE(17);
1260 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL
, 2);
1261 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16));
1262 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1264 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET
, 3);
1265 R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1266 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
)); //PA_SC_WINDOW_SCISSOR_TL
1267 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1269 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL
, 2);
1270 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
));
1271 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1273 /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1274 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL
, 2 );
1275 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
));
1276 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1284 set_vb_data(context_t
* context
, int src_x
, int src_y
, int dst_x
, int dst_y
,
1285 int w
, int h
, int src_h
, unsigned flip_y
)
1288 radeon_bo_map(context
->blit_bo
, 1);
1289 vb
= context
->blit_bo
->ptr
;
1291 vb
[0] = (float)(dst_x
);
1292 vb
[1] = (float)(dst_y
);
1293 vb
[2] = (float)(src_x
);
1294 vb
[3] = (flip_y
) ? (float)(src_h
- src_y
) : (float)src_y
;
1296 vb
[4] = (float)(dst_x
);
1297 vb
[5] = (float)(dst_y
+ h
);
1298 vb
[6] = (float)(src_x
);
1299 vb
[7] = (flip_y
) ? (float)(src_h
- (src_y
+ h
)) : (float)(src_y
+ h
);
1301 vb
[8] = (float)(dst_x
+ w
);
1302 vb
[9] = (float)(dst_y
+ h
);
1303 vb
[10] = (float)(src_x
+ w
);
1304 vb
[11] = (flip_y
) ? (float)(src_h
- (src_y
+ h
)) : (float)(src_y
+ h
);
1306 radeon_bo_unmap(context
->blit_bo
);
1311 draw_auto(context_t
*context
)
1313 BATCH_LOCALS(&context
->radeon
);
1314 uint32_t vgt_primitive_type
= 0, vgt_index_type
= 0, vgt_draw_initiator
= 0, vgt_num_indices
;
1316 SETfield(vgt_primitive_type
, DI_PT_RECTLIST
,
1317 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
,
1318 VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
1319 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
,
1321 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
,
1323 SETfield(vgt_draw_initiator
, DI_SRC_SEL_AUTO_INDEX
, SOURCE_SELECT_shift
,
1324 SOURCE_SELECT_mask
);
1326 vgt_num_indices
= 3;
1328 BEGIN_BATCH_NO_AUTOSTATE(10);
1330 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE
, 1);
1331 R600_OUT_BATCH(vgt_primitive_type
);
1333 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
1334 R600_OUT_BATCH(vgt_index_type
);
1336 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
1339 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO
, 1));
1340 R600_OUT_BATCH(vgt_num_indices
);
1341 R600_OUT_BATCH(vgt_draw_initiator
);
1348 set_default_state(context_t
*context
)
1363 int num_ps_stack_entries
;
1364 int num_vs_stack_entries
;
1365 int num_gs_stack_entries
;
1366 int num_es_stack_entries
;
1367 uint32_t sq_config
, sq_gpr_resource_mgmt_1
, sq_gpr_resource_mgmt_2
;
1368 uint32_t sq_thread_resource_mgmt
, sq_stack_resource_mgmt_1
, sq_stack_resource_mgmt_2
;
1369 uint32_t ta_cntl_aux
, db_watermarks
, sq_dyn_gpr_cntl_ps_flush_req
, db_debug
;
1370 BATCH_LOCALS(&context
->radeon
);
1372 switch (context
->radeon
.radeonScreen
->chip_family
) {
1373 case CHIP_FAMILY_R600
:
1379 num_ps_threads
= 136;
1380 num_vs_threads
= 48;
1383 num_ps_stack_entries
= 128;
1384 num_vs_stack_entries
= 128;
1385 num_gs_stack_entries
= 0;
1386 num_es_stack_entries
= 0;
1388 case CHIP_FAMILY_RV630
:
1389 case CHIP_FAMILY_RV635
:
1395 num_ps_threads
= 144;
1396 num_vs_threads
= 40;
1399 num_ps_stack_entries
= 40;
1400 num_vs_stack_entries
= 40;
1401 num_gs_stack_entries
= 32;
1402 num_es_stack_entries
= 16;
1404 case CHIP_FAMILY_RV610
:
1405 case CHIP_FAMILY_RV620
:
1406 case CHIP_FAMILY_RS780
:
1407 case CHIP_FAMILY_RS880
:
1414 num_ps_threads
= 136;
1415 num_vs_threads
= 48;
1418 num_ps_stack_entries
= 40;
1419 num_vs_stack_entries
= 40;
1420 num_gs_stack_entries
= 32;
1421 num_es_stack_entries
= 16;
1423 case CHIP_FAMILY_RV670
:
1429 num_ps_threads
= 136;
1430 num_vs_threads
= 48;
1433 num_ps_stack_entries
= 40;
1434 num_vs_stack_entries
= 40;
1435 num_gs_stack_entries
= 32;
1436 num_es_stack_entries
= 16;
1438 case CHIP_FAMILY_RV770
:
1444 num_ps_threads
= 188;
1445 num_vs_threads
= 60;
1448 num_ps_stack_entries
= 256;
1449 num_vs_stack_entries
= 256;
1450 num_gs_stack_entries
= 0;
1451 num_es_stack_entries
= 0;
1453 case CHIP_FAMILY_RV730
:
1454 case CHIP_FAMILY_RV740
:
1460 num_ps_threads
= 188;
1461 num_vs_threads
= 60;
1464 num_ps_stack_entries
= 128;
1465 num_vs_stack_entries
= 128;
1466 num_gs_stack_entries
= 0;
1467 num_es_stack_entries
= 0;
1469 case CHIP_FAMILY_RV710
:
1475 num_ps_threads
= 144;
1476 num_vs_threads
= 48;
1479 num_ps_stack_entries
= 128;
1480 num_vs_stack_entries
= 128;
1481 num_gs_stack_entries
= 0;
1482 num_es_stack_entries
= 0;
1487 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1488 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1489 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1490 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1491 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1492 CLEARbit(sq_config
, VC_ENABLE_bit
);
1494 SETbit(sq_config
, VC_ENABLE_bit
);
1495 SETbit(sq_config
, DX9_CONSTS_bit
);
1496 SETbit(sq_config
, ALU_INST_PREFER_VECTOR_bit
);
1497 SETfield(sq_config
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1498 SETfield(sq_config
, vs_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1499 SETfield(sq_config
, gs_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1500 SETfield(sq_config
, es_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1502 sq_gpr_resource_mgmt_1
= 0;
1503 SETfield(sq_gpr_resource_mgmt_1
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1504 SETfield(sq_gpr_resource_mgmt_1
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1505 SETfield(sq_gpr_resource_mgmt_1
, num_temp_gprs
,
1506 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1508 sq_gpr_resource_mgmt_2
= 0;
1509 SETfield(sq_gpr_resource_mgmt_2
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1510 SETfield(sq_gpr_resource_mgmt_2
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1512 sq_thread_resource_mgmt
= 0;
1513 SETfield(sq_thread_resource_mgmt
, num_ps_threads
,
1514 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1515 SETfield(sq_thread_resource_mgmt
, num_vs_threads
,
1516 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1517 SETfield(sq_thread_resource_mgmt
, num_gs_threads
,
1518 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1519 SETfield(sq_thread_resource_mgmt
, num_es_threads
,
1520 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1522 sq_stack_resource_mgmt_1
= 0;
1523 SETfield(sq_stack_resource_mgmt_1
, num_ps_stack_entries
,
1524 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1525 SETfield(sq_stack_resource_mgmt_1
, num_vs_stack_entries
,
1526 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1528 sq_stack_resource_mgmt_2
= 0;
1529 SETfield(sq_stack_resource_mgmt_2
, num_gs_stack_entries
,
1530 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1531 SETfield(sq_stack_resource_mgmt_2
, num_es_stack_entries
,
1532 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1535 SETfield(ta_cntl_aux
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1537 SETfield(db_watermarks
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1538 SETfield(db_watermarks
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1539 SETfield(db_watermarks
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1540 SETfield(db_watermarks
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1541 sq_dyn_gpr_cntl_ps_flush_req
= 0;
1543 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1544 SETfield(ta_cntl_aux
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1545 db_debug
= 0x82000000;
1546 SETfield(db_watermarks
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1548 SETfield(ta_cntl_aux
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1549 SETfield(db_watermarks
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1550 SETbit(sq_dyn_gpr_cntl_ps_flush_req
, VS_PC_LIMIT_ENABLE_bit
);
1553 BEGIN_BATCH_NO_AUTOSTATE(120);
1554 R600_OUT_BATCH_REGSEQ(SQ_CONFIG
, 6);
1555 R600_OUT_BATCH(sq_config
);
1556 R600_OUT_BATCH(sq_gpr_resource_mgmt_1
);
1557 R600_OUT_BATCH(sq_gpr_resource_mgmt_2
);
1558 R600_OUT_BATCH(sq_thread_resource_mgmt
);
1559 R600_OUT_BATCH(sq_stack_resource_mgmt_1
);
1560 R600_OUT_BATCH(sq_stack_resource_mgmt_2
);
1562 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX
, ta_cntl_aux
);
1563 R600_OUT_BATCH_REGVAL(VC_ENHANCE
, 0);
1564 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, sq_dyn_gpr_cntl_ps_flush_req
);
1565 R600_OUT_BATCH_REGVAL(DB_DEBUG
, db_debug
);
1566 R600_OUT_BATCH_REGVAL(DB_WATERMARKS
, db_watermarks
);
1568 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE
, 9);
1579 R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL
,
1580 (CLRCMP_SEL_SRC
<< CLRCMP_FCN_SEL_shift
));
1581 R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC
, 0);
1582 R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC
, 0);
1583 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL
, 0);
1584 R600_OUT_BATCH_REGVAL(CB_SHADER_MASK
, (OUTPUT0_ENABLE_mask
));
1585 R600_OUT_BATCH_REGVAL(CB_TARGET_MASK
, (TARGET0_ENABLE_mask
));
1586 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL
, (RT0_ENABLE_bit
));
1587 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL
, (0xcc << ROP3_shift
));
1589 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL
, VTX_XY_FMT_bit
);
1590 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL
, 0);
1591 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL
, CLIP_DISABLE_bit
);
1592 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL
, (FACE_bit
) |
1593 (POLYMODE_PTYPE__TRIANGLES
<< POLYMODE_FRONT_PTYPE_shift
) |
1594 (POLYMODE_PTYPE__TRIANGLES
<< POLYMODE_BACK_PTYPE_shift
));
1595 R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL
, (PIX_CENTER_bit
) |
1596 (X_ROUND_TO_EVEN
<< PA_SU_VTX_CNTL__ROUND_MODE_shift
) |
1597 (X_1_256TH
<< QUANT_MODE_shift
));
1598 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG
, 0);
1600 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX
, 4);
1601 R600_OUT_BATCH(0xffffff);
1606 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL
, 13);
1621 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN
, 0);
1622 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN
, 0);
1623 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0
, 0);
1624 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1
, 0);
1626 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN
, 3);
1631 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN
, 0);
1632 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL
, 0);
1638 static GLboolean
validate_buffers(context_t
*rmesa
,
1639 struct radeon_bo
*src_bo
,
1640 struct radeon_bo
*dst_bo
)
1644 radeon_cs_space_reset_bos(rmesa
->radeon
.cmdbuf
.cs
);
1646 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1647 src_bo
, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
1651 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1652 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
);
1656 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1658 RADEON_GEM_DOMAIN_GTT
, 0);
1665 unsigned r600_blit(struct gl_context
*ctx
,
1666 struct radeon_bo
*src_bo
,
1667 intptr_t src_offset
,
1668 gl_format src_mesaformat
,
1671 unsigned src_height
,
1674 struct radeon_bo
*dst_bo
,
1675 intptr_t dst_offset
,
1676 gl_format dst_mesaformat
,
1679 unsigned dst_height
,
1686 context_t
*context
= R700_CONTEXT(ctx
);
1689 if (!r600_check_blit(dst_mesaformat
))
1692 if (src_bo
== dst_bo
) {
1696 if (src_offset
% 256 || dst_offset
% 256) {
1701 fprintf(stderr
, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1702 src_width
, src_height
, src_pitch
,
1703 _mesa_format_row_stride(src_mesaformat
, src_width
),
1704 _mesa_get_format_name(src_mesaformat
));
1705 fprintf(stderr
, "dst: width %d, height %d, pitch %d, format %s\n",
1706 dst_width
, dst_height
,
1707 _mesa_format_row_stride(dst_mesaformat
, dst_width
),
1708 _mesa_get_format_name(dst_mesaformat
));
1711 /* Flush is needed to make sure that source buffer has correct data */
1714 rcommonEnsureCmdBufSpace(&context
->radeon
, 311, __FUNCTION__
);
1717 load_shaders(context
->radeon
.glCtx
);
1719 if (!validate_buffers(context
, src_bo
, dst_bo
))
1722 /* set clear state */
1724 set_default_state(context
);
1728 set_shaders(context
);
1732 set_tex_resource(context
, src_mesaformat
, src_bo
,
1733 src_width
, src_height
, src_pitch
, src_offset
);
1736 set_tex_sampler(context
);
1740 set_render_target(context
, dst_bo
, dst_mesaformat
,
1741 dst_pitch
, dst_width
, dst_height
, dst_offset
);
1744 set_scissors(context
, dst_x
, dst_y
, dst_x
+ dst_width
, dst_y
+ dst_height
);
1746 set_vb_data(context
, src_x
, src_y
, dst_x
, dst_y
, w
, h
, src_height
, flip_y
);
1747 /* Vertex buffer setup */
1749 set_vtx_resource(context
);
1756 r700SyncSurf(context
, dst_bo
, 0,
1757 RADEON_GEM_DOMAIN_VRAM
|RADEON_GEM_DOMAIN_GTT
,
1758 CB_ACTION_ENA_bit
| (1 << (id
+ 6)));
1761 /* XXX drm should handle this in fence submit */
1762 r700WaitForIdleClean(context
);