src/mesa/drivers/dri/r600/r600_blit.c

   1 /*
   2  * Copyright (C) 2009 Advanced Micro Devices, Inc.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r600_context.h"
  30
  31 #include "r600_blit.h"
  32 #include "r600_cmdbuf.h"
  33
  34 static inline void
  35 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
  36 {
  37     int id = 0;
  38
  39     nPitchInPixel = rrb->pitch/rrb->cpp;
  40     SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
  41              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
  42     SETfield(cb_color0_size, ((nPitchInPixel * height) / 64) - 1,
  43              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
  44     SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
  45     SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
  46              cb_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
  47     if(4 == rrb->cpp)
  48     {
  49         SETfield(cb_color0_info, COLOR_8_8_8_8,
  50                  CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
  51         SETfield(cb_color0_info, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
  52     }
  53     else
  54     {
  55         SETfield(cb_color0_info, COLOR_5_6_5,
  56                  CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
  57         SETfield(cb_color0_info, SWAP_ALT_REV,
  58                  COMP_SWAP_shift, COMP_SWAP_mask);
  59     }
  60     SETbit(cb_color0_info, SOURCE_FORMAT_bit);
  61     SETbit(cb_color0_info, BLEND_CLAMP_bit);
  62     SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
  63
  64     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
  65     R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
  66     R600_OUT_BATCH(0);
  67     R600_OUT_BATCH_RELOC(0,
  68                          bo,
  69                          0,
  70                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
  71     END_BATCH();
  72
  73     if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
  74         (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
  75             BEGIN_BATCH_NO_AUTOSTATE(2);
  76             R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
  77             R600_OUT_BATCH((2 << id));
  78             END_BATCH();
  79     }
  80
  81     BEGIN_BATCH_NO_AUTOSTATE(18);
  82     R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
  83     R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
  84     R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
  85     R600_OUT_BATCH_REGVAL(CB_COLOR0_TILE + (4 * id), 0);
  86     R600_OUT_BATCH_REGVAL(CB_COLOR0_FRAG + (4 * id), 0);
  87     R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
  88     END_BATCH();
  89
  90     COMMIT_BATCH();
  91
  92 }
  93
  94 static inline void
  95 set_shaders(struct drm_device *dev)
  96 {
  97     /* FS */
  98     pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
  99     r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
 100     r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
 101     r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
 102     /* XXX */
 103
 104     if (!pbo)
 105             return;
 106
 107     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 108
 109     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 110     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
 111     R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
 112     R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
 113                          pbo,
 114                          r700->fs.SQ_PGM_START_FS.u32All,
 115                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 116     END_BATCH();
 117
 118     BEGIN_BATCH_NO_AUTOSTATE(6);
 119     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
 120     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
 121     END_BATCH();
 122
 123     /* VS */
 124     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 125
 126     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 127     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
 128     R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
 129     R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
 130                          pbo,
 131                          r700->vs.SQ_PGM_START_VS.u32All,
 132                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 133     END_BATCH();
 134
 135     BEGIN_BATCH_NO_AUTOSTATE(6);
 136     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
 137     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
 138     END_BATCH();
 139
 140     /* PS */
 141     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 142
 143     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 144     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
 145     R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
 146     R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
 147                          pbo,
 148                          r700->ps.SQ_PGM_START_PS.u32All,
 149                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 150     END_BATCH();
 151
 152     BEGIN_BATCH_NO_AUTOSTATE(9);
 153     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
 154     R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
 155     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
 156     END_BATCH();
 157
 158     COMMIT_BATCH();
 159
 160 }
 161
 162 static inline void
 163 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
 164 {
 165
 166     BEGIN_BATCH_NO_AUTOSTATE(6);
 167     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 168     R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
 169     R600_OUT_BATCH(0);
 170
 171     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 172     R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
 173     R600_OUT_BATCH(0);
 174     END_BATCH();
 175     COMMIT_BATCH();
 176
 177     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 178         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 179         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
 180         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
 181         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
 182             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
 183     else
 184             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
 185
 186     BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 187
 188     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 189     R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
 190     R600_OUT_BATCH(0);
 191     R600_OUT_BATCH(48 - 1);
 192     R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
 193     R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
 194     R600_OUT_BATCH(0);
 195     R600_OUT_BATCH(0);
 196     R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
 197     R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
 198                          paos->bo,
 199                          uSQ_VTX_CONSTANT_WORD0_0,
 200                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 201     END_BATCH();
 202     COMMIT_BATCH();
 203
 204 }
 205
 206 static inline void
 207 set_tex_resource(drm_radeon_private_t *dev_priv,
 208                  int format, int w, int h, int pitch, u64 gpu_addr)
 209 {
 210         uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 211         RING_LOCALS;
 212         DRM_DEBUG("\n");
 213
 214         r700SyncSurf(context, bo,
 215                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
 216                      0, TC_ACTION_ENA_bit);
 217
 218         BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
 219         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 220         R600_OUT_BATCH(i * 7);
 221
 222         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
 223         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
 224         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
 225         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
 226         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
 227         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
 228         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
 229         R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
 230                              bo,
 231                              offset,
 232                              RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 233         R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
 234                              bo,
 235                              r700->textures[i]->SQ_TEX_RESOURCE3,
 236                              RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 237         END_BATCH();
 238         COMMIT_BATCH();
 239
 240         if (h < 1)
 241                 h = 1;
 242
 243         sq_tex_resource_word0 = (1 << 0);
 244         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
 245                                   ((w - 1) << 19));
 246
 247         sq_tex_resource_word1 = (format << 26);
 248         sq_tex_resource_word1 |= ((h - 1) << 0);
 249
 250         sq_tex_resource_word4 = ((1 << 14) |
 251                                  (0 << 16) |
 252                                  (1 << 19) |
 253                                  (2 << 22) |
 254                                  (3 << 25));
 255
 256         BEGIN_RING(9);
 257         OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 258         OUT_RING(0);
 259         OUT_RING(sq_tex_resource_word0);
 260         OUT_RING(sq_tex_resource_word1);
 261         OUT_RING(gpu_addr >> 8);
 262         OUT_RING(gpu_addr >> 8);
 263         OUT_RING(sq_tex_resource_word4);
 264         OUT_RING(0);
 265         OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
 266         ADVANCE_RING();
 267
 268 }
 269
 270 static inline void
 271 set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
 272 {
 273         RING_LOCALS;
 274         DRM_DEBUG("\n");
 275
 276         BEGIN_BATCH_NO_AUTOSTATE(22);
 277         R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
 278         R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
 279         R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
 280
 281         R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
 282         R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
 283         R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
 284         R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
 285         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
 286         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
 287         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
 288         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
 289         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
 290         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
 291         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
 292         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
 293         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
 294
 295         R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
 296         R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
 297         R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
 298         END_BATCH();
 299         COMMIT_BATCH();
 300
 301
 302         BEGIN_RING(12);
 303         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
 304         OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 305         OUT_RING((x1 << 0) | (y1 << 16));
 306         OUT_RING((x2 << 0) | (y2 << 16));
 307
 308         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
 309         OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 310         OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
 311         OUT_RING((x2 << 0) | (y2 << 16));
 312
 313         OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
 314         OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
 315         OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
 316         OUT_RING((x2 << 0) | (y2 << 16));
 317         ADVANCE_RING();
 318 }
 319
 320 static inline void
 321 draw_auto(drm_radeon_private_t *dev_priv)
 322 {
 323         RING_LOCALS;
 324         DRM_DEBUG("\n");
 325
 326         BEGIN_RING(10);
 327         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
 328         OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
 329         OUT_RING(DI_PT_RECTLIST);
 330
 331         OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
 332         OUT_RING(DI_INDEX_SIZE_16_BIT);
 333
 334         OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
 335         OUT_RING(1);
 336
 337         OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
 338         OUT_RING(3);
 339         OUT_RING(DI_SRC_SEL_AUTO_INDEX);
 340
 341         ADVANCE_RING();
 342         COMMIT_RING();
 343 }
 344
 345 static inline void
 346 set_default_state(drm_radeon_private_t *dev_priv)
 347 {
 348         int i;
 349         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 350         u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 351         int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
 352         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 353         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 354         RING_LOCALS;
 355
 356         switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
 357         case CHIP_R600:
 358                 num_ps_gprs = 192;
 359                 num_vs_gprs = 56;
 360                 num_temp_gprs = 4;
 361                 num_gs_gprs = 0;
 362                 num_es_gprs = 0;
 363                 num_ps_threads = 136;
 364                 num_vs_threads = 48;
 365                 num_gs_threads = 4;
 366                 num_es_threads = 4;
 367                 num_ps_stack_entries = 128;
 368                 num_vs_stack_entries = 128;
 369                 num_gs_stack_entries = 0;
 370                 num_es_stack_entries = 0;
 371                 break;
 372         case CHIP_RV630:
 373         case CHIP_RV635:
 374                 num_ps_gprs = 84;
 375                 num_vs_gprs = 36;
 376                 num_temp_gprs = 4;
 377                 num_gs_gprs = 0;
 378                 num_es_gprs = 0;
 379                 num_ps_threads = 144;
 380                 num_vs_threads = 40;
 381                 num_gs_threads = 4;
 382                 num_es_threads = 4;
 383                 num_ps_stack_entries = 40;
 384                 num_vs_stack_entries = 40;
 385                 num_gs_stack_entries = 32;
 386                 num_es_stack_entries = 16;
 387                 break;
 388         case CHIP_RV610:
 389         case CHIP_RV620:
 390         case CHIP_RS780:
 391         case CHIP_RS880:
 392         default:
 393                 num_ps_gprs = 84;
 394                 num_vs_gprs = 36;
 395                 num_temp_gprs = 4;
 396                 num_gs_gprs = 0;
 397                 num_es_gprs = 0;
 398                 num_ps_threads = 136;
 399                 num_vs_threads = 48;
 400                 num_gs_threads = 4;
 401                 num_es_threads = 4;
 402                 num_ps_stack_entries = 40;
 403                 num_vs_stack_entries = 40;
 404                 num_gs_stack_entries = 32;
 405                 num_es_stack_entries = 16;
 406                 break;
 407         case CHIP_RV670:
 408                 num_ps_gprs = 144;
 409                 num_vs_gprs = 40;
 410                 num_temp_gprs = 4;
 411                 num_gs_gprs = 0;
 412                 num_es_gprs = 0;
 413                 num_ps_threads = 136;
 414                 num_vs_threads = 48;
 415                 num_gs_threads = 4;
 416                 num_es_threads = 4;
 417                 num_ps_stack_entries = 40;
 418                 num_vs_stack_entries = 40;
 419                 num_gs_stack_entries = 32;
 420                 num_es_stack_entries = 16;
 421                 break;
 422         case CHIP_RV770:
 423                 num_ps_gprs = 192;
 424                 num_vs_gprs = 56;
 425                 num_temp_gprs = 4;
 426                 num_gs_gprs = 0;
 427                 num_es_gprs = 0;
 428                 num_ps_threads = 188;
 429                 num_vs_threads = 60;
 430                 num_gs_threads = 0;
 431                 num_es_threads = 0;
 432                 num_ps_stack_entries = 256;
 433                 num_vs_stack_entries = 256;
 434                 num_gs_stack_entries = 0;
 435                 num_es_stack_entries = 0;
 436                 break;
 437         case CHIP_RV730:
 438         case CHIP_RV740:
 439                 num_ps_gprs = 84;
 440                 num_vs_gprs = 36;
 441                 num_temp_gprs = 4;
 442                 num_gs_gprs = 0;
 443                 num_es_gprs = 0;
 444                 num_ps_threads = 188;
 445                 num_vs_threads = 60;
 446                 num_gs_threads = 0;
 447                 num_es_threads = 0;
 448                 num_ps_stack_entries = 128;
 449                 num_vs_stack_entries = 128;
 450                 num_gs_stack_entries = 0;
 451                 num_es_stack_entries = 0;
 452                 break;
 453         case CHIP_RV710:
 454                 num_ps_gprs = 192;
 455                 num_vs_gprs = 56;
 456                 num_temp_gprs = 4;
 457                 num_gs_gprs = 0;
 458                 num_es_gprs = 0;
 459                 num_ps_threads = 144;
 460                 num_vs_threads = 48;
 461                 num_gs_threads = 0;
 462                 num_es_threads = 0;
 463                 num_ps_stack_entries = 128;
 464                 num_vs_stack_entries = 128;
 465                 num_gs_stack_entries = 0;
 466                 num_es_stack_entries = 0;
 467                 break;
 468         }
 469
 470         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 471             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 472             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 473             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
 474             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
 475                 sq_config = 0;
 476         else
 477                 sq_config = R600_VC_ENABLE;
 478
 479         sq_config |= (R600_DX9_CONSTS |
 480                       R600_ALU_INST_PREFER_VECTOR |
 481                       R600_PS_PRIO(0) |
 482                       R600_VS_PRIO(1) |
 483                       R600_GS_PRIO(2) |
 484                       R600_ES_PRIO(3));
 485
 486         sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
 487                                   R600_NUM_VS_GPRS(num_vs_gprs) |
 488                                   R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 489         sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
 490                                   R600_NUM_ES_GPRS(num_es_gprs));
 491         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
 492                                    R600_NUM_VS_THREADS(num_vs_threads) |
 493                                    R600_NUM_GS_THREADS(num_gs_threads) |
 494                                    R600_NUM_ES_THREADS(num_es_threads));
 495         sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 496                                     R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 497         sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 498                                     R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 499
 500         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 501                 BEGIN_RING(r7xx_default_size + 10);
 502                 for (i = 0; i < r7xx_default_size; i++)
 503                         OUT_RING(r7xx_default_state[i]);
 504         } else {
 505                 BEGIN_RING(r6xx_default_size + 10);
 506                 for (i = 0; i < r6xx_default_size; i++)
 507                         OUT_RING(r6xx_default_state[i]);
 508         }
 509         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
 510         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
 511         /* SQ config */
 512         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
 513         OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
 514         OUT_RING(sq_config);
 515         OUT_RING(sq_gpr_resource_mgmt_1);
 516         OUT_RING(sq_gpr_resource_mgmt_2);
 517         OUT_RING(sq_thread_resource_mgmt);
 518         OUT_RING(sq_stack_resource_mgmt_1);
 519         OUT_RING(sq_stack_resource_mgmt_2);
 520         ADVANCE_RING();
 521 }
 522
 523 static GLboolean validate_buffers(struct r300_context *r300,
 524                                   struct radeon_bo *src_bo,
 525                                   struct radeon_bo *dst_bo)
 526 {
 527     int ret;
 528     radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
 529                                       src_bo, RADEON_GEM_DOMAIN_VRAM, 0);
 530
 531     radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs,
 532                                       dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
 533
 534     ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
 535                                         first_elem(&r300->radeon.dma.reserved)->bo,
 536                                         RADEON_GEM_DOMAIN_GTT, 0);
 537     if (ret)
 538         return GL_FALSE;
 539
 540     return GL_TRUE;
 541 }
 542
 543 GLboolean r600_blit(struct r300_context *r300,
 544                     struct radeon_bo *src_bo,
 545                     intptr_t src_offset,
 546                     gl_format src_mesaformat,
 547                     unsigned src_pitch,
 548                     unsigned src_width,
 549                     unsigned src_height,
 550                     struct radeon_bo *dst_bo,
 551                     intptr_t dst_offset,
 552                     gl_format dst_mesaformat,
 553                     unsigned dst_pitch,
 554                     unsigned dst_width,
 555                     unsigned dst_height)
 556 {
 557     int id = 0;
 558
 559     if (src_bo == dst_bo) {
 560         return GL_FALSE;
 561     }
 562
 563     if (0) {
 564         fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
 565                 src_width, src_height, src_pitch,
 566                 _mesa_format_row_stride(src_mesaformat, src_width),
 567                 _mesa_get_format_name(src_mesaformat));
 568         fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
 569                 dst_width, dst_height,
 570                 _mesa_format_row_stride(dst_mesaformat, dst_width),
 571                 _mesa_get_format_name(dst_mesaformat));
 572     }
 573
 574     if (!validate_buffers(r300, src_bo, dst_bo))
 575         return GL_FALSE;
 576
 577     rcommonEnsureCmdBufSpace(&r300->radeon, 200, __FUNCTION__);
 578
 579     /* src */
 580     set_tex_resource(dev_priv, tex_format,
 581                      src_pitch / cpp,
 582                      sy2, src_pitch / cpp,
 583                      src_gpu_addr);
 584
 585     r700SyncSurf(context, src_bo,
 586                  RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
 587                  0, TC_ACTION_ENA_bit);
 588
 589     /* dst */
 590     set_render_target(dev_priv, cb_format,
 591                       dst_pitch / cpp, dy2,
 592                       dst_gpu_addr);
 593
 594     /* scissors */
 595     set_scissors(dev_priv, 0, 0, width, height);
 596
 597     /* Vertex buffer setup */
 598     set_vtx_resource(dev_priv, vb_addr);
 599
 600     /* draw */
 601     draw_auto(dev_priv);
 602
 603     r700SyncSurf(context, dst_bo, 0, RADEON_GEM_DOMAIN_VRAM,
 604                  CB_ACTION_ENA_bit | (1 << (id + 6)));
 605
 606     radeonFlush(r300->radeon.glCtx);
 607
 608     return GL_TRUE;
 609 }