2 * Copyright (C) 2009 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "r600_context.h"
31 #include "r600_blit.h"
32 #include "r600_blit_shaders.h"
33 #include "r600_cmdbuf.h"
35 /* common formats supported as both textures and render targets */
36 unsigned r600_check_blit(gl_format mesa_format
)
38 switch (mesa_format
) {
39 case MESA_FORMAT_RGBA8888
:
40 case MESA_FORMAT_SIGNED_RGBA8888
:
41 case MESA_FORMAT_RGBA8888_REV
:
42 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
43 case MESA_FORMAT_ARGB8888
:
44 case MESA_FORMAT_XRGB8888
:
45 case MESA_FORMAT_ARGB8888_REV
:
46 case MESA_FORMAT_XRGB8888_REV
:
47 case MESA_FORMAT_RGB565
:
48 case MESA_FORMAT_RGB565_REV
:
49 case MESA_FORMAT_ARGB4444
:
50 case MESA_FORMAT_ARGB4444_REV
:
51 case MESA_FORMAT_ARGB1555
:
52 case MESA_FORMAT_ARGB1555_REV
:
53 case MESA_FORMAT_AL88
:
54 case MESA_FORMAT_AL88_REV
:
55 case MESA_FORMAT_RGB332
:
60 case MESA_FORMAT_RGBA_FLOAT32
:
61 case MESA_FORMAT_RGBA_FLOAT16
:
62 case MESA_FORMAT_ALPHA_FLOAT32
:
63 case MESA_FORMAT_ALPHA_FLOAT16
:
64 case MESA_FORMAT_LUMINANCE_FLOAT32
:
65 case MESA_FORMAT_LUMINANCE_FLOAT16
:
66 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
67 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
68 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
69 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
70 case MESA_FORMAT_X8_Z24
:
71 case MESA_FORMAT_S8_Z24
:
72 case MESA_FORMAT_Z24_S8
:
75 case MESA_FORMAT_SRGBA8
:
76 case MESA_FORMAT_SLA8
:
84 /* not sure blit to depth works or not yet */
85 if (_mesa_get_format_bits(mesa_format
, GL_DEPTH_BITS
) > 0)
92 set_render_target(context_t
*context
, struct radeon_bo
*bo
, gl_format mesa_format
,
93 int nPitchInPixel
, int w
, int h
, intptr_t dst_offset
)
95 uint32_t cb_color0_base
, cb_color0_size
= 0, cb_color0_info
= 0, cb_color0_view
= 0;
97 uint32_t comp_swap
, format
;
98 BATCH_LOCALS(&context
->radeon
);
100 cb_color0_base
= dst_offset
/ 256;
102 SETfield(cb_color0_size
, (nPitchInPixel
/ 8) - 1,
103 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
104 SETfield(cb_color0_size
, ((nPitchInPixel
* h
) / 64) - 1,
105 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
);
107 SETfield(cb_color0_info
, ENDIAN_NONE
, ENDIAN_shift
, ENDIAN_mask
);
108 SETfield(cb_color0_info
, ARRAY_LINEAR_GENERAL
,
109 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
111 SETbit(cb_color0_info
, BLEND_BYPASS_bit
);
113 switch(mesa_format
) {
114 case MESA_FORMAT_RGBA8888
:
115 format
= COLOR_8_8_8_8
;
116 comp_swap
= SWAP_STD_REV
;
117 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
118 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
120 case MESA_FORMAT_SIGNED_RGBA8888
:
121 format
= COLOR_8_8_8_8
;
122 comp_swap
= SWAP_STD_REV
;
123 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
124 SETfield(cb_color0_info
, NUMBER_SNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
126 case MESA_FORMAT_RGBA8888_REV
:
127 format
= COLOR_8_8_8_8
;
128 comp_swap
= SWAP_STD
;
129 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
130 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
132 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
133 format
= COLOR_8_8_8_8
;
134 comp_swap
= SWAP_STD
;
135 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
136 SETfield(cb_color0_info
, NUMBER_SNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
138 case MESA_FORMAT_ARGB8888
:
139 case MESA_FORMAT_XRGB8888
:
140 format
= COLOR_8_8_8_8
;
141 comp_swap
= SWAP_ALT
;
142 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
143 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
145 case MESA_FORMAT_ARGB8888_REV
:
146 case MESA_FORMAT_XRGB8888_REV
:
147 format
= COLOR_8_8_8_8
;
148 comp_swap
= SWAP_ALT_REV
;
149 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
150 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
152 case MESA_FORMAT_RGB565
:
153 format
= COLOR_5_6_5
;
154 comp_swap
= SWAP_STD_REV
;
155 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
156 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
158 case MESA_FORMAT_RGB565_REV
:
159 format
= COLOR_5_6_5
;
160 comp_swap
= SWAP_STD
;
161 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
162 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
164 case MESA_FORMAT_ARGB4444
:
165 format
= COLOR_4_4_4_4
;
166 comp_swap
= SWAP_ALT
;
167 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
168 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
170 case MESA_FORMAT_ARGB4444_REV
:
171 format
= COLOR_4_4_4_4
;
172 comp_swap
= SWAP_ALT_REV
;
173 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
174 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
176 case MESA_FORMAT_ARGB1555
:
177 format
= COLOR_1_5_5_5
;
178 comp_swap
= SWAP_ALT
;
179 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
180 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
182 case MESA_FORMAT_ARGB1555_REV
:
183 format
= COLOR_1_5_5_5
;
184 comp_swap
= SWAP_ALT_REV
;
185 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
186 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
188 case MESA_FORMAT_AL88
:
190 comp_swap
= SWAP_STD
;
191 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
192 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
194 case MESA_FORMAT_AL88_REV
:
196 comp_swap
= SWAP_STD_REV
;
197 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
198 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
200 case MESA_FORMAT_RGB332
:
201 format
= COLOR_3_3_2
;
202 comp_swap
= SWAP_STD_REV
;
203 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
204 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
208 comp_swap
= SWAP_ALT_REV
;
209 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
210 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
213 case MESA_FORMAT_CI8
:
215 comp_swap
= SWAP_STD
;
216 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
217 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
221 comp_swap
= SWAP_ALT
;
222 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
223 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
225 case MESA_FORMAT_RGBA_FLOAT32
:
226 format
= COLOR_32_32_32_32_FLOAT
;
227 comp_swap
= SWAP_STD_REV
;
228 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
229 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
230 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
232 case MESA_FORMAT_RGBA_FLOAT16
:
233 format
= COLOR_16_16_16_16_FLOAT
;
234 comp_swap
= SWAP_STD_REV
;
235 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
236 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
238 case MESA_FORMAT_ALPHA_FLOAT32
:
239 format
= COLOR_32_FLOAT
;
240 comp_swap
= SWAP_ALT_REV
;
241 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
242 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
243 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
245 case MESA_FORMAT_ALPHA_FLOAT16
:
246 format
= COLOR_16_FLOAT
;
247 comp_swap
= SWAP_ALT_REV
;
248 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
249 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
251 case MESA_FORMAT_LUMINANCE_FLOAT32
:
252 format
= COLOR_32_FLOAT
;
253 comp_swap
= SWAP_ALT
;
254 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
255 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
256 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
258 case MESA_FORMAT_LUMINANCE_FLOAT16
:
259 format
= COLOR_16_FLOAT
;
260 comp_swap
= SWAP_ALT
;
261 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
262 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
264 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
265 format
= COLOR_32_32_FLOAT
;
266 comp_swap
= SWAP_ALT_REV
;
267 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
268 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
269 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
271 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
272 format
= COLOR_16_16_FLOAT
;
273 comp_swap
= SWAP_ALT_REV
;
274 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
275 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
277 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
278 format
= COLOR_32_FLOAT
;
279 comp_swap
= SWAP_STD
;
280 SETbit(cb_color0_info
, BLEND_FLOAT32_bit
);
281 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
282 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
284 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
285 format
= COLOR_16_FLOAT
;
286 comp_swap
= SWAP_STD
;
287 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
288 SETfield(cb_color0_info
, NUMBER_FLOAT
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
290 case MESA_FORMAT_X8_Z24
:
291 case MESA_FORMAT_S8_Z24
:
293 comp_swap
= SWAP_STD
;
294 SETfield(cb_color0_info
, ARRAY_1D_TILED_THIN1
,
295 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
296 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
297 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
299 case MESA_FORMAT_Z24_S8
:
301 comp_swap
= SWAP_STD
;
302 SETfield(cb_color0_info
, ARRAY_1D_TILED_THIN1
,
303 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
304 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
305 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
307 case MESA_FORMAT_Z16
:
309 comp_swap
= SWAP_STD
;
310 SETfield(cb_color0_info
, ARRAY_1D_TILED_THIN1
,
311 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
312 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
313 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
315 case MESA_FORMAT_Z32
:
317 comp_swap
= SWAP_STD
;
318 SETfield(cb_color0_info
, ARRAY_1D_TILED_THIN1
,
319 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
320 CLEARbit(cb_color0_info
, SOURCE_FORMAT_bit
);
321 SETfield(cb_color0_info
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
323 case MESA_FORMAT_SRGBA8
:
324 format
= COLOR_8_8_8_8
;
325 comp_swap
= SWAP_STD_REV
;
326 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
327 SETfield(cb_color0_info
, NUMBER_SRGB
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
329 case MESA_FORMAT_SLA8
:
331 comp_swap
= SWAP_ALT_REV
;
332 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
333 SETfield(cb_color0_info
, NUMBER_SRGB
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
335 case MESA_FORMAT_SL8
:
337 comp_swap
= SWAP_ALT_REV
;
338 SETbit(cb_color0_info
, SOURCE_FORMAT_bit
);
339 SETfield(cb_color0_info
, NUMBER_SRGB
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
342 fprintf(stderr
,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format
));
343 assert("Invalid format for US output\n");
347 SETfield(cb_color0_info
, format
, CB_COLOR0_INFO__FORMAT_shift
,
348 CB_COLOR0_INFO__FORMAT_mask
);
349 SETfield(cb_color0_info
, comp_swap
, COMP_SWAP_shift
, COMP_SWAP_mask
);
351 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
352 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE
+ (4 * id
), 1);
353 R600_OUT_BATCH(cb_color0_base
);
354 R600_OUT_BATCH_RELOC(0,
357 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
360 if ((context
->radeon
.radeonScreen
->chip_family
> CHIP_FAMILY_R600
) &&
361 (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)) {
362 BEGIN_BATCH_NO_AUTOSTATE(2);
363 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE
, 0));
364 R600_OUT_BATCH((2 << id
));
368 /* Set CMASK & TILE buffer to the offset of color buffer as
369 * we don't use those this shouldn't cause any issue and we
370 * then have a valid cmd stream
372 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
373 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE
+ (4 * id
), 1);
374 R600_OUT_BATCH(cb_color0_base
);
375 R600_OUT_BATCH_RELOC(0,
378 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
380 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
381 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG
+ (4 * id
), 1);
382 R600_OUT_BATCH(cb_color0_base
);
383 R600_OUT_BATCH_RELOC(0,
386 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
389 BEGIN_BATCH_NO_AUTOSTATE(12);
390 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE
+ (4 * id
), cb_color0_size
);
391 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW
+ (4 * id
), cb_color0_view
);
392 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO
+ (4 * id
), cb_color0_info
);
393 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK
+ (4 * id
), 0);
400 static inline void load_shaders(GLcontext
* ctx
)
403 radeonContextPtr radeonctx
= RADEON_CONTEXT(ctx
);
404 context_t
*context
= R700_CONTEXT(ctx
);
408 if (context
->blit_bo_loaded
== 1)
412 context
->blit_bo
= radeon_bo_open(radeonctx
->radeonScreen
->bom
, 0,
413 size
, 256, RADEON_GEM_DOMAIN_GTT
, 0);
414 radeon_bo_map(context
->blit_bo
, 1);
415 shader
= context
->blit_bo
->ptr
;
417 for(i
=0; i
<sizeof(r6xx_vs
)/4; i
++) {
418 shader
[128+i
] = r6xx_vs
[i
];
420 for(i
=0; i
<sizeof(r6xx_ps
)/4; i
++) {
421 shader
[256+i
] = r6xx_ps
[i
];
424 radeon_bo_unmap(context
->blit_bo
);
425 context
->blit_bo_loaded
= 1;
430 set_shaders(context_t
*context
)
432 struct radeon_bo
* pbo
= context
->blit_bo
;
433 BATCH_LOCALS(&context
->radeon
);
435 uint32_t sq_pgm_start_fs
= (512 >> 8);
436 uint32_t sq_pgm_resources_fs
= 0;
437 uint32_t sq_pgm_cf_offset_fs
= 0;
439 uint32_t sq_pgm_start_vs
= (512 >> 8);
440 uint32_t sq_pgm_resources_vs
= (1 << NUM_GPRS_shift
);
441 uint32_t sq_pgm_cf_offset_vs
= 0;
443 uint32_t sq_pgm_start_ps
= (1024 >> 8);
444 uint32_t sq_pgm_resources_ps
= (1 << NUM_GPRS_shift
);
445 uint32_t sq_pgm_cf_offset_ps
= 0;
446 uint32_t sq_pgm_exports_ps
= (1 << 1);
448 r700SyncSurf(context
, pbo
, RADEON_GEM_DOMAIN_GTT
, 0, SH_ACTION_ENA_bit
);
451 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
452 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS
, 1);
453 R600_OUT_BATCH(sq_pgm_start_fs
);
454 R600_OUT_BATCH_RELOC(sq_pgm_start_fs
,
457 RADEON_GEM_DOMAIN_GTT
, 0, 0);
460 BEGIN_BATCH_NO_AUTOSTATE(6);
461 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS
, sq_pgm_resources_fs
);
462 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS
, sq_pgm_cf_offset_fs
);
466 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
467 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS
, 1);
468 R600_OUT_BATCH(sq_pgm_start_vs
);
469 R600_OUT_BATCH_RELOC(sq_pgm_start_vs
,
472 RADEON_GEM_DOMAIN_GTT
, 0, 0);
475 BEGIN_BATCH_NO_AUTOSTATE(6);
476 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS
, sq_pgm_resources_vs
);
477 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS
, sq_pgm_cf_offset_vs
);
481 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
482 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS
, 1);
483 R600_OUT_BATCH(sq_pgm_start_ps
);
484 R600_OUT_BATCH_RELOC(sq_pgm_start_ps
,
487 RADEON_GEM_DOMAIN_GTT
, 0, 0);
490 BEGIN_BATCH_NO_AUTOSTATE(9);
491 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS
, sq_pgm_resources_ps
);
492 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS
, sq_pgm_exports_ps
);
493 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS
, sq_pgm_cf_offset_ps
);
496 BEGIN_BATCH_NO_AUTOSTATE(18);
497 R600_OUT_BATCH_REGVAL(SPI_VS_OUT_CONFIG
, 0); //EXPORT_COUNT is - 1
498 R600_OUT_BATCH_REGVAL(SPI_VS_OUT_ID_0
, 0);
499 R600_OUT_BATCH_REGVAL(SPI_PS_INPUT_CNTL_0
, SEL_CENTROID_bit
);
500 R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_0
, (1 << NUM_INTERP_shift
));
501 R600_OUT_BATCH_REGVAL(SPI_PS_IN_CONTROL_1
, 0);
502 R600_OUT_BATCH_REGVAL(SPI_INTERP_CONTROL_0
, 0);
510 set_vtx_resource(context_t
*context
)
512 struct radeon_bo
*bo
= context
->blit_bo
;
513 BATCH_LOCALS(&context
->radeon
);
515 BEGIN_BATCH_NO_AUTOSTATE(6);
516 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 1));
517 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
520 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 1));
521 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
526 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
527 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
528 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
529 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
530 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
531 r700SyncSurf(context
, bo
, RADEON_GEM_DOMAIN_GTT
, 0, TC_ACTION_ENA_bit
);
533 r700SyncSurf(context
, bo
, RADEON_GEM_DOMAIN_GTT
, 0, VC_ACTION_ENA_bit
);
535 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
537 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE
, 7));
538 R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET
* FETCH_RESOURCE_STRIDE
);
540 R600_OUT_BATCH(48 - 1);
541 R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift
);
542 R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift
);
545 R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER
<< SQ_TEX_RESOURCE_WORD6_0__TYPE_shift
);
546 R600_OUT_BATCH_RELOC(SQ_VTX_CONSTANT_WORD0_0
,
548 SQ_VTX_CONSTANT_WORD0_0
,
549 RADEON_GEM_DOMAIN_GTT
, 0, 0);
556 set_tex_resource(context_t
* context
,
557 gl_format mesa_format
, struct radeon_bo
*bo
, int w
, int h
,
558 int TexelPitch
, intptr_t src_offset
)
560 uint32_t sq_tex_resource0
, sq_tex_resource1
, sq_tex_resource2
, sq_tex_resource4
, sq_tex_resource6
;
562 sq_tex_resource0
= sq_tex_resource1
= sq_tex_resource2
= sq_tex_resource4
= sq_tex_resource6
= 0;
563 BATCH_LOCALS(&context
->radeon
);
565 SETfield(sq_tex_resource0
, SQ_TEX_DIM_2D
, DIM_shift
, DIM_mask
);
566 SETfield(sq_tex_resource0
, ARRAY_LINEAR_GENERAL
,
567 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
568 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
570 switch (mesa_format
) {
571 case MESA_FORMAT_RGBA8888
:
572 case MESA_FORMAT_SIGNED_RGBA8888
:
573 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
574 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
576 SETfield(sq_tex_resource4
, SQ_SEL_W
,
577 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
578 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
579 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
580 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
581 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
582 SETfield(sq_tex_resource4
, SQ_SEL_X
,
583 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
584 if (mesa_format
== MESA_FORMAT_SIGNED_RGBA8888
) {
585 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
586 FORMAT_COMP_X_shift
, FORMAT_COMP_X_mask
);
587 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
588 FORMAT_COMP_Y_shift
, FORMAT_COMP_Y_mask
);
589 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
590 FORMAT_COMP_Z_shift
, FORMAT_COMP_Z_mask
);
591 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
592 FORMAT_COMP_W_shift
, FORMAT_COMP_W_mask
);
595 case MESA_FORMAT_RGBA8888_REV
:
596 case MESA_FORMAT_SIGNED_RGBA8888_REV
:
597 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
598 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
600 SETfield(sq_tex_resource4
, SQ_SEL_X
,
601 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
602 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
603 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
604 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
605 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
606 SETfield(sq_tex_resource4
, SQ_SEL_W
,
607 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
608 if (mesa_format
== MESA_FORMAT_SIGNED_RGBA8888_REV
) {
609 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
610 FORMAT_COMP_X_shift
, FORMAT_COMP_X_mask
);
611 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
612 FORMAT_COMP_Y_shift
, FORMAT_COMP_Y_mask
);
613 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
614 FORMAT_COMP_Z_shift
, FORMAT_COMP_Z_mask
);
615 SETfield(sq_tex_resource4
, SQ_FORMAT_COMP_SIGNED
,
616 FORMAT_COMP_W_shift
, FORMAT_COMP_W_mask
);
619 case MESA_FORMAT_ARGB8888
:
620 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
621 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
623 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
624 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
625 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
626 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
627 SETfield(sq_tex_resource4
, SQ_SEL_X
,
628 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
629 SETfield(sq_tex_resource4
, SQ_SEL_W
,
630 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
632 case MESA_FORMAT_XRGB8888
:
633 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
634 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
636 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
637 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
638 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
639 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
640 SETfield(sq_tex_resource4
, SQ_SEL_X
,
641 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
642 SETfield(sq_tex_resource4
, SQ_SEL_1
,
643 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
645 case MESA_FORMAT_ARGB8888_REV
:
646 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
647 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
649 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
650 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
651 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
652 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
653 SETfield(sq_tex_resource4
, SQ_SEL_W
,
654 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
655 SETfield(sq_tex_resource4
, SQ_SEL_X
,
656 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
658 case MESA_FORMAT_XRGB8888_REV
:
659 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
660 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
662 SETfield(sq_tex_resource4
, SQ_SEL_1
,
663 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
664 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
665 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
666 SETfield(sq_tex_resource4
, SQ_SEL_W
,
667 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
668 SETfield(sq_tex_resource4
, SQ_SEL_X
,
669 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
671 case MESA_FORMAT_RGB565
:
672 SETfield(sq_tex_resource1
, FMT_5_6_5
,
673 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
675 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
676 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
677 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
678 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
679 SETfield(sq_tex_resource4
, SQ_SEL_X
,
680 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
681 SETfield(sq_tex_resource4
, SQ_SEL_1
,
682 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
684 case MESA_FORMAT_RGB565_REV
:
685 SETfield(sq_tex_resource1
, FMT_5_6_5
,
686 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
688 SETfield(sq_tex_resource4
, SQ_SEL_X
,
689 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
690 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
691 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
692 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
693 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
694 SETfield(sq_tex_resource4
, SQ_SEL_1
,
695 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
697 case MESA_FORMAT_ARGB4444
:
698 SETfield(sq_tex_resource1
, FMT_4_4_4_4
,
699 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
701 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
702 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
703 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
704 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
705 SETfield(sq_tex_resource4
, SQ_SEL_X
,
706 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
707 SETfield(sq_tex_resource4
, SQ_SEL_W
,
708 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
710 case MESA_FORMAT_ARGB4444_REV
:
711 SETfield(sq_tex_resource1
, FMT_4_4_4_4
,
712 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
714 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
715 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
716 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
717 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
718 SETfield(sq_tex_resource4
, SQ_SEL_W
,
719 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
720 SETfield(sq_tex_resource4
, SQ_SEL_X
,
721 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
723 case MESA_FORMAT_ARGB1555
:
724 SETfield(sq_tex_resource1
, FMT_1_5_5_5
,
725 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
727 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
728 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
729 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
730 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
731 SETfield(sq_tex_resource4
, SQ_SEL_X
,
732 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
733 SETfield(sq_tex_resource4
, SQ_SEL_W
,
734 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
736 case MESA_FORMAT_ARGB1555_REV
:
737 SETfield(sq_tex_resource1
, FMT_1_5_5_5
,
738 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
740 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
741 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
742 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
743 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
744 SETfield(sq_tex_resource4
, SQ_SEL_W
,
745 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
746 SETfield(sq_tex_resource4
, SQ_SEL_X
,
747 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
749 case MESA_FORMAT_AL88
:
750 case MESA_FORMAT_AL88_REV
: /* TODO : Check this. */
751 SETfield(sq_tex_resource1
, FMT_8_8
,
752 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
754 SETfield(sq_tex_resource4
, SQ_SEL_X
,
755 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
756 SETfield(sq_tex_resource4
, SQ_SEL_X
,
757 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
758 SETfield(sq_tex_resource4
, SQ_SEL_X
,
759 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
760 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
761 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
763 case MESA_FORMAT_RGB332
:
764 SETfield(sq_tex_resource1
, FMT_3_3_2
,
765 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
767 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
768 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
769 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
770 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
771 SETfield(sq_tex_resource4
, SQ_SEL_X
,
772 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
773 SETfield(sq_tex_resource4
, SQ_SEL_1
,
774 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
776 case MESA_FORMAT_A8
: /* ZERO, ZERO, ZERO, X */
777 SETfield(sq_tex_resource1
, FMT_8
,
778 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
780 SETfield(sq_tex_resource4
, SQ_SEL_0
,
781 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
782 SETfield(sq_tex_resource4
, SQ_SEL_0
,
783 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
784 SETfield(sq_tex_resource4
, SQ_SEL_0
,
785 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
786 SETfield(sq_tex_resource4
, SQ_SEL_X
,
787 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
789 case MESA_FORMAT_L8
: /* X, X, X, ONE */
790 SETfield(sq_tex_resource1
, FMT_8
,
791 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
793 SETfield(sq_tex_resource4
, SQ_SEL_X
,
794 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
795 SETfield(sq_tex_resource4
, SQ_SEL_X
,
796 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
797 SETfield(sq_tex_resource4
, SQ_SEL_X
,
798 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
799 SETfield(sq_tex_resource4
, SQ_SEL_1
,
800 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
802 case MESA_FORMAT_I8
: /* X, X, X, X */
803 case MESA_FORMAT_CI8
:
804 SETfield(sq_tex_resource1
, FMT_8
,
805 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
807 SETfield(sq_tex_resource4
, SQ_SEL_X
,
808 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
809 SETfield(sq_tex_resource4
, SQ_SEL_X
,
810 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
811 SETfield(sq_tex_resource4
, SQ_SEL_X
,
812 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
813 SETfield(sq_tex_resource4
, SQ_SEL_X
,
814 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
816 case MESA_FORMAT_RGBA_FLOAT32
:
817 SETfield(sq_tex_resource1
, FMT_32_32_32_32_FLOAT
,
818 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
820 SETfield(sq_tex_resource4
, SQ_SEL_X
,
821 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
822 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
823 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
824 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
825 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
826 SETfield(sq_tex_resource4
, SQ_SEL_W
,
827 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
829 case MESA_FORMAT_RGBA_FLOAT16
:
830 SETfield(sq_tex_resource1
, FMT_16_16_16_16_FLOAT
,
831 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
833 SETfield(sq_tex_resource4
, SQ_SEL_X
,
834 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
835 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
836 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
837 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
838 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
839 SETfield(sq_tex_resource4
, SQ_SEL_W
,
840 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
842 case MESA_FORMAT_ALPHA_FLOAT32
: /* ZERO, ZERO, ZERO, X */
843 SETfield(sq_tex_resource1
, FMT_32_FLOAT
,
844 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
846 SETfield(sq_tex_resource4
, SQ_SEL_0
,
847 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
848 SETfield(sq_tex_resource4
, SQ_SEL_0
,
849 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
850 SETfield(sq_tex_resource4
, SQ_SEL_0
,
851 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
852 SETfield(sq_tex_resource4
, SQ_SEL_X
,
853 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
855 case MESA_FORMAT_ALPHA_FLOAT16
: /* ZERO, ZERO, ZERO, X */
856 SETfield(sq_tex_resource1
, FMT_16_FLOAT
,
857 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
859 SETfield(sq_tex_resource4
, SQ_SEL_0
,
860 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
861 SETfield(sq_tex_resource4
, SQ_SEL_0
,
862 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
863 SETfield(sq_tex_resource4
, SQ_SEL_0
,
864 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
865 SETfield(sq_tex_resource4
, SQ_SEL_X
,
866 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
868 case MESA_FORMAT_LUMINANCE_FLOAT32
: /* X, X, X, ONE */
869 SETfield(sq_tex_resource1
, FMT_32_FLOAT
,
870 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
872 SETfield(sq_tex_resource4
, SQ_SEL_X
,
873 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
874 SETfield(sq_tex_resource4
, SQ_SEL_X
,
875 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
876 SETfield(sq_tex_resource4
, SQ_SEL_X
,
877 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
878 SETfield(sq_tex_resource4
, SQ_SEL_1
,
879 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
881 case MESA_FORMAT_LUMINANCE_FLOAT16
: /* X, X, X, ONE */
882 SETfield(sq_tex_resource1
, FMT_16_FLOAT
,
883 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
885 SETfield(sq_tex_resource4
, SQ_SEL_X
,
886 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
887 SETfield(sq_tex_resource4
, SQ_SEL_X
,
888 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
889 SETfield(sq_tex_resource4
, SQ_SEL_X
,
890 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
891 SETfield(sq_tex_resource4
, SQ_SEL_1
,
892 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
894 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
:
895 SETfield(sq_tex_resource1
, FMT_32_32_FLOAT
,
896 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
898 SETfield(sq_tex_resource4
, SQ_SEL_X
,
899 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
900 SETfield(sq_tex_resource4
, SQ_SEL_X
,
901 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
902 SETfield(sq_tex_resource4
, SQ_SEL_X
,
903 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
904 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
905 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
907 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
:
908 SETfield(sq_tex_resource1
, FMT_16_16_FLOAT
,
909 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
911 SETfield(sq_tex_resource4
, SQ_SEL_X
,
912 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
913 SETfield(sq_tex_resource4
, SQ_SEL_X
,
914 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
915 SETfield(sq_tex_resource4
, SQ_SEL_X
,
916 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
917 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
918 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
920 case MESA_FORMAT_INTENSITY_FLOAT32
: /* X, X, X, X */
921 SETfield(sq_tex_resource1
, FMT_32_FLOAT
,
922 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
924 SETfield(sq_tex_resource4
, SQ_SEL_X
,
925 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
926 SETfield(sq_tex_resource4
, SQ_SEL_X
,
927 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
928 SETfield(sq_tex_resource4
, SQ_SEL_X
,
929 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
930 SETfield(sq_tex_resource4
, SQ_SEL_X
,
931 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
933 case MESA_FORMAT_INTENSITY_FLOAT16
: /* X, X, X, X */
934 SETfield(sq_tex_resource1
, FMT_16_FLOAT
,
935 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
937 SETfield(sq_tex_resource4
, SQ_SEL_X
,
938 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
939 SETfield(sq_tex_resource4
, SQ_SEL_X
,
940 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
941 SETfield(sq_tex_resource4
, SQ_SEL_X
,
942 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
943 SETfield(sq_tex_resource4
, SQ_SEL_X
,
944 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
946 case MESA_FORMAT_Z16
:
947 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
948 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
949 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
950 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
951 SETfield(sq_tex_resource1
, FMT_16
,
952 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
953 SETfield(sq_tex_resource4
, SQ_SEL_X
,
954 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
955 SETfield(sq_tex_resource4
, SQ_SEL_X
,
956 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
957 SETfield(sq_tex_resource4
, SQ_SEL_X
,
958 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
959 SETfield(sq_tex_resource4
, SQ_SEL_X
,
960 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
962 case MESA_FORMAT_X8_Z24
:
963 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
964 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
965 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
966 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
967 SETfield(sq_tex_resource1
, FMT_8_24
,
968 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
969 SETfield(sq_tex_resource4
, SQ_SEL_X
,
970 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
971 SETfield(sq_tex_resource4
, SQ_SEL_1
,
972 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
973 SETfield(sq_tex_resource4
, SQ_SEL_0
,
974 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
975 SETfield(sq_tex_resource4
, SQ_SEL_1
,
976 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
978 case MESA_FORMAT_S8_Z24
:
979 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
980 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
981 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
982 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
983 SETfield(sq_tex_resource1
, FMT_8_24
,
984 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
985 SETfield(sq_tex_resource4
, SQ_SEL_X
,
986 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
987 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
988 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
989 SETfield(sq_tex_resource4
, SQ_SEL_0
,
990 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
991 SETfield(sq_tex_resource4
, SQ_SEL_1
,
992 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
994 case MESA_FORMAT_Z24_S8
:
995 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
996 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
997 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
998 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
999 SETfield(sq_tex_resource1
, FMT_24_8
,
1000 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1001 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1002 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1003 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1004 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1005 SETfield(sq_tex_resource4
, SQ_SEL_0
,
1006 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1007 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1008 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1010 case MESA_FORMAT_Z32
:
1011 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1012 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1013 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1014 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1015 SETfield(sq_tex_resource1
, FMT_32
,
1016 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1017 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1018 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1019 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1020 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1021 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1022 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1023 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1024 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1026 case MESA_FORMAT_S8
:
1027 SETbit(sq_tex_resource0
, TILE_TYPE_bit
);
1028 SETfield(sq_tex_resource0
, ARRAY_1D_TILED_THIN1
,
1029 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift
,
1030 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask
);
1031 SETfield(sq_tex_resource1
, FMT_8
,
1032 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1033 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1034 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1035 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1036 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1037 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1038 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1039 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1040 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1042 case MESA_FORMAT_SRGBA8
:
1043 SETfield(sq_tex_resource1
, FMT_8_8_8_8
,
1044 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1046 SETfield(sq_tex_resource4
, SQ_SEL_W
,
1047 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1048 SETfield(sq_tex_resource4
, SQ_SEL_Z
,
1049 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1050 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1051 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1052 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1053 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1054 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1056 case MESA_FORMAT_SLA8
:
1057 SETfield(sq_tex_resource1
, FMT_8_8
,
1058 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1060 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1061 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1062 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1063 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1064 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1065 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1066 SETfield(sq_tex_resource4
, SQ_SEL_Y
,
1067 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1068 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1070 case MESA_FORMAT_SL8
: /* X, X, X, ONE */
1071 SETfield(sq_tex_resource1
, FMT_8
,
1072 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift
, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask
);
1074 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1075 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
);
1076 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1077 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
);
1078 SETfield(sq_tex_resource4
, SQ_SEL_X
,
1079 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
);
1080 SETfield(sq_tex_resource4
, SQ_SEL_1
,
1081 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift
, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask
);
1082 SETbit(sq_tex_resource4
, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit
);
1085 fprintf(stderr
,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format
));
1086 assert("Invalid format for US output\n");
1090 SETfield(sq_tex_resource0
, (TexelPitch
/8)-1, PITCH_shift
, PITCH_mask
);
1091 SETfield(sq_tex_resource0
, w
- 1, TEX_WIDTH_shift
, TEX_WIDTH_mask
);
1092 SETfield(sq_tex_resource1
, h
- 1, TEX_HEIGHT_shift
, TEX_HEIGHT_mask
);
1094 sq_tex_resource2
= src_offset
/ 256;
1096 SETfield(sq_tex_resource6
, SQ_TEX_VTX_VALID_TEXTURE
,
1097 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift
,
1098 SQ_TEX_RESOURCE_WORD6_0__TYPE_mask
);
1100 r700SyncSurf(context
, bo
,
1101 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
,
1102 0, TC_ACTION_ENA_bit
);
1104 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
1105 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE
, 7));
1106 R600_OUT_BATCH(0 * 7);
1108 R600_OUT_BATCH(sq_tex_resource0
);
1109 R600_OUT_BATCH(sq_tex_resource1
);
1110 R600_OUT_BATCH(sq_tex_resource2
);
1111 R600_OUT_BATCH(0); //SQ_TEX_RESOURCE3
1112 R600_OUT_BATCH(sq_tex_resource4
);
1113 R600_OUT_BATCH(0); //SQ_TEX_RESOURCE5
1114 R600_OUT_BATCH(sq_tex_resource6
);
1115 R600_OUT_BATCH_RELOC(0,
1118 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
1119 R600_OUT_BATCH_RELOC(0,
1122 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
1128 set_tex_sampler(context_t
* context
)
1130 uint32_t sq_tex_sampler_word0
= 0, sq_tex_sampler_word1
= 0, sq_tex_sampler_word2
= 0;
1133 SETbit(sq_tex_sampler_word2
, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit
);
1135 BATCH_LOCALS(&context
->radeon
);
1137 BEGIN_BATCH_NO_AUTOSTATE(5);
1138 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER
, 3));
1139 R600_OUT_BATCH(i
* 3);
1140 R600_OUT_BATCH(sq_tex_sampler_word0
);
1141 R600_OUT_BATCH(sq_tex_sampler_word1
);
1142 R600_OUT_BATCH(sq_tex_sampler_word2
);
1148 set_scissors(context_t
*context
, int x1
, int y1
, int x2
, int y2
)
1150 BATCH_LOCALS(&context
->radeon
);
1152 BEGIN_BATCH_NO_AUTOSTATE(17);
1153 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL
, 2);
1154 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16));
1155 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1157 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET
, 3);
1158 R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1159 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
)); //PA_SC_WINDOW_SCISSOR_TL
1160 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1162 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL
, 2);
1163 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
));
1164 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1166 /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1167 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL
, 2 );
1168 R600_OUT_BATCH((x1
<< 0) | (y1
<< 16) | (WINDOW_OFFSET_DISABLE_bit
));
1169 R600_OUT_BATCH((x2
<< 0) | (y2
<< 16));
1177 set_vb_data(context_t
* context
, int src_x
, int src_y
, int dst_x
, int dst_y
,
1178 int w
, int h
, int src_h
, unsigned flip_y
)
1181 radeon_bo_map(context
->blit_bo
, 1);
1182 vb
= context
->blit_bo
->ptr
;
1184 vb
[0] = (float)(dst_x
);
1185 vb
[1] = (float)(dst_y
);
1186 vb
[2] = (float)(src_x
);
1187 vb
[3] = (flip_y
) ? (float)(src_h
- src_y
) : (float)src_y
;
1189 vb
[4] = (float)(dst_x
);
1190 vb
[5] = (float)(dst_y
+ h
);
1191 vb
[6] = (float)(src_x
);
1192 vb
[7] = (flip_y
) ? (float)(src_h
- (src_y
+ h
)) : (float)(src_y
+ h
);
1194 vb
[8] = (float)(dst_x
+ w
);
1195 vb
[9] = (float)(dst_y
+ h
);
1196 vb
[10] = (float)(src_x
+ w
);
1197 vb
[11] = (flip_y
) ? (float)(src_h
- (src_y
+ h
)) : (float)(src_y
+ h
);
1199 radeon_bo_unmap(context
->blit_bo
);
1204 draw_auto(context_t
*context
)
1206 BATCH_LOCALS(&context
->radeon
);
1207 uint32_t vgt_primitive_type
= 0, vgt_index_type
= 0, vgt_draw_initiator
= 0, vgt_num_indices
;
1209 SETfield(vgt_primitive_type
, DI_PT_RECTLIST
,
1210 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
,
1211 VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
1212 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
,
1214 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
,
1216 SETfield(vgt_draw_initiator
, DI_SRC_SEL_AUTO_INDEX
, SOURCE_SELECT_shift
,
1217 SOURCE_SELECT_mask
);
1219 vgt_num_indices
= 3;
1221 BEGIN_BATCH_NO_AUTOSTATE(10);
1223 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE
, 1);
1224 R600_OUT_BATCH(vgt_primitive_type
);
1226 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
1227 R600_OUT_BATCH(vgt_index_type
);
1229 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
1232 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO
, 1));
1233 R600_OUT_BATCH(vgt_num_indices
);
1234 R600_OUT_BATCH(vgt_draw_initiator
);
1241 set_default_state(context_t
*context
)
1256 int num_ps_stack_entries
;
1257 int num_vs_stack_entries
;
1258 int num_gs_stack_entries
;
1259 int num_es_stack_entries
;
1260 uint32_t sq_config
, sq_gpr_resource_mgmt_1
, sq_gpr_resource_mgmt_2
;
1261 uint32_t sq_thread_resource_mgmt
, sq_stack_resource_mgmt_1
, sq_stack_resource_mgmt_2
;
1262 uint32_t ta_cntl_aux
, db_watermarks
, sq_dyn_gpr_cntl_ps_flush_req
, db_debug
;
1263 BATCH_LOCALS(&context
->radeon
);
1265 switch (context
->radeon
.radeonScreen
->chip_family
) {
1266 case CHIP_FAMILY_R600
:
1272 num_ps_threads
= 136;
1273 num_vs_threads
= 48;
1276 num_ps_stack_entries
= 128;
1277 num_vs_stack_entries
= 128;
1278 num_gs_stack_entries
= 0;
1279 num_es_stack_entries
= 0;
1281 case CHIP_FAMILY_RV630
:
1282 case CHIP_FAMILY_RV635
:
1288 num_ps_threads
= 144;
1289 num_vs_threads
= 40;
1292 num_ps_stack_entries
= 40;
1293 num_vs_stack_entries
= 40;
1294 num_gs_stack_entries
= 32;
1295 num_es_stack_entries
= 16;
1297 case CHIP_FAMILY_RV610
:
1298 case CHIP_FAMILY_RV620
:
1299 case CHIP_FAMILY_RS780
:
1300 case CHIP_FAMILY_RS880
:
1307 num_ps_threads
= 136;
1308 num_vs_threads
= 48;
1311 num_ps_stack_entries
= 40;
1312 num_vs_stack_entries
= 40;
1313 num_gs_stack_entries
= 32;
1314 num_es_stack_entries
= 16;
1316 case CHIP_FAMILY_RV670
:
1322 num_ps_threads
= 136;
1323 num_vs_threads
= 48;
1326 num_ps_stack_entries
= 40;
1327 num_vs_stack_entries
= 40;
1328 num_gs_stack_entries
= 32;
1329 num_es_stack_entries
= 16;
1331 case CHIP_FAMILY_RV770
:
1337 num_ps_threads
= 188;
1338 num_vs_threads
= 60;
1341 num_ps_stack_entries
= 256;
1342 num_vs_stack_entries
= 256;
1343 num_gs_stack_entries
= 0;
1344 num_es_stack_entries
= 0;
1346 case CHIP_FAMILY_RV730
:
1347 case CHIP_FAMILY_RV740
:
1353 num_ps_threads
= 188;
1354 num_vs_threads
= 60;
1357 num_ps_stack_entries
= 128;
1358 num_vs_stack_entries
= 128;
1359 num_gs_stack_entries
= 0;
1360 num_es_stack_entries
= 0;
1362 case CHIP_FAMILY_RV710
:
1368 num_ps_threads
= 144;
1369 num_vs_threads
= 48;
1372 num_ps_stack_entries
= 128;
1373 num_vs_stack_entries
= 128;
1374 num_gs_stack_entries
= 0;
1375 num_es_stack_entries
= 0;
1380 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1381 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1382 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1383 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1384 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1385 CLEARbit(sq_config
, VC_ENABLE_bit
);
1387 SETbit(sq_config
, VC_ENABLE_bit
);
1388 SETbit(sq_config
, DX9_CONSTS_bit
);
1389 SETbit(sq_config
, ALU_INST_PREFER_VECTOR_bit
);
1390 SETfield(sq_config
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1391 SETfield(sq_config
, vs_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1392 SETfield(sq_config
, gs_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1393 SETfield(sq_config
, es_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1395 sq_gpr_resource_mgmt_1
= 0;
1396 SETfield(sq_gpr_resource_mgmt_1
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1397 SETfield(sq_gpr_resource_mgmt_1
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1398 SETfield(sq_gpr_resource_mgmt_1
, num_temp_gprs
,
1399 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1401 sq_gpr_resource_mgmt_2
= 0;
1402 SETfield(sq_gpr_resource_mgmt_2
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1403 SETfield(sq_gpr_resource_mgmt_2
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1405 sq_thread_resource_mgmt
= 0;
1406 SETfield(sq_thread_resource_mgmt
, num_ps_threads
,
1407 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1408 SETfield(sq_thread_resource_mgmt
, num_vs_threads
,
1409 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1410 SETfield(sq_thread_resource_mgmt
, num_gs_threads
,
1411 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1412 SETfield(sq_thread_resource_mgmt
, num_es_threads
,
1413 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1415 sq_stack_resource_mgmt_1
= 0;
1416 SETfield(sq_stack_resource_mgmt_1
, num_ps_stack_entries
,
1417 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1418 SETfield(sq_stack_resource_mgmt_1
, num_vs_stack_entries
,
1419 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1421 sq_stack_resource_mgmt_2
= 0;
1422 SETfield(sq_stack_resource_mgmt_2
, num_gs_stack_entries
,
1423 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1424 SETfield(sq_stack_resource_mgmt_2
, num_es_stack_entries
,
1425 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1428 SETfield(ta_cntl_aux
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1430 SETfield(db_watermarks
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1431 SETfield(db_watermarks
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1432 SETfield(db_watermarks
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1433 SETfield(db_watermarks
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1434 sq_dyn_gpr_cntl_ps_flush_req
= 0;
1436 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1437 SETfield(ta_cntl_aux
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1438 db_debug
= 0x82000000;
1439 SETfield(db_watermarks
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1441 SETfield(ta_cntl_aux
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1442 SETfield(db_watermarks
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1443 SETbit(sq_dyn_gpr_cntl_ps_flush_req
, VS_PC_LIMIT_ENABLE_bit
);
1446 BEGIN_BATCH_NO_AUTOSTATE(117);
1447 R600_OUT_BATCH_REGSEQ(SQ_CONFIG
, 6);
1448 R600_OUT_BATCH(sq_config
);
1449 R600_OUT_BATCH(sq_gpr_resource_mgmt_1
);
1450 R600_OUT_BATCH(sq_gpr_resource_mgmt_2
);
1451 R600_OUT_BATCH(sq_thread_resource_mgmt
);
1452 R600_OUT_BATCH(sq_stack_resource_mgmt_1
);
1453 R600_OUT_BATCH(sq_stack_resource_mgmt_2
);
1455 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX
, ta_cntl_aux
);
1456 R600_OUT_BATCH_REGVAL(VC_ENHANCE
, 0);
1457 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, sq_dyn_gpr_cntl_ps_flush_req
);
1458 R600_OUT_BATCH_REGVAL(DB_DEBUG
, db_debug
);
1459 R600_OUT_BATCH_REGVAL(DB_WATERMARKS
, db_watermarks
);
1461 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE
, 9);
1472 R600_OUT_BATCH_REGVAL(CB_CLRCMP_CONTROL
,
1473 (CLRCMP_SEL_SRC
<< CLRCMP_FCN_SEL_shift
));
1474 R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC
, 0);
1475 R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC
, 0);
1476 R600_OUT_BATCH_REGVAL(DB_DEPTH_INFO
, 0);
1477 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL
, 0);
1478 R600_OUT_BATCH_REGVAL(CB_SHADER_MASK
, (OUTPUT0_ENABLE_mask
));
1479 R600_OUT_BATCH_REGVAL(CB_TARGET_MASK
, (TARGET0_ENABLE_mask
));
1480 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL
, (RT0_ENABLE_bit
));
1481 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL
, (0xcc << ROP3_shift
));
1483 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL
, VTX_XY_FMT_bit
);
1484 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL
, 0);
1485 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL
, CLIP_DISABLE_bit
);
1486 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL
, (FACE_bit
) |
1487 (POLYMODE_PTYPE__TRIANGLES
<< POLYMODE_FRONT_PTYPE_shift
) |
1488 (POLYMODE_PTYPE__TRIANGLES
<< POLYMODE_BACK_PTYPE_shift
));
1489 R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL
, (PIX_CENTER_bit
) |
1490 (X_ROUND_TO_EVEN
<< PA_SU_VTX_CNTL__ROUND_MODE_shift
) |
1491 (X_1_256TH
<< QUANT_MODE_shift
));
1493 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX
, 4);
1494 R600_OUT_BATCH(2048);
1499 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL
, 13);
1514 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN
, 0);
1515 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN
, 0);
1516 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0
, 0);
1517 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1
, 0);
1519 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN
, 3);
1524 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN
, 0);
1530 static GLboolean
validate_buffers(context_t
*rmesa
,
1531 struct radeon_bo
*src_bo
,
1532 struct radeon_bo
*dst_bo
)
1536 radeon_cs_space_reset_bos(rmesa
->radeon
.cmdbuf
.cs
);
1538 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1539 src_bo
, RADEON_GEM_DOMAIN_VRAM
, 0);
1543 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1544 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
);
1548 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1550 RADEON_GEM_DOMAIN_GTT
, 0);
1554 ret
= radeon_cs_space_check_with_bo(rmesa
->radeon
.cmdbuf
.cs
,
1555 first_elem(&rmesa
->radeon
.dma
.reserved
)->bo
,
1556 RADEON_GEM_DOMAIN_GTT
, 0);
1563 unsigned r600_blit(GLcontext
*ctx
,
1564 struct radeon_bo
*src_bo
,
1565 intptr_t src_offset
,
1566 gl_format src_mesaformat
,
1569 unsigned src_height
,
1572 struct radeon_bo
*dst_bo
,
1573 intptr_t dst_offset
,
1574 gl_format dst_mesaformat
,
1577 unsigned dst_height
,
1584 context_t
*context
= R700_CONTEXT(ctx
);
1587 if (!r600_check_blit(dst_mesaformat
))
1590 if (src_bo
== dst_bo
) {
1594 if (src_offset
% 256 || dst_offset
% 256) {
1599 fprintf(stderr
, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1600 src_width
, src_height
, src_pitch
,
1601 _mesa_format_row_stride(src_mesaformat
, src_width
),
1602 _mesa_get_format_name(src_mesaformat
));
1603 fprintf(stderr
, "dst: width %d, height %d, pitch %d, format %s\n",
1604 dst_width
, dst_height
,
1605 _mesa_format_row_stride(dst_mesaformat
, dst_width
),
1606 _mesa_get_format_name(dst_mesaformat
));
1609 /* Flush is needed to make sure that source buffer has correct data */
1612 rcommonEnsureCmdBufSpace(&context
->radeon
, 304, __FUNCTION__
);
1615 load_shaders(context
->radeon
.glCtx
);
1617 if (!validate_buffers(context
, src_bo
, dst_bo
))
1620 /* set clear state */
1622 set_default_state(context
);
1626 set_shaders(context
);
1630 set_tex_resource(context
, src_mesaformat
, src_bo
,
1631 src_width
, src_height
, src_pitch
, src_offset
);
1634 set_tex_sampler(context
);
1638 set_render_target(context
, dst_bo
, dst_mesaformat
,
1639 dst_pitch
, dst_width
, dst_height
, dst_offset
);
1642 set_scissors(context
, dst_x
, dst_y
, dst_x
+ dst_width
, dst_y
+ dst_height
);
1644 set_vb_data(context
, src_x
, src_y
, dst_x
, dst_y
, w
, h
, src_height
, flip_y
);
1645 /* Vertex buffer setup */
1647 set_vtx_resource(context
);
1654 r700SyncSurf(context
, dst_bo
, 0,
1655 RADEON_GEM_DOMAIN_VRAM
|RADEON_GEM_DOMAIN_GTT
,
1656 CB_ACTION_ENA_bit
| (1 << (id
+ 6)));
1659 /* XXX drm should handle this in fence submit */
1660 r700WaitForIdleClean(context
);