src/mesa/drivers/dri/r600/r600_cmdbuf.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #include "main/glheader.h"
  37 #include "main/state.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/context.h"
  41 #include "main/simple_list.h"
  42 #include "swrast/swrast.h"
  43
  44 #include "drm.h"
  45 #include "radeon_drm.h"
  46
  47 #include "r600_context.h"
  48 #include "r600_ioctl.h"
  49 #include "radeon_reg.h"
  50 #include "r600_reg.h"
  51 #include "r600_cmdbuf.h"
  52 #include "r600_emit.h"
  53 #include "radeon_bocs_wrapper.h"
  54 #include "radeon_mipmap_tree.h"
  55 #include "r600_state.h"
  56 #include "radeon_reg.h"
  57
  58 #define R600_VAP_PVS_UPLOAD_ADDRESS 0x2200
  59 #   define RADEON_ONE_REG_WR        (1 << 15)
  60
  61 /** # of dwords reserved for additional instructions that may need to be written
  62  * during flushing.
  63  */
  64 #define SPACE_FOR_FLUSHING      4
  65
  66 static unsigned packet0_count(r600ContextPtr r600, uint32_t *pkt)
  67 {
  68     if (r600->radeon.radeonScreen->kernel_mm) {
  69         return ((((*pkt) >> 16) & 0x3FFF) + 1);
  70     } else {
  71         drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
  72         return t->packet0.count;
  73     }
  74     return 0;
  75 }
  76
  77 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
  78
  79 void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
  80 {
  81         r600ContextPtr r600 = R600_CONTEXT(ctx);
  82         BATCH_LOCALS(&r600->radeon);
  83         drm_r300_cmd_header_t cmd;
  84         uint32_t addr, ndw, i;
  85
  86         if (!r600->radeon.radeonScreen->kernel_mm) {
  87                 uint32_t dwords;
  88                 dwords = (*atom->check) (ctx, atom);
  89                 BEGIN_BATCH_NO_AUTOSTATE(dwords);
  90                 OUT_BATCH_TABLE(atom->cmd, dwords);
  91                 END_BATCH();
  92                 return;
  93         }
  94
  95         cmd.u = atom->cmd[0];
  96         addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
  97         ndw = cmd.vpu.count * 4;
  98         if (ndw) {
  99
 100                 if (r600->vap_flush_needed) {
 101                         BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
 102
 103                         /* flush processing vertices */
 104                         OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0);
 105                         OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 106                         OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 107                         OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0xffffff);
 108                         OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
 109                         r600->vap_flush_needed = GL_FALSE;
 110                 } else {
 111                         BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
 112                 }
 113                 OUT_BATCH_REGVAL(R600_VAP_PVS_UPLOAD_ADDRESS, addr);
 114                 OUT_BATCH(CP_PACKET0(R600_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 115                 for (i = 0; i < ndw; i++) {
 116                         OUT_BATCH(atom->cmd[i+1]);
 117                 }
 118                 OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
 119                 END_BATCH();
 120         }
 121 }
 122
 123 static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 124 {
 125         r600ContextPtr r600 = R600_CONTEXT(ctx);
 126         BATCH_LOCALS(&r600->radeon);
 127         int numtmus = packet0_count(r600, r600->hw.tex.offset.cmd);
 128         int notexture = 0;
 129
 130         if (numtmus) {
 131                 int i;
 132
 133                 for(i = 0; i < numtmus; ++i) {
 134                     radeonTexObj *t = r600->hw.textures[i];
 135
 136                     if (!t)
 137                         notexture = 1;
 138                 }
 139
 140                 if (r600->radeon.radeonScreen->kernel_mm && notexture) {
 141                         return;
 142                 }
 143                 BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
 144                 for(i = 0; i < numtmus; ++i) {
 145                     radeonTexObj *t = r600->hw.textures[i];
 146                     OUT_BATCH_REGSEQ(R600_TX_OFFSET_0 + (i * 4), 1);
 147                     if (t && !t->image_override) {
 148                             OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
 149                                             RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 150                     } else if (!t) {
 151                             OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]);
 152                     } else { /* override cases */
 153                             if (t->bo) {
 154                                     OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
 155                                                     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
 156                             } else if (!r600->radeon.radeonScreen->kernel_mm) {
 157                                     OUT_BATCH(t->override_offset);
 158                             }
 159                             else
 160                                 OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]);
 161                     }
 162                 }
 163                 END_BATCH();
 164         }
 165 }
 166
 167 static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 168 {
 169         r600ContextPtr r600 = R600_CONTEXT(ctx);
 170         BATCH_LOCALS(&r600->radeon);
 171         struct radeon_renderbuffer *rrb;
 172         uint32_t cbpitch;
 173         uint32_t offset = r600->radeon.state.color.draw_offset;
 174
 175         rrb = radeon_get_colorbuffer(&r600->radeon);
 176         if (!rrb || !rrb->bo) {
 177                 fprintf(stderr, "no rrb\n");
 178                 return;
 179         }
 180
 181         cbpitch = (rrb->pitch / rrb->cpp);
 182         if (rrb->cpp == 4)
 183                 cbpitch |= R600_COLOR_FORMAT_ARGB8888;
 184         else
 185                 cbpitch |= R600_COLOR_FORMAT_RGB565;
 186
 187         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
 188                 cbpitch |= R600_COLOR_TILE_ENABLE;
 189
 190         BEGIN_BATCH_NO_AUTOSTATE(8);
 191         OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1);
 192         OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 193         OUT_BATCH_REGSEQ(R600_RB3D_COLORPITCH0, 1);
 194         OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 195         END_BATCH();
 196     if (r600->radeon.radeonScreen->driScreen->dri2.enabled) {
 197         if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 198             BEGIN_BATCH_NO_AUTOSTATE(3);
 199             OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2);
 200             OUT_BATCH(0);
 201             OUT_BATCH((rrb->width << R600_SCISSORS_X_SHIFT) |
 202                     (rrb->height << R600_SCISSORS_Y_SHIFT));
 203             END_BATCH();
 204         } else {
 205             BEGIN_BATCH_NO_AUTOSTATE(3);
 206             OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2);
 207             OUT_BATCH((R600_SCISSORS_OFFSET << R600_SCISSORS_X_SHIFT) |
 208                     (R600_SCISSORS_OFFSET << R600_SCISSORS_Y_SHIFT));
 209             OUT_BATCH(((rrb->width + R600_SCISSORS_OFFSET) << R600_SCISSORS_X_SHIFT) |
 210                     ((rrb->height + R600_SCISSORS_OFFSET) << R600_SCISSORS_Y_SHIFT));
 211             END_BATCH();
 212         }
 213     }
 214 }
 215
 216 static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
 217 {
 218         r600ContextPtr r600 = R600_CONTEXT(ctx);
 219         BATCH_LOCALS(&r600->radeon);
 220         struct radeon_renderbuffer *rrb;
 221         uint32_t zbpitch;
 222
 223         rrb = radeon_get_depthbuffer(&r600->radeon);
 224         if (!rrb)
 225                 return;
 226
 227         zbpitch = (rrb->pitch / rrb->cpp);
 228         if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
 229                 zbpitch |= R600_DEPTHMACROTILE_ENABLE;
 230         }
 231         if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 232                 zbpitch |= R600_DEPTHMICROTILE_TILED;
 233         }
 234
 235         BEGIN_BATCH_NO_AUTOSTATE(6);
 236         OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1);
 237         OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 238         OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, zbpitch);
 239         END_BATCH();
 240 }
 241
 242 static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
 243 {
 244         r600ContextPtr r600 = R600_CONTEXT(ctx);
 245         BATCH_LOCALS(&r600->radeon);
 246         struct radeon_renderbuffer *rrb;
 247         uint32_t format = 0;
 248
 249         rrb = radeon_get_depthbuffer(&r600->radeon);
 250         if (!rrb)
 251           format = 0;
 252         else {
 253           if (rrb->cpp == 2)
 254             format = R600_DEPTHFORMAT_16BIT_INT_Z;
 255           else if (rrb->cpp == 4)
 256             format = R600_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
 257         }
 258
 259         OUT_BATCH(atom->cmd[0]);
 260         atom->cmd[1] &= ~0xf;
 261         atom->cmd[1] |= format;
 262         OUT_BATCH(atom->cmd[1]);
 263         OUT_BATCH(atom->cmd[2]);
 264         OUT_BATCH(atom->cmd[3]);
 265         OUT_BATCH(atom->cmd[4]);
 266 }
 267
 268 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
 269 {
 270         return atom->cmd_size;
 271 }
 272
 273 static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
 274 {
 275         r600ContextPtr r600 = R600_CONTEXT(ctx);
 276         int cnt;
 277         if (atom->cmd[0] == CP_PACKET2) {
 278                 return 0;
 279         }
 280         cnt = packet0_count(r600, atom->cmd);
 281         return cnt ? cnt + 1 : 0;
 282 }
 283
 284 int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom)
 285 {
 286         int cnt;
 287
 288         cnt = vpu_count(atom->cmd);
 289         return cnt ? (cnt * 4) + 1 : 0;
 290 }
 291
 292 #define ALLOC_STATE( ATOM, CHK, SZ, IDX )                               \
 293    do {                                                                 \
 294       r600->hw.ATOM.cmd_size = (SZ);                                    \
 295       r600->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t));   \
 296       r600->hw.ATOM.name = #ATOM;                                       \
 297       r600->hw.ATOM.idx = (IDX);                                        \
 298       r600->hw.ATOM.check = check_##CHK;                                \
 299       r600->hw.ATOM.dirty = GL_FALSE;                                   \
 300       r600->radeon.hw.max_state_size += (SZ);                                   \
 301       insert_at_tail(&r600->radeon.hw.atomlist, &r600->hw.ATOM);                \
 302    } while (0)
 303 /**
 304  * Allocate memory for the command buffer and initialize the state atom
 305  * list. Note that the initial hardware state is set by r600InitState().
 306  */
 307 void r600InitCmdBuf(r600ContextPtr r600)
 308 {
 309         int mtu;
 310         int i;
 311
 312         r600->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
 313
 314         mtu = r600->radeon.glCtx->Const.MaxTextureUnits;
 315         if (RADEON_DEBUG & DEBUG_TEXTURE) {
 316                 fprintf(stderr, "Using %d maximum texture units..\n", mtu);
 317         }
 318
 319         /* Setup the atom linked list */
 320         make_empty_list(&r600->radeon.hw.atomlist);
 321         r600->radeon.hw.atomlist.name = "atom-list";
 322
 323         /* Initialize state atoms */
 324         ALLOC_STATE(vpt, always, R600_VPT_CMDSIZE, 0);
 325         r600->hw.vpt.cmd[R600_VPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VPORT_XSCALE, 6);
 326         ALLOC_STATE(vap_cntl, always, R600_VAP_CNTL_SIZE, 0);
 327         r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_STATE_FLUSH_REG, 1);
 328         r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH_1] = 0;
 329         r600->hw.vap_cntl.cmd[R600_VAP_CNTL_CMD] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL, 1);
 330
 331         ALLOC_STATE(vte, always, 3, 0);
 332         r600->hw.vte.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VTE_CNTL, 2);
 333         ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
 334         r600->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VF_MAX_VTX_INDX, 2);
 335         ALLOC_STATE(vap_cntl_status, always, 2, 0);
 336         r600->hw.vap_cntl_status.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL_STATUS, 1);
 337         ALLOC_STATE(vir[0], variable, R600_VIR_CMDSIZE, 0);
 338         r600->hw.vir[0].cmd[R600_VIR_CMD_0] =
 339             cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_0, 1);
 340         ALLOC_STATE(vir[1], variable, R600_VIR_CMDSIZE, 1);
 341         r600->hw.vir[1].cmd[R600_VIR_CMD_0] =
 342             cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_EXT_0, 1);
 343         ALLOC_STATE(vic, always, R600_VIC_CMDSIZE, 0);
 344         r600->hw.vic.cmd[R600_VIC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VTX_STATE_CNTL, 2);
 345         ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
 346         r600->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
 347
 348         ALLOC_STATE(vap_clip_cntl, always, 2, 0);
 349         r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1);
 350         ALLOC_STATE(vap_clip, always, 5, 0);
 351         r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4);
 352         ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
 353         r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
 354
 355         ALLOC_STATE(vof, always, R600_VOF_CMDSIZE, 0);
 356         r600->hw.vof.cmd[R600_VOF_CMD_0] =
 357             cmdpacket0(r600->radeon.radeonScreen, R600_VAP_OUTPUT_VTX_FMT_0, 2);
 358
 359         ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0);
 360         r600->hw.pvs.cmd[R600_PVS_CMD_0] =
 361                 cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3);
 362
 363         ALLOC_STATE(gb_enable, always, 2, 0);
 364         r600->hw.gb_enable.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_ENABLE, 1);
 365         ALLOC_STATE(gb_misc, always, R600_GB_MISC_CMDSIZE, 0);
 366         r600->hw.gb_misc.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_MSPOS0, 5);
 367         ALLOC_STATE(txe, always, R600_TXE_CMDSIZE, 0);
 368         r600->hw.txe.cmd[R600_TXE_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_ENABLE, 1);
 369         ALLOC_STATE(ga_point_s0, always, 5, 0);
 370         r600->hw.ga_point_s0.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_S0, 4);
 371         ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
 372         r600->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_TRIANGLE_STIPPLE, 1);
 373         ALLOC_STATE(ps, always, R600_PS_CMDSIZE, 0);
 374         r600->hw.ps.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_SIZE, 1);
 375         ALLOC_STATE(ga_point_minmax, always, 4, 0);
 376         r600->hw.ga_point_minmax.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_MINMAX, 3);
 377         ALLOC_STATE(lcntl, always, 2, 0);
 378         r600->hw.lcntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_CNTL, 1);
 379         ALLOC_STATE(ga_line_stipple, always, 4, 0);
 380         r600->hw.ga_line_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_STIPPLE_VALUE, 3);
 381         ALLOC_STATE(shade, always, 5, 0);
 382         r600->hw.shade.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_ENHANCE, 4);
 383         ALLOC_STATE(polygon_mode, always, 4, 0);
 384         r600->hw.polygon_mode.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POLY_MODE, 3);
 385         ALLOC_STATE(fogp, always, 3, 0);
 386         r600->hw.fogp.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_FOG_SCALE, 2);
 387         ALLOC_STATE(zbias_cntl, always, 2, 0);
 388         r600->hw.zbias_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_TEX_WRAP, 1);
 389         ALLOC_STATE(zbs, always, R600_ZBS_CMDSIZE, 0);
 390         r600->hw.zbs.cmd[R600_ZBS_CMD_0] =
 391             cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_FRONT_SCALE, 4);
 392         ALLOC_STATE(occlusion_cntl, always, 2, 0);
 393         r600->hw.occlusion_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_ENABLE, 1);
 394         ALLOC_STATE(cul, always, R600_CUL_CMDSIZE, 0);
 395         r600->hw.cul.cmd[R600_CUL_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_CULL_MODE, 1);
 396         ALLOC_STATE(su_depth_scale, always, 3, 0);
 397         r600->hw.su_depth_scale.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_DEPTH_SCALE, 2);
 398         ALLOC_STATE(rc, always, R600_RC_CMDSIZE, 0);
 399         r600->hw.rc.cmd[R600_RC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_COUNT, 2);
 400
 401         ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0);
 402         r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8);
 403         ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0);
 404         r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1);
 405
 406         ALLOC_STATE(sc_hyperz, always, 3, 0);
 407         r600->hw.sc_hyperz.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_HYPERZ, 2);
 408         ALLOC_STATE(sc_screendoor, always, 2, 0);
 409         r600->hw.sc_screendoor.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_SCREENDOOR, 1);
 410         ALLOC_STATE(us_out_fmt, always, 6, 0);
 411         r600->hw.us_out_fmt.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_OUT_FMT, 5);
 412
 413         ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0);
 414         r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3);
 415         r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4);
 416
 417         ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0);
 418         r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0);
 419
 420         ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0);
 421         r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1);
 422         ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1);
 423         r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1);
 424         ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2);
 425         r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1);
 426         ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3);
 427         r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1);
 428         ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0);
 429         r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0);
 430
 431         ALLOC_STATE(fogs, always, R600_FOGS_CMDSIZE, 0);
 432         r600->hw.fogs.cmd[R600_FOGS_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_BLEND, 1);
 433         ALLOC_STATE(fogc, always, R600_FOGC_CMDSIZE, 0);
 434         r600->hw.fogc.cmd[R600_FOGC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_COLOR_R, 3);
 435         ALLOC_STATE(at, always, R600_AT_CMDSIZE, 0);
 436         r600->hw.at.cmd[R600_AT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_ALPHA_FUNC, 2);
 437         ALLOC_STATE(fg_depth_src, always, 2, 0);
 438         r600->hw.fg_depth_src.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_DEPTH_SRC, 1);
 439         ALLOC_STATE(rb3d_cctl, always, 2, 0);
 440         r600->hw.rb3d_cctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CCTL, 1);
 441         ALLOC_STATE(bld, always, R600_BLD_CMDSIZE, 0);
 442         r600->hw.bld.cmd[R600_BLD_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CBLEND, 2);
 443         ALLOC_STATE(cmk, always, R600_CMK_CMDSIZE, 0);
 444         r600->hw.cmk.cmd[R600_CMK_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
 445
 446         ALLOC_STATE(blend_color, always, 2, 0);
 447         r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1);
 448
 449         ALLOC_STATE(rop, always, 2, 0);
 450         r600->hw.rop.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_ROPCNTL, 1);
 451         ALLOC_STATE(cb, always, R600_CB_CMDSIZE, 0);
 452         r600->hw.cb.emit = &emit_cb_offset;
 453         ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
 454         r600->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_DITHER_CTL, 9);
 455         ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
 456         r600->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_AARESOLVE_CTL, 1);
 457
 458         ALLOC_STATE(zs, always, R600_ZS_CMDSIZE, 0);
 459         r600->hw.zs.cmd[R600_ZS_CMD_0] =
 460             cmdpacket0(r600->radeon.radeonScreen, R600_ZB_CNTL, 3);
 461
 462         ALLOC_STATE(zstencil_format, always, 5, 0);
 463         r600->hw.zstencil_format.cmd[0] =
 464             cmdpacket0(r600->radeon.radeonScreen, R600_ZB_FORMAT, 4);
 465         r600->hw.zstencil_format.emit = emit_zstencil_format;
 466
 467         ALLOC_STATE(zb, always, R600_ZB_CMDSIZE, 0);
 468         r600->hw.zb.emit = emit_zb_offset;
 469         ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
 470         r600->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_DEPTHCLEARVALUE, 1);
 471         ALLOC_STATE(unk4F30, always, 3, 0);
 472         r600->hw.unk4F30.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, 0x4F30, 2);
 473         ALLOC_STATE(zb_hiz_offset, always, 2, 0);
 474         r600->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_OFFSET, 1);
 475         ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
 476         r600->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_PITCH, 1);
 477
 478         ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0);
 479         r600->hw.vpi.cmd[0] =
 480                 cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0);
 481         r600->hw.vpi.emit = emit_vpu;
 482
 483         ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0);
 484         r600->hw.vpp.cmd[0] =
 485                 cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0);
 486         r600->hw.vpp.emit = emit_vpu;
 487
 488         ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0);
 489         r600->hw.vps.cmd[0] =
 490                 cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1);
 491         r600->hw.vps.emit = emit_vpu;
 492
 493         for (i = 0; i < 6; i++) {
 494                 ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0);
 495                 r600->hw.vpucp[i].cmd[0] =
 496                         cmdvpu(r600->radeon.radeonScreen,
 497                                R600_PVS_UCP_START + i, 1);
 498                 r600->hw.vpucp[i].emit = emit_vpu;
 499         }
 500
 501         /* Textures */
 502         ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
 503         r600->hw.tex.filter.cmd[R600_TEX_CMD_0] =
 504             cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 0);
 505
 506         ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
 507         r600->hw.tex.filter_1.cmd[R600_TEX_CMD_0] =
 508             cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER1_0, 0);
 509
 510         ALLOC_STATE(tex.size, variable, mtu + 1, 0);
 511         r600->hw.tex.size.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_SIZE_0, 0);
 512
 513         ALLOC_STATE(tex.format, variable, mtu + 1, 0);
 514         r600->hw.tex.format.cmd[R600_TEX_CMD_0] =
 515             cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT_0, 0);
 516
 517         ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
 518         r600->hw.tex.pitch.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT2_0, 0);
 519
 520         ALLOC_STATE(tex.offset, variable, 1, 0);
 521         r600->hw.tex.offset.cmd[R600_TEX_CMD_0] =
 522             cmdpacket0(r600->radeon.radeonScreen, R600_TX_OFFSET_0, 0);
 523         r600->hw.tex.offset.emit = &emit_tex_offsets;
 524
 525         ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
 526         r600->hw.tex.chroma_key.cmd[R600_TEX_CMD_0] =
 527             cmdpacket0(r600->radeon.radeonScreen, R600_TX_CHROMA_KEY_0, 0);
 528
 529         ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
 530         r600->hw.tex.border_color.cmd[R600_TEX_CMD_0] =
 531             cmdpacket0(r600->radeon.radeonScreen, R600_TX_BORDER_COLOR_0, 0);
 532
 533         r600->radeon.hw.is_dirty = GL_TRUE;
 534         r600->radeon.hw.all_dirty = GL_TRUE;
 535
 536         rcommonInitCmdBuf(&r600->radeon);
 537 }