2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Nicolai Haehnle <prefect_@gmx.net>
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
45 #include "radeon_drm.h"
47 #include "r600_context.h"
48 #include "r600_ioctl.h"
49 #include "radeon_reg.h"
51 #include "r600_cmdbuf.h"
52 #include "r600_emit.h"
53 #include "radeon_bocs_wrapper.h"
54 #include "radeon_mipmap_tree.h"
55 #include "r600_state.h"
56 #include "radeon_reg.h"
58 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
59 # define RADEON_ONE_REG_WR (1 << 15)
61 /** # of dwords reserved for additional instructions that may need to be written
64 #define SPACE_FOR_FLUSHING 4
66 static unsigned packet0_count(r300ContextPtr r300
, uint32_t *pkt
)
68 if (r300
->radeon
.radeonScreen
->kernel_mm
) {
69 return ((((*pkt
) >> 16) & 0x3FFF) + 1);
71 drm_r300_cmd_header_t
*t
= (drm_r300_cmd_header_t
*)pkt
;
72 return t
->packet0
.count
;
77 #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
78 #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
80 void emit_vpu(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
82 r300ContextPtr r300
= R300_CONTEXT(ctx
);
83 BATCH_LOCALS(&r300
->radeon
);
84 drm_r300_cmd_header_t cmd
;
85 uint32_t addr
, ndw
, i
;
87 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
89 dwords
= (*atom
->check
) (ctx
, atom
);
90 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
91 OUT_BATCH_TABLE(atom
->cmd
, dwords
);
97 addr
= (cmd
.vpu
.adrhi
<< 8) | cmd
.vpu
.adrlo
;
98 ndw
= cmd
.vpu
.count
* 4;
101 if (r300
->vap_flush_needed
) {
102 BEGIN_BATCH_NO_AUTOSTATE(15 + ndw
);
104 /* flush processing vertices */
105 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR
, 0);
106 OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT
, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
107 OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL
, RADEON_WAIT_3D_IDLECLEAN
);
108 OUT_BATCH_REGVAL(R300_SC_SCREENDOOR
, 0xffffff);
109 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
110 r300
->vap_flush_needed
= GL_FALSE
;
112 BEGIN_BATCH_NO_AUTOSTATE(5 + ndw
);
114 OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS
, addr
);
115 OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
116 for (i
= 0; i
< ndw
; i
++) {
117 OUT_BATCH(atom
->cmd
[i
+1]);
119 OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
124 void emit_r500fp(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
126 r300ContextPtr r300
= R300_CONTEXT(ctx
);
127 BATCH_LOCALS(&r300
->radeon
);
128 drm_r300_cmd_header_t cmd
;
129 uint32_t addr
, ndw
, i
, sz
;
130 int type
, clamp
, stride
;
132 if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
134 dwords
= (*atom
->check
) (ctx
, atom
);
135 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
136 OUT_BATCH_TABLE(atom
->cmd
, dwords
);
141 cmd
.u
= atom
->cmd
[0];
142 sz
= cmd
.r500fp
.count
;
143 addr
= ((cmd
.r500fp
.adrhi_flags
& 1) << 8) | cmd
.r500fp
.adrlo
;
144 type
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_TYPE
);
145 clamp
= !!(cmd
.r500fp
.adrhi_flags
& R500FP_CONSTANT_CLAMP
);
147 addr
|= (type
<< 16);
148 addr
|= (clamp
<< 17);
150 stride
= type
? 4 : 6;
155 BEGIN_BATCH_NO_AUTOSTATE(3 + ndw
);
156 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX
, 0));
158 OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA
, ndw
-1) | RADEON_ONE_REG_WR
);
159 for (i
= 0; i
< ndw
; i
++) {
160 OUT_BATCH(atom
->cmd
[i
+1]);
166 static void emit_tex_offsets(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
168 r300ContextPtr r300
= R300_CONTEXT(ctx
);
169 BATCH_LOCALS(&r300
->radeon
);
170 int numtmus
= packet0_count(r300
, r300
->hw
.tex
.offset
.cmd
);
176 for(i
= 0; i
< numtmus
; ++i
) {
177 radeonTexObj
*t
= r300
->hw
.textures
[i
];
183 if (r300
->radeon
.radeonScreen
->kernel_mm
&& notexture
) {
186 BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus
);
187 for(i
= 0; i
< numtmus
; ++i
) {
188 radeonTexObj
*t
= r300
->hw
.textures
[i
];
189 OUT_BATCH_REGSEQ(R300_TX_OFFSET_0
+ (i
* 4), 1);
190 if (t
&& !t
->image_override
) {
191 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, 0,
192 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
194 OUT_BATCH(r300
->radeon
.radeonScreen
->texOffset
[0]);
195 } else { /* override cases */
197 OUT_BATCH_RELOC(t
->tile_bits
, t
->bo
, 0,
198 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
199 } else if (!r300
->radeon
.radeonScreen
->kernel_mm
) {
200 OUT_BATCH(t
->override_offset
);
203 OUT_BATCH(r300
->radeon
.radeonScreen
->texOffset
[0]);
210 static void emit_cb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
212 r300ContextPtr r300
= R300_CONTEXT(ctx
);
213 BATCH_LOCALS(&r300
->radeon
);
214 struct radeon_renderbuffer
*rrb
;
216 uint32_t offset
= r300
->radeon
.state
.color
.draw_offset
;
218 rrb
= radeon_get_colorbuffer(&r300
->radeon
);
219 if (!rrb
|| !rrb
->bo
) {
220 fprintf(stderr
, "no rrb\n");
224 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
226 cbpitch
|= R300_COLOR_FORMAT_ARGB8888
;
228 cbpitch
|= R300_COLOR_FORMAT_RGB565
;
230 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
231 cbpitch
|= R300_COLOR_TILE_ENABLE
;
233 BEGIN_BATCH_NO_AUTOSTATE(8);
234 OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0
, 1);
235 OUT_BATCH_RELOC(offset
, rrb
->bo
, offset
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
236 OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0
, 1);
237 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, cbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
239 if (r300
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
240 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
) {
241 BEGIN_BATCH_NO_AUTOSTATE(3);
242 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
244 OUT_BATCH((rrb
->width
<< R300_SCISSORS_X_SHIFT
) |
245 (rrb
->height
<< R300_SCISSORS_Y_SHIFT
));
248 BEGIN_BATCH_NO_AUTOSTATE(3);
249 OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL
, 2);
250 OUT_BATCH((R300_SCISSORS_OFFSET
<< R300_SCISSORS_X_SHIFT
) |
251 (R300_SCISSORS_OFFSET
<< R300_SCISSORS_Y_SHIFT
));
252 OUT_BATCH(((rrb
->width
+ R300_SCISSORS_OFFSET
) << R300_SCISSORS_X_SHIFT
) |
253 ((rrb
->height
+ R300_SCISSORS_OFFSET
) << R300_SCISSORS_Y_SHIFT
));
259 static void emit_zb_offset(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
261 r300ContextPtr r300
= R300_CONTEXT(ctx
);
262 BATCH_LOCALS(&r300
->radeon
);
263 struct radeon_renderbuffer
*rrb
;
266 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
270 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
271 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
) {
272 zbpitch
|= R300_DEPTHMACROTILE_ENABLE
;
274 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
){
275 zbpitch
|= R300_DEPTHMICROTILE_TILED
;
278 BEGIN_BATCH_NO_AUTOSTATE(6);
279 OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET
, 1);
280 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
281 OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH
, zbpitch
);
285 static void emit_zstencil_format(GLcontext
*ctx
, struct radeon_state_atom
* atom
)
287 r300ContextPtr r300
= R300_CONTEXT(ctx
);
288 BATCH_LOCALS(&r300
->radeon
);
289 struct radeon_renderbuffer
*rrb
;
292 rrb
= radeon_get_depthbuffer(&r300
->radeon
);
297 format
= R300_DEPTHFORMAT_16BIT_INT_Z
;
298 else if (rrb
->cpp
== 4)
299 format
= R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL
;
302 OUT_BATCH(atom
->cmd
[0]);
303 atom
->cmd
[1] &= ~0xf;
304 atom
->cmd
[1] |= format
;
305 OUT_BATCH(atom
->cmd
[1]);
306 OUT_BATCH(atom
->cmd
[2]);
307 OUT_BATCH(atom
->cmd
[3]);
308 OUT_BATCH(atom
->cmd
[4]);
311 static int check_always(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
313 return atom
->cmd_size
;
316 static int check_variable(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
318 r300ContextPtr r300
= R300_CONTEXT(ctx
);
320 if (atom
->cmd
[0] == CP_PACKET2
) {
323 cnt
= packet0_count(r300
, atom
->cmd
);
324 return cnt
? cnt
+ 1 : 0;
327 int check_vpu(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
331 cnt
= vpu_count(atom
->cmd
);
332 return cnt
? (cnt
* 4) + 1 : 0;
335 int check_r500fp(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
339 cnt
= r500fp_count(atom
->cmd
);
340 return cnt
? (cnt
* 6) + 1 : 0;
343 int check_r500fp_const(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
347 cnt
= r500fp_count(atom
->cmd
);
348 return cnt
? (cnt
* 4) + 1 : 0;
351 #define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
353 r300->hw.ATOM.cmd_size = (SZ); \
354 r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
355 r300->hw.ATOM.name = #ATOM; \
356 r300->hw.ATOM.idx = (IDX); \
357 r300->hw.ATOM.check = check_##CHK; \
358 r300->hw.ATOM.dirty = GL_FALSE; \
359 r300->radeon.hw.max_state_size += (SZ); \
360 insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
363 * Allocate memory for the command buffer and initialize the state atom
364 * list. Note that the initial hardware state is set by r300InitState().
366 void r300InitCmdBuf(r300ContextPtr r300
)
373 if (!(r300
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
))
376 if (r300
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
379 r300
->radeon
.hw
.max_state_size
= 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
381 mtu
= r300
->radeon
.glCtx
->Const
.MaxTextureUnits
;
382 if (RADEON_DEBUG
& DEBUG_TEXTURE
) {
383 fprintf(stderr
, "Using %d maximum texture units..\n", mtu
);
386 /* Setup the atom linked list */
387 make_empty_list(&r300
->radeon
.hw
.atomlist
);
388 r300
->radeon
.hw
.atomlist
.name
= "atom-list";
390 /* Initialize state atoms */
391 ALLOC_STATE(vpt
, always
, R300_VPT_CMDSIZE
, 0);
392 r300
->hw
.vpt
.cmd
[R300_VPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VPORT_XSCALE
, 6);
393 ALLOC_STATE(vap_cntl
, always
, R300_VAP_CNTL_SIZE
, 0);
394 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_STATE_FLUSH_REG
, 1);
395 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_FLUSH_1
] = 0;
396 r300
->hw
.vap_cntl
.cmd
[R300_VAP_CNTL_CMD
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL
, 1);
398 ALLOC_STATE(vap_index_offset
, always
, 2, 0);
399 r300
->hw
.vap_index_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_VAP_INDEX_OFFSET
, 1);
400 r300
->hw
.vap_index_offset
.cmd
[1] = 0;
402 ALLOC_STATE(vte
, always
, 3, 0);
403 r300
->hw
.vte
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SE_VTE_CNTL
, 2);
404 ALLOC_STATE(vap_vf_max_vtx_indx
, always
, 3, 0);
405 r300
->hw
.vap_vf_max_vtx_indx
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VF_MAX_VTX_INDX
, 2);
406 ALLOC_STATE(vap_cntl_status
, always
, 2, 0);
407 r300
->hw
.vap_cntl_status
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CNTL_STATUS
, 1);
408 ALLOC_STATE(vir
[0], variable
, R300_VIR_CMDSIZE
, 0);
409 r300
->hw
.vir
[0].cmd
[R300_VIR_CMD_0
] =
410 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_0
, 1);
411 ALLOC_STATE(vir
[1], variable
, R300_VIR_CMDSIZE
, 1);
412 r300
->hw
.vir
[1].cmd
[R300_VIR_CMD_0
] =
413 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PROG_STREAM_CNTL_EXT_0
, 1);
414 ALLOC_STATE(vic
, always
, R300_VIC_CMDSIZE
, 0);
415 r300
->hw
.vic
.cmd
[R300_VIC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_VTX_STATE_CNTL
, 2);
416 ALLOC_STATE(vap_psc_sgn_norm_cntl
, always
, 2, 0);
417 r300
->hw
.vap_psc_sgn_norm_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PSC_SGN_NORM_CNTL
, SGN_NORM_ZERO_CLAMP_MINUS_ONE
);
420 ALLOC_STATE(vap_clip_cntl
, always
, 2, 0);
421 r300
->hw
.vap_clip_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_CLIP_CNTL
, 1);
422 ALLOC_STATE(vap_clip
, always
, 5, 0);
423 r300
->hw
.vap_clip
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_GB_VERT_CLIP_ADJ
, 4);
424 ALLOC_STATE(vap_pvs_vtx_timeout_reg
, always
, 2, 0);
425 r300
->hw
.vap_pvs_vtx_timeout_reg
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, VAP_PVS_VTX_TIMEOUT_REG
, 1);
428 ALLOC_STATE(vof
, always
, R300_VOF_CMDSIZE
, 0);
429 r300
->hw
.vof
.cmd
[R300_VOF_CMD_0
] =
430 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_OUTPUT_VTX_FMT_0
, 2);
433 ALLOC_STATE(pvs
, always
, R300_PVS_CMDSIZE
, 0);
434 r300
->hw
.pvs
.cmd
[R300_PVS_CMD_0
] =
435 cmdpacket0(r300
->radeon
.radeonScreen
, R300_VAP_PVS_CODE_CNTL_0
, 3);
438 ALLOC_STATE(gb_enable
, always
, 2, 0);
439 r300
->hw
.gb_enable
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_ENABLE
, 1);
440 ALLOC_STATE(gb_misc
, always
, R300_GB_MISC_CMDSIZE
, 0);
441 r300
->hw
.gb_misc
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GB_MSPOS0
, 5);
442 ALLOC_STATE(txe
, always
, R300_TXE_CMDSIZE
, 0);
443 r300
->hw
.txe
.cmd
[R300_TXE_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_ENABLE
, 1);
444 ALLOC_STATE(ga_point_s0
, always
, 5, 0);
445 r300
->hw
.ga_point_s0
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_S0
, 4);
446 ALLOC_STATE(ga_triangle_stipple
, always
, 2, 0);
447 r300
->hw
.ga_triangle_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_TRIANGLE_STIPPLE
, 1);
448 ALLOC_STATE(ps
, always
, R300_PS_CMDSIZE
, 0);
449 r300
->hw
.ps
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_SIZE
, 1);
450 ALLOC_STATE(ga_point_minmax
, always
, 4, 0);
451 r300
->hw
.ga_point_minmax
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POINT_MINMAX
, 3);
452 ALLOC_STATE(lcntl
, always
, 2, 0);
453 r300
->hw
.lcntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_CNTL
, 1);
454 ALLOC_STATE(ga_line_stipple
, always
, 4, 0);
455 r300
->hw
.ga_line_stipple
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_LINE_STIPPLE_VALUE
, 3);
456 ALLOC_STATE(shade
, always
, 5, 0);
457 r300
->hw
.shade
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_ENHANCE
, 4);
458 ALLOC_STATE(polygon_mode
, always
, 4, 0);
459 r300
->hw
.polygon_mode
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_POLY_MODE
, 3);
460 ALLOC_STATE(fogp
, always
, 3, 0);
461 r300
->hw
.fogp
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_GA_FOG_SCALE
, 2);
462 ALLOC_STATE(zbias_cntl
, always
, 2, 0);
463 r300
->hw
.zbias_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_TEX_WRAP
, 1);
464 ALLOC_STATE(zbs
, always
, R300_ZBS_CMDSIZE
, 0);
465 r300
->hw
.zbs
.cmd
[R300_ZBS_CMD_0
] =
466 cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_FRONT_SCALE
, 4);
467 ALLOC_STATE(occlusion_cntl
, always
, 2, 0);
468 r300
->hw
.occlusion_cntl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_POLY_OFFSET_ENABLE
, 1);
469 ALLOC_STATE(cul
, always
, R300_CUL_CMDSIZE
, 0);
470 r300
->hw
.cul
.cmd
[R300_CUL_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_CULL_MODE
, 1);
471 ALLOC_STATE(su_depth_scale
, always
, 3, 0);
472 r300
->hw
.su_depth_scale
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SU_DEPTH_SCALE
, 2);
473 ALLOC_STATE(rc
, always
, R300_RC_CMDSIZE
, 0);
474 r300
->hw
.rc
.cmd
[R300_RC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_COUNT
, 2);
476 ALLOC_STATE(ri
, always
, R500_RI_CMDSIZE
, 0);
477 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_IP_0
, 16);
478 for (i
= 0; i
< 8; i
++) {
479 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
+ i
+1] =
480 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_S_SHIFT
) |
481 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_T_SHIFT
) |
482 (R500_RS_IP_PTR_K0
<< R500_RS_IP_TEX_PTR_R_SHIFT
) |
483 (R500_RS_IP_PTR_K1
<< R500_RS_IP_TEX_PTR_Q_SHIFT
);
485 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
486 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RS_INST_0
, 1);
488 ALLOC_STATE(ri
, always
, R300_RI_CMDSIZE
, 0);
489 r300
->hw
.ri
.cmd
[R300_RI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_IP_0
, 8);
490 ALLOC_STATE(rr
, variable
, R300_RR_CMDSIZE
, 0);
491 r300
->hw
.rr
.cmd
[R300_RR_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RS_INST_0
, 1);
493 ALLOC_STATE(sc_hyperz
, always
, 3, 0);
494 r300
->hw
.sc_hyperz
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_HYPERZ
, 2);
495 ALLOC_STATE(sc_screendoor
, always
, 2, 0);
496 r300
->hw
.sc_screendoor
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_SC_SCREENDOOR
, 1);
497 ALLOC_STATE(us_out_fmt
, always
, 6, 0);
498 r300
->hw
.us_out_fmt
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_OUT_FMT
, 5);
501 ALLOC_STATE(fp
, always
, R500_FP_CMDSIZE
, 0);
502 r300
->hw
.fp
.cmd
[R500_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CONFIG
, 2);
503 r300
->hw
.fp
.cmd
[R500_FP_CNTL
] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO
;
504 r300
->hw
.fp
.cmd
[R500_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_CODE_ADDR
, 3);
505 r300
->hw
.fp
.cmd
[R500_FP_CMD_2
] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_US_FC_CTRL
, 1);
506 r300
->hw
.fp
.cmd
[R500_FP_FC_CNTL
] = 0; /* FIXME when we add flow control */
508 ALLOC_STATE(r500fp
, r500fp
, R500_FPI_CMDSIZE
, 0);
509 r300
->hw
.r500fp
.cmd
[R300_FPI_CMD_0
] =
510 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 0, 0);
511 r300
->hw
.r500fp
.emit
= emit_r500fp
;
512 ALLOC_STATE(r500fp_const
, r500fp_const
, R500_FPP_CMDSIZE
, 0);
513 r300
->hw
.r500fp_const
.cmd
[R300_FPI_CMD_0
] =
514 cmdr500fp(r300
->radeon
.radeonScreen
, 0, 0, 1, 0);
515 r300
->hw
.r500fp_const
.emit
= emit_r500fp
;
517 ALLOC_STATE(fp
, always
, R300_FP_CMDSIZE
, 0);
518 r300
->hw
.fp
.cmd
[R300_FP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CONFIG
, 3);
519 r300
->hw
.fp
.cmd
[R300_FP_CMD_1
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_CODE_ADDR_0
, 4);
521 ALLOC_STATE(fpt
, variable
, R300_FPT_CMDSIZE
, 0);
522 r300
->hw
.fpt
.cmd
[R300_FPT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_TEX_INST_0
, 0);
524 ALLOC_STATE(fpi
[0], variable
, R300_FPI_CMDSIZE
, 0);
525 r300
->hw
.fpi
[0].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_INST_0
, 1);
526 ALLOC_STATE(fpi
[1], variable
, R300_FPI_CMDSIZE
, 1);
527 r300
->hw
.fpi
[1].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_RGB_ADDR_0
, 1);
528 ALLOC_STATE(fpi
[2], variable
, R300_FPI_CMDSIZE
, 2);
529 r300
->hw
.fpi
[2].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_INST_0
, 1);
530 ALLOC_STATE(fpi
[3], variable
, R300_FPI_CMDSIZE
, 3);
531 r300
->hw
.fpi
[3].cmd
[R300_FPI_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_US_ALU_ALPHA_ADDR_0
, 1);
532 ALLOC_STATE(fpp
, variable
, R300_FPP_CMDSIZE
, 0);
533 r300
->hw
.fpp
.cmd
[R300_FPP_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_PFS_PARAM_0_X
, 0);
535 ALLOC_STATE(fogs
, always
, R300_FOGS_CMDSIZE
, 0);
536 r300
->hw
.fogs
.cmd
[R300_FOGS_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_BLEND
, 1);
537 ALLOC_STATE(fogc
, always
, R300_FOGC_CMDSIZE
, 0);
538 r300
->hw
.fogc
.cmd
[R300_FOGC_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_FOG_COLOR_R
, 3);
539 ALLOC_STATE(at
, always
, R300_AT_CMDSIZE
, 0);
540 r300
->hw
.at
.cmd
[R300_AT_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_ALPHA_FUNC
, 2);
541 ALLOC_STATE(fg_depth_src
, always
, 2, 0);
542 r300
->hw
.fg_depth_src
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_FG_DEPTH_SRC
, 1);
543 ALLOC_STATE(rb3d_cctl
, always
, 2, 0);
544 r300
->hw
.rb3d_cctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CCTL
, 1);
545 ALLOC_STATE(bld
, always
, R300_BLD_CMDSIZE
, 0);
546 r300
->hw
.bld
.cmd
[R300_BLD_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_CBLEND
, 2);
547 ALLOC_STATE(cmk
, always
, R300_CMK_CMDSIZE
, 0);
548 r300
->hw
.cmk
.cmd
[R300_CMK_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, RB3D_COLOR_CHANNEL_MASK
, 1);
550 ALLOC_STATE(blend_color
, always
, 3, 0);
551 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_CONSTANT_COLOR_AR
, 2);
553 ALLOC_STATE(blend_color
, always
, 2, 0);
554 r300
->hw
.blend_color
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_BLEND_COLOR
, 1);
556 ALLOC_STATE(rop
, always
, 2, 0);
557 r300
->hw
.rop
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_ROPCNTL
, 1);
558 ALLOC_STATE(cb
, always
, R300_CB_CMDSIZE
, 0);
559 r300
->hw
.cb
.emit
= &emit_cb_offset
;
560 ALLOC_STATE(rb3d_dither_ctl
, always
, 10, 0);
561 r300
->hw
.rb3d_dither_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_DITHER_CTL
, 9);
562 ALLOC_STATE(rb3d_aaresolve_ctl
, always
, 2, 0);
563 r300
->hw
.rb3d_aaresolve_ctl
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_RB3D_AARESOLVE_CTL
, 1);
564 ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold
, always
, 3, 0);
565 r300
->hw
.rb3d_discard_src_pixel_lte_threshold
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
, 2);
566 ALLOC_STATE(zs
, always
, R300_ZS_CMDSIZE
, 0);
567 r300
->hw
.zs
.cmd
[R300_ZS_CMD_0
] =
568 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_CNTL
, 3);
570 ALLOC_STATE(zstencil_format
, always
, 5, 0);
571 r300
->hw
.zstencil_format
.cmd
[0] =
572 cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_FORMAT
, 4);
573 r300
->hw
.zstencil_format
.emit
= emit_zstencil_format
;
575 ALLOC_STATE(zb
, always
, R300_ZB_CMDSIZE
, 0);
576 r300
->hw
.zb
.emit
= emit_zb_offset
;
577 ALLOC_STATE(zb_depthclearvalue
, always
, 2, 0);
578 r300
->hw
.zb_depthclearvalue
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_DEPTHCLEARVALUE
, 1);
579 ALLOC_STATE(unk4F30
, always
, 3, 0);
580 r300
->hw
.unk4F30
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, 0x4F30, 2);
581 ALLOC_STATE(zb_hiz_offset
, always
, 2, 0);
582 r300
->hw
.zb_hiz_offset
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_OFFSET
, 1);
583 ALLOC_STATE(zb_hiz_pitch
, always
, 2, 0);
584 r300
->hw
.zb_hiz_pitch
.cmd
[0] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_ZB_HIZ_PITCH
, 1);
586 /* VPU only on TCL */
589 ALLOC_STATE(vpi
, vpu
, R300_VPI_CMDSIZE
, 0);
590 r300
->hw
.vpi
.cmd
[0] =
591 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CODE_START
, 0);
592 r300
->hw
.vpi
.emit
= emit_vpu
;
595 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
596 r300
->hw
.vpp
.cmd
[0] =
597 cmdvpu(r300
->radeon
.radeonScreen
, R500_PVS_CONST_START
, 0);
598 r300
->hw
.vpp
.emit
= emit_vpu
;
600 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
601 r300
->hw
.vps
.cmd
[0] =
602 cmdvpu(r300
->radeon
.radeonScreen
, R500_POINT_VPORT_SCALE_OFFSET
, 1);
603 r300
->hw
.vps
.emit
= emit_vpu
;
605 for (i
= 0; i
< 6; i
++) {
606 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
607 r300
->hw
.vpucp
[i
].cmd
[0] =
608 cmdvpu(r300
->radeon
.radeonScreen
,
609 R500_PVS_UCP_START
+ i
, 1);
610 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
613 ALLOC_STATE(vpp
, vpu
, R300_VPP_CMDSIZE
, 0);
614 r300
->hw
.vpp
.cmd
[0] =
615 cmdvpu(r300
->radeon
.radeonScreen
, R300_PVS_CONST_START
, 0);
616 r300
->hw
.vpp
.emit
= emit_vpu
;
618 ALLOC_STATE(vps
, vpu
, R300_VPS_CMDSIZE
, 0);
619 r300
->hw
.vps
.cmd
[0] =
620 cmdvpu(r300
->radeon
.radeonScreen
, R300_POINT_VPORT_SCALE_OFFSET
, 1);
621 r300
->hw
.vps
.emit
= emit_vpu
;
623 for (i
= 0; i
< 6; i
++) {
624 ALLOC_STATE(vpucp
[i
], vpu
, R300_VPUCP_CMDSIZE
, 0);
625 r300
->hw
.vpucp
[i
].cmd
[0] =
626 cmdvpu(r300
->radeon
.radeonScreen
,
627 R300_PVS_UCP_START
+ i
, 1);
628 r300
->hw
.vpucp
[i
].emit
= emit_vpu
;
634 ALLOC_STATE(tex
.filter
, variable
, mtu
+ 1, 0);
635 r300
->hw
.tex
.filter
.cmd
[R300_TEX_CMD_0
] =
636 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER0_0
, 0);
638 ALLOC_STATE(tex
.filter_1
, variable
, mtu
+ 1, 0);
639 r300
->hw
.tex
.filter_1
.cmd
[R300_TEX_CMD_0
] =
640 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FILTER1_0
, 0);
642 ALLOC_STATE(tex
.size
, variable
, mtu
+ 1, 0);
643 r300
->hw
.tex
.size
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_SIZE_0
, 0);
645 ALLOC_STATE(tex
.format
, variable
, mtu
+ 1, 0);
646 r300
->hw
.tex
.format
.cmd
[R300_TEX_CMD_0
] =
647 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT_0
, 0);
649 ALLOC_STATE(tex
.pitch
, variable
, mtu
+ 1, 0);
650 r300
->hw
.tex
.pitch
.cmd
[R300_TEX_CMD_0
] = cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_FORMAT2_0
, 0);
652 ALLOC_STATE(tex
.offset
, variable
, 1, 0);
653 r300
->hw
.tex
.offset
.cmd
[R300_TEX_CMD_0
] =
654 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_OFFSET_0
, 0);
655 r300
->hw
.tex
.offset
.emit
= &emit_tex_offsets
;
657 ALLOC_STATE(tex
.chroma_key
, variable
, mtu
+ 1, 0);
658 r300
->hw
.tex
.chroma_key
.cmd
[R300_TEX_CMD_0
] =
659 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_CHROMA_KEY_0
, 0);
661 ALLOC_STATE(tex
.border_color
, variable
, mtu
+ 1, 0);
662 r300
->hw
.tex
.border_color
.cmd
[R300_TEX_CMD_0
] =
663 cmdpacket0(r300
->radeon
.radeonScreen
, R300_TX_BORDER_COLOR_0
, 0);
665 r300
->radeon
.hw
.is_dirty
= GL_TRUE
;
666 r300
->radeon
.hw
.all_dirty
= GL_TRUE
;
668 rcommonInitCmdBuf(&r300
->radeon
);