2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * Mostly coppied from \radeon\radeon_cs_legacy.c
36 #include "main/glheader.h"
37 #include "main/state.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "swrast/swrast.h"
45 #include "radeon_drm.h"
47 #include "r600_context.h"
48 #include "radeon_reg.h"
49 #include "r600_cmdbuf.h"
50 #include "r600_emit.h"
51 #include "radeon_bocs_wrapper.h"
52 #include "radeon_mipmap_tree.h"
53 #include "radeon_reg.h"
57 static struct radeon_cs
* r600_cs_create(struct radeon_cs_manager
*csm
,
62 cs
= (struct radeon_cs
*)calloc(1, sizeof(struct radeon_cs
));
67 cs
->ndw
= (ndw
+ 0x3FF) & (~0x3FF);
68 cs
->packets
= (uint32_t*)malloc(4*cs
->ndw
);
69 if (cs
->packets
== NULL
) {
73 cs
->relocs_total_size
= 0;
77 int r600_cs_write_reloc(struct radeon_cs
*cs
,
80 uint32_t write_domain
,
82 offset_modifiers
* poffset_mod
)
84 struct r600_cs_reloc_legacy
*relocs
;
87 relocs
= (struct r600_cs_reloc_legacy
*)cs
->relocs
;
89 if ((read_domain
&& write_domain
) || (!read_domain
&& !write_domain
)) {
90 /* in one CS a bo can only be in read or write domain but not
91 * in read & write domain at the same sime
95 if (read_domain
== RADEON_GEM_DOMAIN_CPU
) {
98 if (write_domain
== RADEON_GEM_DOMAIN_CPU
) {
101 /* check if bo is already referenced */
102 for(i
= 0; i
< cs
->crelocs
; i
++) {
104 uint32_t *reloc_indices
;
106 if (relocs
[i
].base
.bo
->handle
== bo
->handle
) {
107 /* Check domains must be in read or write. As we check already
108 * checked that in argument one of the read or write domain was
109 * set we only need to check that if previous reloc as the read
110 * domain set then the read_domain should also be set for this
113 if (relocs
[i
].base
.read_domain
&& !read_domain
) {
116 if (relocs
[i
].base
.write_domain
&& !write_domain
) {
119 relocs
[i
].base
.read_domain
|= read_domain
;
120 relocs
[i
].base
.write_domain
|= write_domain
;
122 relocs
[i
].cindices
++;
123 indices
= (uint32_t*)realloc(relocs
[i
].indices
,
124 relocs
[i
].cindices
* 4);
125 reloc_indices
= (uint32_t*)realloc(relocs
[i
].reloc_indices
,
126 relocs
[i
].cindices
* 4);
127 if ( (indices
== NULL
) || (reloc_indices
== NULL
) ) {
128 relocs
[i
].cindices
-= 1;
131 relocs
[i
].indices
= indices
;
132 relocs
[i
].reloc_indices
= reloc_indices
;
133 relocs
[i
].indices
[relocs
[i
].cindices
- 1] = cs
->cdw
- 1;
134 relocs
[i
].reloc_indices
[relocs
[i
].cindices
- 1] = cs
->section_cdw
;
135 cs
->section_ndw
+= 2;
136 cs
->section_cdw
+= 2;
138 relocs
[i
].offset_mod
.shift
= poffset_mod
->shift
;
139 relocs
[i
].offset_mod
.shiftbits
= poffset_mod
->shiftbits
;
140 relocs
[i
].offset_mod
.mask
= poffset_mod
->mask
;
145 /* add bo to reloc */
146 relocs
= (struct r600_cs_reloc_legacy
*)
148 sizeof(struct r600_cs_reloc_legacy
) * (cs
->crelocs
+ 1));
149 if (relocs
== NULL
) {
153 relocs
[cs
->crelocs
].base
.bo
= bo
;
154 relocs
[cs
->crelocs
].base
.read_domain
= read_domain
;
155 relocs
[cs
->crelocs
].base
.write_domain
= write_domain
;
156 relocs
[cs
->crelocs
].base
.flags
= flags
;
157 relocs
[cs
->crelocs
].indices
= (uint32_t*)malloc(4);
158 relocs
[cs
->crelocs
].reloc_indices
= (uint32_t*)malloc(4);
159 if ( (relocs
[cs
->crelocs
].indices
== NULL
) || (relocs
[cs
->crelocs
].reloc_indices
== NULL
) )
163 relocs
[cs
->crelocs
].offset_mod
.shift
= poffset_mod
->shift
;
164 relocs
[cs
->crelocs
].offset_mod
.shiftbits
= poffset_mod
->shiftbits
;
165 relocs
[cs
->crelocs
].offset_mod
.mask
= poffset_mod
->mask
;
167 relocs
[cs
->crelocs
].indices
[0] = cs
->cdw
- 1;
168 relocs
[cs
->crelocs
].reloc_indices
[0] = cs
->section_cdw
;
169 cs
->section_ndw
+= 2;
170 cs
->section_cdw
+= 2;
171 relocs
[cs
->crelocs
].cindices
= 1;
172 cs
->relocs_total_size
+= radeon_bo_legacy_relocs_size(bo
);
180 static int r600_cs_begin(struct radeon_cs
*cs
,
187 fprintf(stderr
, "CS already in a section(%s,%s,%d)\n",
188 cs
->section_file
, cs
->section_func
, cs
->section_line
);
189 fprintf(stderr
, "CS can't start section(%s,%s,%d)\n",
194 if (cs
->cdw
+ ndw
+ 32 > cs
->ndw
) { /* Left 32 DWORD (8 offset+pitch) spare room for reloc indices */
196 int num
= (ndw
> 0x3FF) ? ndw
: 0x3FF;
198 tmp
= (cs
->cdw
+ 1 + num
) & (~num
);
199 ptr
= (uint32_t*)realloc(cs
->packets
, 4 * tmp
);
209 cs
->section_cdw
= cs
->cdw
+ ndw
; /* start of reloc indices. */
210 cs
->section_file
= file
;
211 cs
->section_func
= func
;
212 cs
->section_line
= line
;
217 static int r600_cs_end(struct radeon_cs
*cs
,
224 fprintf(stderr
, "CS no section to end at (%s,%s,%d)\n",
230 if ( (cs
->section_ndw
+ cs
->cdw
) != cs
->section_cdw
)
232 fprintf(stderr
, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
233 cs
->section_file
, cs
->section_func
, cs
->section_line
, cs
->section_ndw
, cs
->section_cdw
);
234 fprintf(stderr
, "cs->section_ndw = %d, cs->cdw = %d, cs->section_cdw = %d \n",
235 cs
->section_ndw
, cs
->cdw
, cs
->section_cdw
);
236 fprintf(stderr
, "CS section end at (%s,%s,%d)\n",
241 cs
->cdw
= cs
->section_cdw
;
245 static int r600_cs_process_relocs(struct radeon_cs
*cs
,
246 uint32_t * reloc_chunk
,
247 uint32_t * length_dw_reloc_chunk
)
249 struct r600_cs_manager_legacy
*csm
= (struct r600_cs_manager_legacy
*)cs
->csm
;
250 struct r600_cs_reloc_legacy
*relocs
;
253 uint32_t offset_dw
= 0;
255 csm
= (struct r600_cs_manager_legacy
*)cs
->csm
;
256 relocs
= (struct r600_cs_reloc_legacy
*)cs
->relocs
;
258 for (i
= 0; i
< cs
->crelocs
; i
++)
260 for (j
= 0; j
< relocs
[i
].cindices
; j
++)
262 uint32_t soffset
, eoffset
, asicoffset
;
264 r
= radeon_bo_legacy_validate(relocs
[i
].base
.bo
,
272 fprintf(stderr
, "validated %p [0x%08X, 0x%08X]\n",
273 relocs
[i
].base
.bo
, soffset
, eoffset
);
276 asicoffset
= soffset
;
277 if (asicoffset
>= eoffset
)
279 /* radeon_bo_debug(relocs[i].base.bo, 12); */
280 fprintf(stderr
, "validated %p [0x%08X, 0x%08X]\n",
281 relocs
[i
].base
.bo
, soffset
, eoffset
);
282 fprintf(stderr
, "above end: %p 0x%08X 0x%08X\n",
284 cs
->packets
[relocs
[i
].indices
[j
]],
289 /* apply offset operator */
290 switch (relocs
[i
].offset_mod
.shift
)
293 asicoffset
= asicoffset
& relocs
[i
].offset_mod
.mask
;
296 asicoffset
= (asicoffset
<< relocs
[i
].offset_mod
.shiftbits
) & relocs
[i
].offset_mod
.mask
;
299 asicoffset
= (asicoffset
>> relocs
[i
].offset_mod
.shiftbits
) & relocs
[i
].offset_mod
.mask
;
305 /* pkt3 nop header in ib chunk */
306 cs
->packets
[relocs
[i
].reloc_indices
[j
]] = 0xC0001000;
308 /* reloc index in ib chunk */
309 cs
->packets
[relocs
[i
].reloc_indices
[j
] + 1] = offset_dw
;
311 /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */
312 reloc_chunk
[offset_dw
] = asicoffset
;
313 reloc_chunk
[offset_dw
+ 3] = 0;
319 *length_dw_reloc_chunk
= offset_dw
;
324 static int r600_cs_set_age(struct radeon_cs
*cs
) /* -------------- */
326 struct r600_cs_manager_legacy
*csm
= (struct r600_cs_manager_legacy
*)cs
->csm
;
327 struct r600_cs_reloc_legacy
*relocs
;
330 relocs
= (struct r600_cs_reloc_legacy
*)cs
->relocs
;
331 for (i
= 0; i
< cs
->crelocs
; i
++) {
332 radeon_bo_legacy_pending(relocs
[i
].base
.bo
, csm
->pending_age
);
333 radeon_bo_unref(relocs
[i
].base
.bo
);
338 static void dump_cmdbuf(struct radeon_cs
*cs
)
341 fprintf(stderr
,"--start--\n");
342 for (i
= 0; i
< cs
->cdw
; i
++){
343 fprintf(stderr
,"0x%08x\n", cs
->packets
[i
]);
345 fprintf(stderr
,"--end--\n");
349 static int r600_cs_emit(struct radeon_cs
*cs
)
351 struct r600_cs_manager_legacy
*csm
= (struct r600_cs_manager_legacy
*)cs
->csm
;
352 struct drm_radeon_cs cs_cmd
;
353 struct drm_radeon_cs_chunk cs_chunk
[2];
354 drm_radeon_cmd_buffer_t cmd
;
355 /* drm_r300_cmd_header_t age; */
356 uint32_t length_dw_reloc_chunk
;
358 uint64_t chunk_ptrs
[2];
359 uint32_t reloc_chunk
[128];
363 /* TODO : put chip level things here if need. */
364 /* csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); */
366 BATCH_LOCALS(csm
->ctx
);
367 drm_radeon_getparam_t gp
;
368 uint32_t current_scratchx_age
;
370 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
371 gp
.value
= (int *)¤t_scratchx_age
;
372 r
= drmCommandWriteRead(cs
->csm
->fd
,
378 fprintf(stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
, r
);
382 csm
->pending_age
= 0;
383 csm
->pending_count
= 1;
385 current_scratchx_age
++;
386 csm
->pending_age
= current_scratchx_age
;
388 BEGIN_BATCH_NO_AUTOSTATE(3);
389 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
390 R600_OUT_BATCH((SCRATCH_REG2
- R600_SET_CONFIG_REG_OFFSET
) >> 2);
391 R600_OUT_BATCH(current_scratchx_age
);
395 //TODO ioctl to get back cs id assigned in drm
396 //csm->pending_age = cs_id_back;
398 r
= r600_cs_process_relocs(cs
, &(reloc_chunk
[0]), &length_dw_reloc_chunk
);
404 cs_chunk
[0].chunk_id
= RADEON_CHUNK_ID_IB
;
405 cs_chunk
[0].length_dw
= cs
->cdw
;
406 cs_chunk
[0].chunk_data
= (unsigned long)(cs
->packets
);
409 cs_chunk
[1].chunk_id
= RADEON_CHUNK_ID_RELOCS
;
410 cs_chunk
[1].length_dw
= length_dw_reloc_chunk
;
411 cs_chunk
[1].chunk_data
= (unsigned long)&(reloc_chunk
[0]);
413 chunk_ptrs
[0] = (uint64_t)(unsigned long)&(cs_chunk
[0]);
414 chunk_ptrs
[1] = (uint64_t)(unsigned long)&(cs_chunk
[1]);
416 cs_cmd
.num_chunks
= 2;
417 /* cs_cmd.cs_id = 0; */
418 cs_cmd
.chunks
= (uint64_t)(unsigned long)chunk_ptrs
;
424 r
= drmCommandWriteRead(cs
->csm
->fd
, DRM_RADEON_CS
, &cs_cmd
, sizeof(cs_cmd
));
426 } while (r
== -EAGAIN
&& retry
< 1000);
434 cs
->csm
->read_used
= 0;
435 cs
->csm
->vram_write_used
= 0;
436 cs
->csm
->gart_write_used
= 0;
441 static void inline r600_cs_free_reloc(void *relocs_p
, int crelocs
)
443 struct r600_cs_reloc_legacy
*relocs
= relocs_p
;
447 for (i
= 0; i
< crelocs
; i
++)
449 free(relocs
[i
].indices
);
450 free(relocs
[i
].reloc_indices
);
454 static int r600_cs_destroy(struct radeon_cs
*cs
)
456 r600_cs_free_reloc(cs
->relocs
, cs
->crelocs
);
463 static int r600_cs_erase(struct radeon_cs
*cs
)
465 r600_cs_free_reloc(cs
->relocs
, cs
->crelocs
);
467 cs
->relocs_total_size
= 0;
475 static int r600_cs_need_flush(struct radeon_cs
*cs
)
477 /* this function used to flush when the BO usage got to
478 * a certain size, now the higher levels handle this better */
482 static void r600_cs_print(struct radeon_cs
*cs
, FILE *file
)
486 static struct radeon_cs_funcs r600_cs_funcs
= {
498 struct radeon_cs_manager
* r600_radeon_cs_manager_legacy_ctor(struct radeon_context
*ctx
)
500 struct r600_cs_manager_legacy
*csm
;
502 csm
= (struct r600_cs_manager_legacy
*)
503 calloc(1, sizeof(struct r600_cs_manager_legacy
));
507 csm
->base
.funcs
= &r600_cs_funcs
;
508 csm
->base
.fd
= ctx
->dri
.fd
;
510 csm
->pending_age
= 1;
511 return (struct radeon_cs_manager
*)csm
;
514 void r600InitCmdBuf(context_t
*r600
) /* from rcommonInitCmdBuf */
516 radeonContextPtr rmesa
= &r600
->radeon
;
519 /* Initialize command buffer */
520 size
= 256 * driQueryOptioni(&rmesa
->optionCache
,
521 "command_buffer_size");
522 if (size
< 2 * rmesa
->hw
.max_state_size
) {
523 size
= 2 * rmesa
->hw
.max_state_size
+ 65535;
528 if (rmesa
->radeonScreen
->kernel_mm
) {
529 int fd
= rmesa
->radeonScreen
->driScreen
->fd
;
530 rmesa
->cmdbuf
.csm
= radeon_cs_manager_gem_ctor(fd
);
532 rmesa
->cmdbuf
.csm
= r600_radeon_cs_manager_legacy_ctor(rmesa
);
534 if (rmesa
->cmdbuf
.csm
== NULL
) {
535 /* FIXME: fatal error */
538 rmesa
->cmdbuf
.cs
= radeon_cs_create(rmesa
->cmdbuf
.csm
, size
);
539 assert(rmesa
->cmdbuf
.cs
!= NULL
);
540 rmesa
->cmdbuf
.size
= size
;
542 if (!rmesa
->radeonScreen
->kernel_mm
) {
543 radeon_cs_set_limit(rmesa
->cmdbuf
.cs
, RADEON_GEM_DOMAIN_VRAM
, rmesa
->radeonScreen
->texSize
[0]);
544 radeon_cs_set_limit(rmesa
->cmdbuf
.cs
, RADEON_GEM_DOMAIN_GTT
, rmesa
->radeonScreen
->gartTextures
.size
);
546 struct drm_radeon_gem_info mminfo
;
548 if (!drmCommandWriteRead(rmesa
->dri
.fd
, DRM_RADEON_GEM_INFO
, &mminfo
, sizeof(mminfo
)))
550 radeon_cs_set_limit(rmesa
->cmdbuf
.cs
, RADEON_GEM_DOMAIN_VRAM
, mminfo
.vram_visible
);
551 radeon_cs_set_limit(rmesa
->cmdbuf
.cs
, RADEON_GEM_DOMAIN_GTT
, mminfo
.gart_size
);