evergreen : initial support driver code.
[mesa.git] / src / mesa / drivers / dri / r600 / r600_context.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Keith Whitwell <keith@tungstengraphics.com>
34 *
35 * \author Nicolai Haehnle <prefect_@gmx.net>
36 */
37
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/extensions.h"
44 #include "main/bufferobj.h"
45 #include "main/texobj.h"
46
47 #include "swrast/swrast.h"
48 #include "swrast_setup/swrast_setup.h"
49 #include "vbo/vbo.h"
50
51 #include "tnl/tnl.h"
52 #include "tnl/t_pipeline.h"
53
54 #include "drivers/common/driverfuncs.h"
55
56 #include "radeon_debug.h"
57 #include "r600_context.h"
58 #include "radeon_common_context.h"
59 #include "radeon_buffer_objects.h"
60 #include "radeon_span.h"
61 #include "r600_cmdbuf.h"
62 #include "radeon_bocs_wrapper.h"
63 #include "radeon_queryobj.h"
64 #include "r600_blit.h"
65
66 #include "r700_state.h"
67 #include "r700_ioctl.h"
68
69 #include "evergreen_context.h"
70 #include "evergreen_state.h"
71 #include "evergreen_tex.h"
72 #include "evergreen_ioctl.h"
73 #include "evergreen_oglprog.h"
74
75 #include "utils.h"
76
77 #define R600_ENABLE_GLSL_TEST 1
78
79 #define need_GL_VERSION_2_0
80 #define need_GL_VERSION_2_1
81 #define need_GL_ARB_draw_elements_base_vertex
82 #define need_GL_ARB_occlusion_query
83 #define need_GL_ARB_point_parameters
84 #define need_GL_ARB_vertex_program
85 #define need_GL_EXT_blend_equation_separate
86 #define need_GL_EXT_blend_func_separate
87 #define need_GL_EXT_blend_minmax
88 #define need_GL_EXT_framebuffer_object
89 #define need_GL_EXT_fog_coord
90 #define need_GL_EXT_gpu_program_parameters
91 #define need_GL_EXT_provoking_vertex
92 #define need_GL_EXT_secondary_color
93 #define need_GL_EXT_stencil_two_side
94 #define need_GL_ATI_separate_stencil
95 #define need_GL_NV_vertex_program
96
97 #include "main/remap_helper.h"
98
99 static const struct dri_extension card_extensions[] = {
100 /* *INDENT-OFF* */
101 {"GL_ARB_depth_clamp", NULL},
102 {"GL_ARB_depth_texture", NULL},
103 {"GL_ARB_fragment_program", NULL},
104 {"GL_ARB_fragment_program_shadow", NULL},
105 {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions},
106 {"GL_ARB_multitexture", NULL},
107 {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions},
108 {"GL_ARB_shadow", NULL},
109 {"GL_ARB_shadow_ambient", NULL},
110 {"GL_ARB_texture_border_clamp", NULL},
111 {"GL_ARB_texture_cube_map", NULL},
112 {"GL_ARB_texture_env_add", NULL},
113 {"GL_ARB_texture_env_combine", NULL},
114 {"GL_ARB_texture_env_crossbar", NULL},
115 {"GL_ARB_texture_env_dot3", NULL},
116 {"GL_ARB_texture_mirrored_repeat", NULL},
117 {"GL_ARB_texture_non_power_of_two", NULL},
118 {"GL_ARB_vertex_program", GL_ARB_vertex_program_functions},
119 {"GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions},
120 {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions},
121 {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions},
122 {"GL_EXT_blend_subtract", NULL},
123 {"GL_EXT_packed_depth_stencil", NULL},
124 {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
125 {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions},
126 {"GL_EXT_provoking_vertex", GL_EXT_provoking_vertex_functions },
127 {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions},
128 {"GL_EXT_shadow_funcs", NULL},
129 {"GL_EXT_stencil_two_side", GL_EXT_stencil_two_side_functions},
130 {"GL_EXT_stencil_wrap", NULL},
131 {"GL_EXT_texture_edge_clamp", NULL},
132 {"GL_EXT_texture_env_combine", NULL},
133 {"GL_EXT_texture_env_dot3", NULL},
134 {"GL_EXT_texture_filter_anisotropic", NULL},
135 {"GL_EXT_texture_lod_bias", NULL},
136 {"GL_EXT_texture_mirror_clamp", NULL},
137 {"GL_EXT_texture_rectangle", NULL},
138 {"GL_EXT_vertex_array_bgra", NULL},
139 {"GL_EXT_texture_sRGB", NULL},
140 {"GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions},
141 {"GL_ATI_texture_env_combine3", NULL},
142 {"GL_ATI_texture_mirror_once", NULL},
143 {"GL_MESA_pack_invert", NULL},
144 {"GL_MESA_ycbcr_texture", NULL},
145 {"GL_MESAX_texture_float", NULL},
146 {"GL_NV_blend_square", NULL},
147 {"GL_NV_vertex_program", GL_NV_vertex_program_functions},
148 {"GL_SGIS_generate_mipmap", NULL},
149 {"GL_ARB_pixel_buffer_object", NULL},
150 {"GL_ARB_draw_elements_base_vertex", GL_ARB_draw_elements_base_vertex_functions },
151 {NULL, NULL}
152 /* *INDENT-ON* */
153 };
154
155
156 static const struct dri_extension mm_extensions[] = {
157 { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
158 { NULL, NULL }
159 };
160
161 /**
162 * The GL 2.0 functions are needed to make display lists work with
163 * functions added by GL_ATI_separate_stencil.
164 */
165 static const struct dri_extension gl_20_extension[] = {
166 #ifdef R600_ENABLE_GLSL_TEST
167 {"GL_ARB_shading_language_100", GL_VERSION_2_0_functions },
168 {"GL_ARB_shading_language_120", GL_VERSION_2_1_functions },
169 #else
170 {"GL_VERSION_2_0", GL_VERSION_2_0_functions },
171 #endif /* R600_ENABLE_GLSL_TEST */
172 {NULL, NULL}
173 };
174
175 static const struct tnl_pipeline_stage *r600_pipeline[] = {
176 /* Catch any t&l fallbacks
177 */
178 &_tnl_vertex_transform_stage,
179 &_tnl_normal_transform_stage,
180 &_tnl_lighting_stage,
181 &_tnl_fog_coordinate_stage,
182 &_tnl_texgen_stage,
183 &_tnl_texture_transform_stage,
184 &_tnl_point_attenuation_stage,
185 &_tnl_vertex_program_stage,
186 &_tnl_render_stage,
187 0,
188 };
189
190 static void r600_get_lock(radeonContextPtr rmesa)
191 {
192 drm_radeon_sarea_t *sarea = rmesa->sarea;
193
194 if (sarea->ctx_owner != rmesa->dri.hwContext) {
195 sarea->ctx_owner = rmesa->dri.hwContext;
196 if (!rmesa->radeonScreen->kernel_mm)
197 radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
198 }
199 }
200
201 static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
202 {
203 /* please flush pipe do all pending work */
204 /* to be enabled */
205 }
206
207 static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon)
208 {
209 r700Start3D((context_t *)radeon);
210 }
211
212 static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
213 {
214 context_t *context = R700_CONTEXT(ctx);
215 if (mode)
216 context->radeon.Fallback |= bit;
217 else
218 context->radeon.Fallback &= ~bit;
219 }
220
221 static void r600_emit_query_finish(radeonContextPtr radeon)
222 {
223 context_t *context = (context_t*) radeon;
224 BATCH_LOCALS(&context->radeon);
225
226 struct radeon_query_object *query = radeon->query.current;
227
228 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
229 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
230 R600_OUT_BATCH(ZPASS_DONE);
231 R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
232 R600_OUT_BATCH(0x00000000);
233 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
234 END_BATCH();
235 assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
236 query->emitted_begin = GL_FALSE;
237 }
238
239 static void r600_init_vtbl(radeonContextPtr radeon)
240 {
241 radeon->vtbl.get_lock = r600_get_lock;
242 radeon->vtbl.update_viewport_offset = r700UpdateViewportOffset;
243 radeon->vtbl.emit_cs_header = r600_vtbl_emit_cs_header;
244 radeon->vtbl.swtcl_flush = NULL;
245 radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms;
246 radeon->vtbl.fallback = r600_fallback;
247 radeon->vtbl.emit_query_finish = r600_emit_query_finish;
248 radeon->vtbl.check_blit = r600_check_blit;
249 radeon->vtbl.blit = r600_blit;
250 radeon->vtbl.is_format_renderable = r600IsFormatRenderable;
251 }
252
253 static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
254 {
255 context_t *context = R700_CONTEXT(ctx);
256 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
257
258 if( (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
259 &&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_HEMLOCK) )
260 {
261 r700->bShaderUseMemConstant = GL_TRUE;
262 }
263 else
264 {
265 r700->bShaderUseMemConstant = GL_FALSE;
266 }
267
268 ctx->Const.MaxTextureImageUnits = 16;
269 /* 8 per clause on r6xx, 16 on r7xx
270 * but I think mesa only supports 8 at the moment
271 */
272 ctx->Const.MaxTextureCoordUnits = 8;
273 ctx->Const.MaxTextureUnits =
274 MIN2(ctx->Const.MaxTextureImageUnits,
275 ctx->Const.MaxTextureCoordUnits);
276 ctx->Const.MaxCombinedTextureImageUnits =
277 ctx->Const.MaxVertexTextureImageUnits +
278 ctx->Const.MaxTextureImageUnits;
279
280 ctx->Const.MaxTextureMaxAnisotropy = 16.0;
281 ctx->Const.MaxTextureLodBias = 16.0;
282
283 ctx->Const.MaxTextureLevels = 13; /* hw support 14 */
284 ctx->Const.MaxTextureRectSize = 4096; /* hw support 8192 */
285
286 ctx->Const.MinPointSize = 0x0001 / 8.0;
287 ctx->Const.MinPointSizeAA = 0x0001 / 8.0;
288 ctx->Const.MaxPointSize = 0xffff / 8.0;
289 ctx->Const.MaxPointSizeAA = 0xffff / 8.0;
290
291 ctx->Const.MinLineWidth = 0x0001 / 8.0;
292 ctx->Const.MinLineWidthAA = 0x0001 / 8.0;
293 ctx->Const.MaxLineWidth = 0xffff / 8.0;
294 ctx->Const.MaxLineWidthAA = 0xffff / 8.0;
295
296 ctx->Const.MaxDrawBuffers = 1; /* hw supports 8 */
297 ctx->Const.MaxColorAttachments = 1;
298 ctx->Const.MaxRenderbufferSize = 4096;
299
300 /* 256 for reg-based consts, inline consts also supported */
301 ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */
302 ctx->Const.VertexProgram.MaxNativeInstructions = 8192;
303 ctx->Const.VertexProgram.MaxNativeAttribs = 160;
304 ctx->Const.VertexProgram.MaxTemps = 128;
305 ctx->Const.VertexProgram.MaxNativeTemps = 128;
306 ctx->Const.VertexProgram.MaxNativeParameters = 256;
307 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */
308
309 ctx->Const.FragmentProgram.MaxNativeTemps = 128;
310 ctx->Const.FragmentProgram.MaxNativeAttribs = 32;
311 ctx->Const.FragmentProgram.MaxNativeParameters = 256;
312 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192;
313 /* 8 per clause on r6xx, 16 on r7xx */
314 if (screen->chip_family >= CHIP_FAMILY_RV770)
315 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 16;
316 else
317 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 8;
318 ctx->Const.FragmentProgram.MaxNativeInstructions = 8192;
319 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 8; /* ??? */
320 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; /* and these are?? */
321 }
322
323 static void r600ParseOptions(context_t *r600, radeonScreenPtr screen)
324 {
325 /* Parse configuration files.
326 * Do this here so that initialMaxAnisotropy is set before we create
327 * the default textures.
328 */
329 driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache,
330 screen->driScreen->myNum, "r600");
331
332 r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache,
333 "def_max_anisotropy");
334
335 }
336
337 static void r600InitGLExtensions(GLcontext *ctx)
338 {
339 context_t *r600 = R700_CONTEXT(ctx);
340
341 driInitExtensions(ctx, card_extensions, GL_TRUE);
342 if (r600->radeon.radeonScreen->kernel_mm)
343 driInitExtensions(ctx, mm_extensions, GL_FALSE);
344
345 #ifdef R600_ENABLE_GLSL_TEST
346 driInitExtensions(ctx, gl_20_extension, GL_TRUE);
347 _mesa_enable_2_0_extensions(ctx);
348
349 /* glsl compiler has problem if this is not GL_TRUE */
350 ctx->Shader.EmitCondCodes = GL_TRUE;
351 #endif /* R600_ENABLE_GLSL_TEST */
352
353 if (driQueryOptionb
354 (&r600->radeon.optionCache, "disable_stencil_two_side"))
355 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
356
357 if (r600->radeon.glCtx->Mesa_DXTn
358 && !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) {
359 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
360 _mesa_enable_extension(ctx, "GL_S3_s3tc");
361 } else
362 if (driQueryOptionb(&r600->radeon.optionCache, "force_s3tc_enable"))
363 {
364 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
365 }
366
367 /* RV740 had a broken pipe config prior to drm 1.32 */
368 if (!r600->radeon.radeonScreen->kernel_mm) {
369 if ((r600->radeon.dri.drmMinor < 32) &&
370 (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV740))
371 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
372 }
373 }
374
375 /* Create the device specific rendering context.
376 */
377 GLboolean r600CreateContext(gl_api api,
378 const __GLcontextModes * glVisual,
379 __DRIcontext * driContextPriv,
380 void *sharedContextPrivate)
381 {
382 __DRIscreen *sPriv = driContextPriv->driScreenPriv;
383 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
384 struct dd_function_table functions;
385 context_t *r600;
386 GLcontext *ctx;
387
388 assert(glVisual);
389 assert(driContextPriv);
390 assert(screen);
391
392 /* Allocate the R600 context */
393 r600 = (context_t*) CALLOC(sizeof(*r600));
394 if (!r600) {
395 radeon_error("Failed to allocate memory for context.\n");
396 return GL_FALSE;
397 }
398
399 r600ParseOptions(r600, screen);
400
401 r600->radeon.radeonScreen = screen;
402
403 if(screen->chip_family >= CHIP_FAMILY_CEDAR)
404 {
405 evergreen_init_vtbl(&r600->radeon);
406 }
407 else
408 {
409 r600_init_vtbl(&r600->radeon);
410 }
411
412 /* Init default driver functions then plug in our R600-specific functions
413 * (the texture functions are especially important)
414 */
415 _mesa_init_driver_functions(&functions);
416
417 if(screen->chip_family >= CHIP_FAMILY_CEDAR)
418 {
419 evergreenCreateChip(r600);
420 evergreenInitStateFuncs(&r600->radeon, &functions);
421 evergreenInitTextureFuncs(&r600->radeon, &functions);
422 evergreenInitShaderFuncs(&functions);
423 }
424 else
425 {
426 r700InitStateFuncs(&r600->radeon, &functions);
427 r600InitTextureFuncs(&r600->radeon, &functions);
428 r700InitShaderFuncs(&functions);
429 }
430
431 radeonInitQueryObjFunctions(&functions);
432
433 if(screen->chip_family >= CHIP_FAMILY_CEDAR)
434 {
435 evergreenInitIoctlFuncs(&functions);
436 }
437 else
438 {
439 r700InitIoctlFuncs(&functions);
440 }
441 radeonInitBufferObjectFuncs(&functions);
442
443 if (!radeonInitContext(&r600->radeon, &functions,
444 glVisual, driContextPriv,
445 sharedContextPrivate)) {
446 radeon_error("Initializing context failed.\n");
447 FREE(r600);
448 return GL_FALSE;
449 }
450
451 ctx = r600->radeon.glCtx;
452
453 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
454 ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
455
456 r600InitConstValues(ctx, screen);
457
458 _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
459
460 /* Initialize the software rasterizer and helper modules.
461 */
462 _swrast_CreateContext(ctx);
463 _vbo_CreateContext(ctx);
464 _tnl_CreateContext(ctx);
465 _swsetup_CreateContext(ctx);
466 _swsetup_Wakeup(ctx);
467
468 /* Install the customized pipeline:
469 */
470 _tnl_destroy_pipeline(ctx);
471 _tnl_install_pipeline(ctx, r600_pipeline);
472 TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
473
474 /* Configure swrast and TNL to match hardware characteristics:
475 */
476 _swrast_allow_pixel_fog(ctx, GL_FALSE);
477 _swrast_allow_vertex_fog(ctx, GL_TRUE);
478 _tnl_allow_pixel_fog(ctx, GL_FALSE);
479 _tnl_allow_vertex_fog(ctx, GL_TRUE);
480
481 radeon_init_debug();
482
483 if(screen->chip_family >= CHIP_FAMILY_CEDAR)
484 {
485 evergreenInitDraw(ctx);
486 }
487 else
488 {
489 r700InitDraw(ctx);
490 }
491
492 radeon_fbo_init(&r600->radeon);
493 radeonInitSpanFuncs( ctx );
494 r600InitCmdBuf(r600);
495
496 if(screen->chip_family >= CHIP_FAMILY_CEDAR)
497 {
498 evergreenInitState(r600->radeon.glCtx);
499 }
500 else
501 {
502 r700InitState(r600->radeon.glCtx);
503 }
504
505 r600InitGLExtensions(ctx);
506
507 return GL_TRUE;
508 }
509
510 void r600DestroyContext(__DRIcontext *driContextPriv )
511 {
512 void *pChip;
513 context_t *context = (context_t *) driContextPriv->driverPrivate;
514
515 assert(context);
516
517 pChip = context->pChip;
518
519 /* destroy context first, free pChip, in case there are things flush to asic. */
520 radeonDestroyContext(driContextPriv);
521
522 FREE(pChip);
523 }
524
525