Merge branch 'mesa_7_6_branch' into mesa_7_7_branch
[mesa.git] / src / mesa / drivers / dri / r600 / r600_context.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Keith Whitwell <keith@tungstengraphics.com>
34 *
35 * \author Nicolai Haehnle <prefect_@gmx.net>
36 */
37
38 #include "main/glheader.h"
39 #include "main/api_arrayelt.h"
40 #include "main/context.h"
41 #include "main/simple_list.h"
42 #include "main/imports.h"
43 #include "main/matrix.h"
44 #include "main/extensions.h"
45 #include "main/state.h"
46 #include "main/bufferobj.h"
47 #include "main/texobj.h"
48
49 #include "swrast/swrast.h"
50 #include "swrast_setup/swrast_setup.h"
51 #include "vbo/vbo.h"
52
53 #include "tnl/tnl.h"
54 #include "tnl/t_pipeline.h"
55 #include "tnl/t_vp_build.h"
56
57 #include "drivers/common/driverfuncs.h"
58
59 #include "radeon_debug.h"
60 #include "r600_context.h"
61 #include "radeon_common_context.h"
62 #include "radeon_buffer_objects.h"
63 #include "radeon_span.h"
64 #include "r600_cmdbuf.h"
65 #include "r600_emit.h"
66 #include "radeon_bocs_wrapper.h"
67 #include "radeon_queryobj.h"
68
69 #include "r700_state.h"
70 #include "r700_ioctl.h"
71
72
73 #include "vblank.h"
74 #include "utils.h"
75 #include "xmlpool.h" /* for symbolic values of enum-type options */
76
77 #define need_GL_VERSION_2_0
78 #define need_GL_ARB_occlusion_query
79 #define need_GL_ARB_point_parameters
80 #define need_GL_ARB_vertex_program
81 #define need_GL_EXT_blend_equation_separate
82 #define need_GL_EXT_blend_func_separate
83 #define need_GL_EXT_blend_minmax
84 #define need_GL_EXT_framebuffer_object
85 #define need_GL_EXT_fog_coord
86 #define need_GL_EXT_gpu_program_parameters
87 #define need_GL_EXT_provoking_vertex
88 #define need_GL_EXT_secondary_color
89 #define need_GL_EXT_stencil_two_side
90 #define need_GL_ATI_separate_stencil
91 #define need_GL_NV_vertex_program
92
93 #include "main/remap_helper.h"
94
95 static const struct dri_extension card_extensions[] = {
96 /* *INDENT-OFF* */
97 {"GL_ARB_depth_clamp", NULL},
98 {"GL_ARB_depth_texture", NULL},
99 {"GL_ARB_fragment_program", NULL},
100 {"GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions},
101 {"GL_ARB_multitexture", NULL},
102 {"GL_ARB_point_parameters", GL_ARB_point_parameters_functions},
103 {"GL_ARB_shadow", NULL},
104 {"GL_ARB_shadow_ambient", NULL},
105 {"GL_ARB_texture_border_clamp", NULL},
106 {"GL_ARB_texture_cube_map", NULL},
107 {"GL_ARB_texture_env_add", NULL},
108 {"GL_ARB_texture_env_combine", NULL},
109 {"GL_ARB_texture_env_crossbar", NULL},
110 {"GL_ARB_texture_env_dot3", NULL},
111 {"GL_ARB_texture_mirrored_repeat", NULL},
112 {"GL_ARB_vertex_program", GL_ARB_vertex_program_functions},
113 {"GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions},
114 {"GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions},
115 {"GL_EXT_blend_minmax", GL_EXT_blend_minmax_functions},
116 {"GL_EXT_blend_subtract", NULL},
117 {"GL_EXT_packed_depth_stencil", NULL},
118 {"GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
119 {"GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions},
120 {"GL_EXT_provoking_vertex", GL_EXT_provoking_vertex_functions },
121 {"GL_EXT_secondary_color", GL_EXT_secondary_color_functions},
122 {"GL_EXT_shadow_funcs", NULL},
123 {"GL_EXT_stencil_two_side", GL_EXT_stencil_two_side_functions},
124 {"GL_EXT_stencil_wrap", NULL},
125 {"GL_EXT_texture_edge_clamp", NULL},
126 {"GL_EXT_texture_env_combine", NULL},
127 {"GL_EXT_texture_env_dot3", NULL},
128 {"GL_EXT_texture_filter_anisotropic", NULL},
129 {"GL_EXT_texture_lod_bias", NULL},
130 {"GL_EXT_texture_mirror_clamp", NULL},
131 {"GL_EXT_texture_rectangle", NULL},
132 {"GL_EXT_vertex_array_bgra", NULL},
133 {"GL_EXT_texture_sRGB", NULL},
134 {"GL_ATI_separate_stencil", GL_ATI_separate_stencil_functions},
135 {"GL_ATI_texture_env_combine3", NULL},
136 {"GL_ATI_texture_mirror_once", NULL},
137 {"GL_MESA_pack_invert", NULL},
138 {"GL_MESA_ycbcr_texture", NULL},
139 {"GL_MESAX_texture_float", NULL},
140 {"GL_NV_blend_square", NULL},
141 {"GL_NV_vertex_program", GL_NV_vertex_program_functions},
142 {"GL_SGIS_generate_mipmap", NULL},
143 {NULL, NULL}
144 /* *INDENT-ON* */
145 };
146
147
148 static const struct dri_extension mm_extensions[] = {
149 { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
150 { NULL, NULL }
151 };
152
153 /**
154 * The GL 2.0 functions are needed to make display lists work with
155 * functions added by GL_ATI_separate_stencil.
156 */
157 static const struct dri_extension gl_20_extension[] = {
158 {"GL_VERSION_2_0", GL_VERSION_2_0_functions },
159 };
160
161 static const struct tnl_pipeline_stage *r600_pipeline[] = {
162 /* Catch any t&l fallbacks
163 */
164 &_tnl_vertex_transform_stage,
165 &_tnl_normal_transform_stage,
166 &_tnl_lighting_stage,
167 &_tnl_fog_coordinate_stage,
168 &_tnl_texgen_stage,
169 &_tnl_texture_transform_stage,
170 &_tnl_point_attenuation_stage,
171 &_tnl_vertex_program_stage,
172 &_tnl_render_stage,
173 0,
174 };
175
176 static void r600_get_lock(radeonContextPtr rmesa)
177 {
178 drm_radeon_sarea_t *sarea = rmesa->sarea;
179
180 if (sarea->ctx_owner != rmesa->dri.hwContext) {
181 sarea->ctx_owner = rmesa->dri.hwContext;
182 if (!rmesa->radeonScreen->kernel_mm)
183 radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
184 }
185 }
186
187 static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
188 {
189 /* please flush pipe do all pending work */
190 /* to be enabled */
191 }
192
193 static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon)
194 {
195 r700Start3D((context_t *)radeon);
196 }
197
198 static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
199 {
200 context_t *context = R700_CONTEXT(ctx);
201 if (mode)
202 context->radeon.Fallback |= bit;
203 else
204 context->radeon.Fallback &= ~bit;
205 }
206
207 static void r600_emit_query_finish(radeonContextPtr radeon)
208 {
209 context_t *context = (context_t*) radeon;
210 BATCH_LOCALS(&context->radeon);
211
212 struct radeon_query_object *query = radeon->query.current;
213
214 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
215 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
216 R600_OUT_BATCH(ZPASS_DONE);
217 R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
218 R600_OUT_BATCH(0x00000000);
219 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
220 END_BATCH();
221 assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
222 query->emitted_begin = GL_FALSE;
223 }
224
225 static void r600_init_vtbl(radeonContextPtr radeon)
226 {
227 radeon->vtbl.get_lock = r600_get_lock;
228 radeon->vtbl.update_viewport_offset = r700UpdateViewportOffset;
229 radeon->vtbl.emit_cs_header = r600_vtbl_emit_cs_header;
230 radeon->vtbl.swtcl_flush = NULL;
231 radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms;
232 radeon->vtbl.fallback = r600_fallback;
233 radeon->vtbl.emit_query_finish = r600_emit_query_finish;
234 }
235
236 static void r600InitConstValues(GLcontext *ctx, radeonScreenPtr screen)
237 {
238 context_t *r600 = R700_CONTEXT(ctx);
239
240 ctx->Const.MaxTextureImageUnits =
241 driQueryOptioni(&r600->radeon.optionCache, "texture_image_units");
242 ctx->Const.MaxTextureCoordUnits =
243 driQueryOptioni(&r600->radeon.optionCache, "texture_coord_units");
244 ctx->Const.MaxTextureUnits =
245 MIN2(ctx->Const.MaxTextureImageUnits,
246 ctx->Const.MaxTextureCoordUnits);
247 ctx->Const.MaxTextureMaxAnisotropy = 16.0;
248 ctx->Const.MaxTextureLodBias = 16.0;
249
250 ctx->Const.MaxTextureLevels = 13; /* hw support 14 */
251 ctx->Const.MaxTextureRectSize = 4096; /* hw support 8192 */
252
253 ctx->Const.MinPointSize = 0x0001 / 8.0;
254 ctx->Const.MinPointSizeAA = 0x0001 / 8.0;
255 ctx->Const.MaxPointSize = 0xffff / 8.0;
256 ctx->Const.MaxPointSizeAA = 0xffff / 8.0;
257
258 ctx->Const.MinLineWidth = 0x0001 / 8.0;
259 ctx->Const.MinLineWidthAA = 0x0001 / 8.0;
260 ctx->Const.MaxLineWidth = 0xffff / 8.0;
261 ctx->Const.MaxLineWidthAA = 0xffff / 8.0;
262
263 ctx->Const.MaxDrawBuffers = 1; /* hw supports 8 */
264
265 /* 256 for reg-based consts, inline consts also supported */
266 ctx->Const.VertexProgram.MaxInstructions = 8192; /* in theory no limit */
267 ctx->Const.VertexProgram.MaxNativeInstructions = 8192;
268 ctx->Const.VertexProgram.MaxNativeAttribs = 160;
269 ctx->Const.VertexProgram.MaxTemps = 128;
270 ctx->Const.VertexProgram.MaxNativeTemps = 128;
271 ctx->Const.VertexProgram.MaxNativeParameters = 256;
272 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1; /* ??? */
273
274 ctx->Const.FragmentProgram.MaxNativeTemps = 128;
275 ctx->Const.FragmentProgram.MaxNativeAttribs = 32;
276 ctx->Const.FragmentProgram.MaxNativeParameters = 256;
277 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 8192;
278 /* 8 per clause on r6xx, 16 on rv670/r7xx */
279 if ((screen->chip_family == CHIP_FAMILY_RV670) ||
280 (screen->chip_family >= CHIP_FAMILY_RV770))
281 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 16;
282 else
283 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 8;
284 ctx->Const.FragmentProgram.MaxNativeInstructions = 8192;
285 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 8; /* ??? */
286 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0; /* and these are?? */
287 }
288
289 static void r600ParseOptions(context_t *r600, radeonScreenPtr screen)
290 {
291 /* Parse configuration files.
292 * Do this here so that initialMaxAnisotropy is set before we create
293 * the default textures.
294 */
295 driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache,
296 screen->driScreen->myNum, "r600");
297
298 r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache,
299 "def_max_anisotropy");
300
301 }
302
303 static void r600InitGLExtensions(GLcontext *ctx)
304 {
305 context_t *r600 = R700_CONTEXT(ctx);
306
307 driInitExtensions(ctx, card_extensions, GL_TRUE);
308 if (r600->radeon.radeonScreen->kernel_mm)
309 driInitExtensions(ctx, mm_extensions, GL_FALSE);
310
311 if (driQueryOptionb
312 (&r600->radeon.optionCache, "disable_stencil_two_side"))
313 _mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
314
315 if (r600->radeon.glCtx->Mesa_DXTn
316 && !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) {
317 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
318 _mesa_enable_extension(ctx, "GL_S3_s3tc");
319 } else
320 if (driQueryOptionb(&r600->radeon.optionCache, "force_s3tc_enable"))
321 {
322 _mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
323 }
324
325 /* XXX: RV740 only seems to report results from half of its DBs */
326 if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV740)
327 _mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
328 }
329
330 /* Create the device specific rendering context.
331 */
332 GLboolean r600CreateContext(const __GLcontextModes * glVisual,
333 __DRIcontextPrivate * driContextPriv,
334 void *sharedContextPrivate)
335 {
336 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
337 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
338 struct dd_function_table functions;
339 context_t *r600;
340 GLcontext *ctx;
341
342 assert(glVisual);
343 assert(driContextPriv);
344 assert(screen);
345
346 /* Allocate the R600 context */
347 r600 = (context_t*) CALLOC(sizeof(*r600));
348 if (!r600) {
349 radeon_error("Failed to allocate memory for context.\n");
350 return GL_FALSE;
351 }
352
353 r600ParseOptions(r600, screen);
354
355 r600->radeon.radeonScreen = screen;
356 r600_init_vtbl(&r600->radeon);
357
358 /* Init default driver functions then plug in our R600-specific functions
359 * (the texture functions are especially important)
360 */
361 _mesa_init_driver_functions(&functions);
362
363 r700InitStateFuncs(&functions);
364 r600InitTextureFuncs(&functions);
365 r700InitShaderFuncs(&functions);
366 radeonInitQueryObjFunctions(&functions);
367 r700InitIoctlFuncs(&functions);
368 radeonInitBufferObjectFuncs(&functions);
369
370 if (!radeonInitContext(&r600->radeon, &functions,
371 glVisual, driContextPriv,
372 sharedContextPrivate)) {
373 radeon_error("Initializing context failed.\n");
374 FREE(r600);
375 return GL_FALSE;
376 }
377
378 ctx = r600->radeon.glCtx;
379
380 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
381 ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
382
383 r600InitConstValues(ctx, screen);
384
385 _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
386
387 /* Initialize the software rasterizer and helper modules.
388 */
389 _swrast_CreateContext(ctx);
390 _vbo_CreateContext(ctx);
391 _tnl_CreateContext(ctx);
392 _swsetup_CreateContext(ctx);
393 _swsetup_Wakeup(ctx);
394
395 /* Install the customized pipeline:
396 */
397 _tnl_destroy_pipeline(ctx);
398 _tnl_install_pipeline(ctx, r600_pipeline);
399 TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
400
401 /* Configure swrast and TNL to match hardware characteristics:
402 */
403 _swrast_allow_pixel_fog(ctx, GL_FALSE);
404 _swrast_allow_vertex_fog(ctx, GL_TRUE);
405 _tnl_allow_pixel_fog(ctx, GL_FALSE);
406 _tnl_allow_vertex_fog(ctx, GL_TRUE);
407
408 radeon_init_debug();
409
410 r700InitDraw(ctx);
411
412 radeon_fbo_init(&r600->radeon);
413 radeonInitSpanFuncs( ctx );
414 r600InitCmdBuf(r600);
415 r700InitState(r600->radeon.glCtx);
416
417 r600InitGLExtensions(ctx);
418
419 return GL_TRUE;
420 }
421
422