src/mesa/drivers/dri/r600/r600_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R600_CONTEXT_H__
  38 #define __R600_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_common.h"
  46
  47 #include "main/macros.h"
  48 #include "main/mtypes.h"
  49 #include "main/colormac.h"
  50
  51 #include "r700_chip.h"
  52 #include "r600_tex.h"
  53 #include "r700_oglprog.h"
  54 #include "r700_vertprog.h"
  55
  56 struct r600_context;
  57 typedef struct r600_context context_t;
  58
  59 #include "main/mm.h"
  60
  61 /************ DMA BUFFERS **************/
  62
  63 /* The blit width for texture uploads
  64  */
  65 #define R600_BLIT_WIDTH_BYTES 1024
  66 #define R600_MAX_TEXTURE_UNITS 8
  67
  68 struct r600_texture_state {
  69         int tc_count;           /* number of incoming texture coordinates from VAP */
  70 };
  71
  72 /* Perhaps more if we store programs in vmem? */
  73 /* drm_r600_cmd_header_t->vpu->count is unsigned char */
  74 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
  75
  76 /* Can be tested with colormat currently. */
  77 #define VSF_MAX_FRAGMENT_TEMPS (14)
  78
  79 #define STATE_R600_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
  80 #define STATE_R600_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
  81
  82 extern int hw_tcl_on;
  83
  84 #define COLOR_IS_RGBA
  85 #define TAG(x) r600##x
  86 #include "tnl_dd/t_dd_vertex.h"
  87 #undef TAG
  88
  89 #define R600_FALLBACK_NONE 0
  90 #define R600_FALLBACK_TCL 1
  91 #define R600_FALLBACK_RAST 2
  92
  93 struct r600_hw_state {
  94         struct radeon_state_atom sq;
  95         struct radeon_state_atom db;
  96         struct radeon_state_atom stencil;
  97         struct radeon_state_atom db_target;
  98         struct radeon_state_atom sc;
  99         struct radeon_state_atom scissor;
 100         struct radeon_state_atom aa;
 101         struct radeon_state_atom cl;
 102         struct radeon_state_atom gb;
 103         struct radeon_state_atom ucp;
 104         struct radeon_state_atom su;
 105         struct radeon_state_atom poly;
 106         struct radeon_state_atom cb;
 107         struct radeon_state_atom clrcmp;
 108         struct radeon_state_atom blnd;
 109         struct radeon_state_atom blnd_clr;
 110         struct radeon_state_atom cb_target;
 111         struct radeon_state_atom sx;
 112         struct radeon_state_atom vgt;
 113         struct radeon_state_atom spi;
 114         struct radeon_state_atom vpt;
 115
 116         struct radeon_state_atom fs;
 117         struct radeon_state_atom vs;
 118         struct radeon_state_atom ps;
 119
 120         struct radeon_state_atom vs_consts;
 121         struct radeon_state_atom ps_consts;
 122
 123         struct radeon_state_atom vtx;
 124         struct radeon_state_atom tx;
 125         struct radeon_state_atom tx_smplr;
 126         struct radeon_state_atom tx_brdr_clr;
 127 };
 128
 129 typedef struct StreamDesc
 130 {
 131         GLint   size;   //number of data element
 132         GLenum  type;  //data element type
 133         GLsizei stride;
 134
 135         struct radeon_bo *bo;
 136         GLint  bo_offset;
 137
 138         GLuint    dwords;
 139         GLuint    dst_loc;
 140         GLuint    _signed;
 141         GLboolean normalize;
 142         GLboolean is_named_bo;
 143         GLubyte   element;
 144 } StreamDesc;
 145
 146 typedef struct r700_index_buffer
 147 {
 148         struct radeon_bo *bo;
 149         int    bo_offset;
 150
 151         GLboolean is_32bit;
 152         GLuint    count;
 153 } r700_index_buffer;
 154
 155 /**
 156  * \brief R600 context structure.
 157  */
 158 struct r600_context {
 159         struct radeon_context radeon;   /* parent class, must be first */
 160
 161         /* ------ */
 162         R700_CHIP_CONTEXT hw;
 163
 164         struct r600_hw_state atoms;
 165
 166         struct r700_vertex_program *selected_vp;
 167
 168         /* Vertex buffers
 169          */
 170         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 171         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 172
 173         GLint      nNumActiveAos;
 174         StreamDesc stream_desc[VERT_ATTRIB_MAX];
 175     struct r700_index_buffer ind_buf;
 176 };
 177
 178 #define R700_CONTEXT(ctx)               ((context_t *)(ctx->DriverCtx))
 179 #define GL_CONTEXT(context)     ((GLcontext *)(context->radeon.glCtx))
 180
 181 extern GLboolean r600CreateContext(const __GLcontextModes * glVisual,
 182                                    __DRIcontextPrivate * driContextPriv,
 183                                    void *sharedContextPrivate);
 184
 185 #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw))
 186
 187 #define R600_NEWPRIM( rmesa )                   \
 188 do {                                            \
 189         if ( rmesa->radeon.dma.flush )                  \
 190                 rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
 191 } while (0)
 192
 193 #define R600_STATECHANGE(r600, ATOM)                    \
 194 do {                                                    \
 195         R600_NEWPRIM(r600);                                     \
 196         r600->atoms.ATOM.dirty = GL_TRUE;                                       \
 197         r600->radeon.hw.is_dirty = GL_TRUE;                     \
 198 } while(0)
 199
 200 extern GLboolean r700SyncSurf(context_t *context,
 201                               struct radeon_bo *pbo,
 202                               uint32_t read_domain,
 203                               uint32_t write_domain,
 204                               uint32_t sync_type);
 205
 206 extern void r700SetupStreams(GLcontext * ctx);
 207 extern void r700Start3D(context_t *context);
 208 extern void r600InitAtoms(context_t *context);
 209 extern void r700InitDraw(GLcontext *ctx);
 210
 211 #define RADEON_D_CAPTURE 0
 212 #define RADEON_D_PLAYBACK 1
 213 #define RADEON_D_PLAYBACK_RAW 2
 214 #define RADEON_D_T 3
 215
 216 #define r600PackFloat32 radeonPackFloat32
 217 #define r600PackFloat24 radeonPackFloat24
 218
 219 #endif                          /* __R600_CONTEXT_H__ */