src/mesa/drivers/dri/r600/r600_context.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  * \author Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #ifndef __R600_CONTEXT_H__
  38 #define __R600_CONTEXT_H__
  39
  40 #include "tnl/t_vertex.h"
  41 #include "drm.h"
  42 #include "radeon_drm.h"
  43 #include "dri_util.h"
  44 #include "texmem.h"
  45 #include "radeon_common.h"
  46
  47 #include "main/macros.h"
  48 #include "main/mtypes.h"
  49 #include "main/colormac.h"
  50
  51 #include "r700_chip.h"
  52 #include "r600_tex.h"
  53 #include "r700_oglprog.h"
  54
  55 struct r600_context;
  56 typedef struct r600_context context_t;
  57
  58 #include "main/mm.h"
  59
  60 /************ DMA BUFFERS **************/
  61
  62 /* The blit width for texture uploads
  63  */
  64 #define R600_BLIT_WIDTH_BYTES 1024
  65 #define R600_MAX_TEXTURE_UNITS 8
  66
  67 struct r600_texture_state {
  68         int tc_count;           /* number of incoming texture coordinates from VAP */
  69 };
  70
  71 /* Perhaps more if we store programs in vmem? */
  72 /* drm_r600_cmd_header_t->vpu->count is unsigned char */
  73 #define VSF_MAX_FRAGMENT_LENGTH (255*4)
  74
  75 /* Can be tested with colormat currently. */
  76 #define VSF_MAX_FRAGMENT_TEMPS (14)
  77
  78 #define STATE_R600_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
  79 #define STATE_R600_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
  80
  81 extern int hw_tcl_on;
  82
  83 #define COLOR_IS_RGBA
  84 #define TAG(x) r600##x
  85 #include "tnl_dd/t_dd_vertex.h"
  86 #undef TAG
  87
  88 #define PFS_MAX_ALU_INST        64
  89 #define PFS_MAX_TEX_INST        64
  90 #define PFS_MAX_TEX_INDIRECT 4
  91 #define PFS_NUM_TEMP_REGS       32
  92 #define PFS_NUM_CONST_REGS      16
  93
  94 #define R600_MAX_AOS_ARRAYS             16
  95
  96 #define REG_COORDS      0
  97 #define REG_COLOR0      1
  98 #define REG_TEX0        2
  99
 100 #define R600_FALLBACK_NONE 0
 101 #define R600_FALLBACK_TCL 1
 102 #define R600_FALLBACK_RAST 2
 103
 104 enum
 105 {
 106     NO_SHIFT    = 0,
 107     LEFT_SHIFT  = 1,
 108     RIGHT_SHIFT = 2,
 109 };
 110
 111 struct r600_hw_state {
 112         struct radeon_state_atom sq;
 113         struct radeon_state_atom db;
 114         struct radeon_state_atom stencil;
 115         struct radeon_state_atom db_target;
 116         struct radeon_state_atom sc;
 117         struct radeon_state_atom scissor;
 118         struct radeon_state_atom aa;
 119         struct radeon_state_atom cl;
 120         struct radeon_state_atom gb;
 121         struct radeon_state_atom ucp;
 122         struct radeon_state_atom su;
 123         struct radeon_state_atom poly;
 124         struct radeon_state_atom cb;
 125         struct radeon_state_atom clrcmp;
 126         struct radeon_state_atom blnd;
 127         struct radeon_state_atom blnd_clr;
 128         struct radeon_state_atom cb_target;
 129         struct radeon_state_atom sx;
 130         struct radeon_state_atom vgt;
 131         struct radeon_state_atom spi;
 132         struct radeon_state_atom vpt;
 133
 134         struct radeon_state_atom fs;
 135         struct radeon_state_atom vs;
 136         struct radeon_state_atom ps;
 137
 138         struct radeon_state_atom vs_consts;
 139         struct radeon_state_atom ps_consts;
 140
 141         struct radeon_state_atom vtx;
 142         struct radeon_state_atom tx;
 143         struct radeon_state_atom tx_smplr;
 144         struct radeon_state_atom tx_brdr_clr;
 145 };
 146
 147 /**
 148  * \brief R600 context structure.
 149  */
 150 struct r600_context {
 151         struct radeon_context radeon;   /* parent class, must be first */
 152
 153         /* ------ */
 154         R700_CHIP_CONTEXT hw;
 155
 156         struct r600_hw_state atoms;
 157
 158         /* Vertex buffers
 159          */
 160         GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
 161         GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
 162
 163 };
 164
 165 #define R700_CONTEXT(ctx)               ((context_t *)(ctx->DriverCtx))
 166 #define GL_CONTEXT(context)     ((GLcontext *)(context->radeon.glCtx))
 167
 168 extern GLboolean r600CreateContext(const __GLcontextModes * glVisual,
 169                                    __DRIcontextPrivate * driContextPriv,
 170                                    void *sharedContextPrivate);
 171
 172 #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw))
 173
 174 #define R600_NEWPRIM( rmesa )                   \
 175 do {                                            \
 176         if ( rmesa->radeon.dma.flush )                  \
 177                 rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
 178 } while (0)
 179
 180 #define R600_STATECHANGE(r600, ATOM)                    \
 181 do {                                                    \
 182         R600_NEWPRIM(r600);                                     \
 183         r600->atoms.ATOM.dirty = GL_TRUE;                                       \
 184         r600->radeon.hw.is_dirty = GL_TRUE;                     \
 185 } while(0)
 186
 187 extern GLboolean r700SyncSurf(context_t *context,
 188                               struct radeon_bo *pbo,
 189                               uint32_t read_domain,
 190                               uint32_t write_domain,
 191                               uint32_t sync_type);
 192
 193 extern void r700SetupStreams(GLcontext * ctx);
 194 extern void r700Start3D(context_t *context);
 195 extern void r600InitAtoms(context_t *context);
 196
 197 #define RADEON_D_CAPTURE 0
 198 #define RADEON_D_PLAYBACK 1
 199 #define RADEON_D_PLAYBACK_RAW 2
 200 #define RADEON_D_T 3
 201
 202 #define r600PackFloat32 radeonPackFloat32
 203 #define r600PackFloat24 radeonPackFloat24
 204
 205 #endif                          /* __R600_CONTEXT_H__ */