2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
33 * \author Keith Whitwell <keith@tungstengraphics.com>
36 #include "main/glheader.h"
37 #include "main/mtypes.h"
38 #include "main/colormac.h"
39 #include "main/imports.h"
40 #include "main/macros.h"
41 #include "main/image.h"
43 #include "swrast_setup/swrast_setup.h"
44 #include "math/m_translate.h"
46 #include "tnl/t_context.h"
48 #include "r600_context.h"
49 #include "r600_state.h"
50 #include "r600_emit.h"
51 #include "r600_ioctl.h"
54 #if SWIZZLE_X != R600_INPUT_ROUTE_SELECT_X || \
55 SWIZZLE_Y != R600_INPUT_ROUTE_SELECT_Y || \
56 SWIZZLE_Z != R600_INPUT_ROUTE_SELECT_Z || \
57 SWIZZLE_W != R600_INPUT_ROUTE_SELECT_W || \
58 SWIZZLE_ZERO != R600_INPUT_ROUTE_SELECT_ZERO || \
59 SWIZZLE_ONE != R600_INPUT_ROUTE_SELECT_ONE
60 #error Cannot change these!
63 #define DEBUG_ALL DEBUG_VERTS
65 #define DW_SIZE(x) ((inputs[tab[(x)]] << R600_DST_VEC_LOC_SHIFT) | \
66 (attribptr[tab[(x)]]->size - 1) << R600_DATA_TYPE_0_SHIFT)
68 GLuint
r600VAPInputRoute0(uint32_t * dst
, GLvector4f
** attribptr
,
69 int *inputs
, GLint
* tab
, GLuint nr
)
73 /* type, inputs, stop bit, size */
74 for (i
= 0; i
< nr
; i
+= 2) {
75 /* make sure input is valid, would lockup the gpu */
76 assert(inputs
[tab
[i
]] != -1);
77 dw
= (R600_SIGNED
| DW_SIZE(i
));
79 dw
|= R600_LAST_VEC
<< R600_DATA_TYPE_0_SHIFT
;
81 assert(inputs
[tab
[i
+ 1]] != -1);
83 DW_SIZE(i
+ 1)) << R600_DATA_TYPE_1_SHIFT
;
85 dw
|= R600_LAST_VEC
<< R600_DATA_TYPE_1_SHIFT
;
94 static GLuint
r600VAPInputRoute1Swizzle(int swizzle
[4])
96 return (swizzle
[0] << R600_SWIZZLE_SELECT_X_SHIFT
) |
97 (swizzle
[1] << R600_SWIZZLE_SELECT_Y_SHIFT
) |
98 (swizzle
[2] << R600_SWIZZLE_SELECT_Z_SHIFT
) |
99 (swizzle
[3] << R600_SWIZZLE_SELECT_W_SHIFT
);
102 GLuint
r600VAPInputRoute1(uint32_t * dst
, int swizzle
[][4], GLuint nr
)
106 for (i
= 0; i
< nr
; i
+= 2) {
107 dw
= (r600VAPInputRoute1Swizzle(swizzle
[i
]) |
108 ((R600_WRITE_ENA_X
| R600_WRITE_ENA_Y
|
109 R600_WRITE_ENA_Z
| R600_WRITE_ENA_W
) << R600_WRITE_ENA_SHIFT
)) << R600_SWIZZLE0_SHIFT
;
111 dw
|= (r600VAPInputRoute1Swizzle(swizzle
[i
+ 1]) |
112 ((R600_WRITE_ENA_X
| R600_WRITE_ENA_Y
|
113 R600_WRITE_ENA_Z
| R600_WRITE_ENA_W
) << R600_WRITE_ENA_SHIFT
)) << R600_SWIZZLE1_SHIFT
;
118 return (nr
+ 1) >> 1;
121 GLuint
r600VAPInputCntl0(GLcontext
* ctx
, GLuint InputsRead
)
123 /* No idea what this value means. I have seen other values written to
124 * this register... */
128 GLuint
r600VAPInputCntl1(GLcontext
* ctx
, GLuint InputsRead
)
130 r600ContextPtr rmesa
= R600_CONTEXT(ctx
);
133 if (InputsRead
& (1 << VERT_ATTRIB_POS
))
134 vic_1
|= R600_INPUT_CNTL_POS
;
136 if (InputsRead
& (1 << VERT_ATTRIB_NORMAL
))
137 vic_1
|= R600_INPUT_CNTL_NORMAL
;
139 if (InputsRead
& (1 << VERT_ATTRIB_COLOR0
))
140 vic_1
|= R600_INPUT_CNTL_COLOR
;
142 rmesa
->state
.texture
.tc_count
= 0;
143 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++)
144 if (InputsRead
& (1 << (VERT_ATTRIB_TEX0
+ i
))) {
145 rmesa
->state
.texture
.tc_count
++;
146 vic_1
|= R600_INPUT_CNTL_TC0
<< i
;
152 GLuint
r600VAPOutputCntl0(GLcontext
* ctx
, GLuint OutputsWritten
)
156 if (OutputsWritten
& (1 << VERT_RESULT_HPOS
))
157 ret
|= R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
;
159 if (OutputsWritten
& (1 << VERT_RESULT_COL0
))
160 ret
|= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT
;
162 if (OutputsWritten
& (1 << VERT_RESULT_COL1
))
163 ret
|= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT
;
165 if (OutputsWritten
& (1 << VERT_RESULT_BFC0
)
166 || OutputsWritten
& (1 << VERT_RESULT_BFC1
))
168 R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT
|
169 R600_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT
|
170 R600_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT
;
172 if (OutputsWritten
& (1 << VERT_RESULT_PSIZ
))
173 ret
|= R600_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT
;
178 GLuint
r600VAPOutputCntl1(GLcontext
* ctx
, GLuint OutputsWritten
)
180 GLuint i
, ret
= 0, first_free_texcoord
= 0;
182 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
183 if (OutputsWritten
& (1 << (VERT_RESULT_TEX0
+ i
))) {
184 ret
|= (4 << (3 * i
));
185 ++first_free_texcoord
;
189 if (OutputsWritten
& (1 << VERT_RESULT_FOGC
)) {
190 if (first_free_texcoord
> 8) {
191 fprintf(stderr
, "\tout of free texcoords to write fog coord\n");
194 ret
|= 4 << (3 * first_free_texcoord
);
200 /* Emit vertex data to GART memory
201 * Route inputs to the vertex processor
202 * This function should never return R600_FALLBACK_TCL when using software tcl.
204 int r600EmitArrays(GLcontext
* ctx
)
206 r600ContextPtr rmesa
= R600_CONTEXT(ctx
);
207 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
208 struct vertex_buffer
*vb
= &tnl
->vb
;
210 GLuint count
= vb
->Count
;
212 GLuint InputsRead
= 0, OutputsWritten
= 0;
214 int vir_inputs
[VERT_ATTRIB_MAX
];
215 GLint tab
[VERT_ATTRIB_MAX
];
216 int swizzle
[VERT_ATTRIB_MAX
][4];
217 struct r600_vertex_program
*prog
=
218 (struct r600_vertex_program
*)CURRENT_VERTEX_SHADER(ctx
);
221 inputs
= prog
->inputs
;
222 InputsRead
= prog
->key
.InputsRead
;
223 OutputsWritten
= prog
->key
.OutputsWritten
;
225 inputs
= rmesa
->state
.sw_tcl_inputs
;
227 DECLARE_RENDERINPUTS(render_inputs_bitset
);
228 RENDERINPUTS_COPY(render_inputs_bitset
, tnl
->render_inputs_bitset
);
230 vb
->AttribPtr
[VERT_ATTRIB_POS
] = vb
->ClipPtr
;
232 assert(RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_POS
));
233 assert(RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_NORMAL
) == 0);
235 if (RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_POS
)) {
236 InputsRead
|= 1 << VERT_ATTRIB_POS
;
237 OutputsWritten
|= 1 << VERT_RESULT_HPOS
;
240 if (RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_COLOR0
)) {
241 InputsRead
|= 1 << VERT_ATTRIB_COLOR0
;
242 OutputsWritten
|= 1 << VERT_RESULT_COL0
;
245 if (RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_COLOR1
)) {
246 InputsRead
|= 1 << VERT_ATTRIB_COLOR1
;
247 OutputsWritten
|= 1 << VERT_RESULT_COL1
;
250 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
251 if (RENDERINPUTS_TEST(render_inputs_bitset
, _TNL_ATTRIB_TEX(i
))) {
252 InputsRead
|= 1 << (VERT_ATTRIB_TEX0
+ i
);
253 OutputsWritten
|= 1 << (VERT_RESULT_TEX0
+ i
);
257 for (i
= 0, nr
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
258 if (InputsRead
& (1 << i
)) {
265 /* Fixed, apply to vir0 only */
266 memcpy(vir_inputs
, inputs
, VERT_ATTRIB_MAX
* sizeof(int));
268 if (InputsRead
& VERT_ATTRIB_POS
)
269 inputs
[VERT_ATTRIB_POS
] = 0;
270 if (InputsRead
& (1 << VERT_ATTRIB_COLOR0
))
271 inputs
[VERT_ATTRIB_COLOR0
] = 2;
272 if (InputsRead
& (1 << VERT_ATTRIB_COLOR1
))
273 inputs
[VERT_ATTRIB_COLOR1
] = 3;
274 for (i
= VERT_ATTRIB_TEX0
; i
<= VERT_ATTRIB_TEX7
; i
++)
275 if (InputsRead
& (1 << i
))
276 inputs
[i
] = 6 + (i
- VERT_ATTRIB_TEX0
);
278 RENDERINPUTS_COPY(rmesa
->state
.render_inputs_bitset
, render_inputs_bitset
);
282 assert(OutputsWritten
);
284 for (i
= 0, nr
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
285 if (InputsRead
& (1 << i
)) {
290 if (nr
> R600_MAX_AOS_ARRAYS
) {
291 return R600_FALLBACK_TCL
;
294 for (i
= 0; i
< nr
; i
++) {
297 swizzle
[i
][0] = SWIZZLE_ZERO
;
298 swizzle
[i
][1] = SWIZZLE_ZERO
;
299 swizzle
[i
][2] = SWIZZLE_ZERO
;
300 swizzle
[i
][3] = SWIZZLE_ONE
;
302 for (ci
= 0; ci
< vb
->AttribPtr
[tab
[i
]]->size
; ci
++) {
305 rcommon_emit_vector(ctx
, &rmesa
->radeon
.tcl
.aos
[i
],
306 vb
->AttribPtr
[tab
[i
]]->data
,
307 vb
->AttribPtr
[tab
[i
]]->size
,
308 vb
->AttribPtr
[tab
[i
]]->stride
, count
);
311 /* Setup INPUT_ROUTE. */
312 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
313 R600_STATECHANGE(rmesa
, vir
[0]);
314 rmesa
->hw
.vir
[0].cmd
[0] &= 0xC000FFFF;
315 rmesa
->hw
.vir
[1].cmd
[0] &= 0xC000FFFF;
316 rmesa
->hw
.vir
[0].cmd
[0] |=
317 (r600VAPInputRoute0(&rmesa
->hw
.vir
[0].cmd
[R600_VIR_CNTL_0
],
318 vb
->AttribPtr
, inputs
, tab
, nr
) & 0x3FFF) << 16;
319 R600_STATECHANGE(rmesa
, vir
[1]);
320 rmesa
->hw
.vir
[1].cmd
[0] |=
321 (r600VAPInputRoute1(&rmesa
->hw
.vir
[1].cmd
[R600_VIR_CNTL_0
], swizzle
,
324 R600_STATECHANGE(rmesa
, vir
[0]);
325 ((drm_r300_cmd_header_t
*) rmesa
->hw
.vir
[0].cmd
)->packet0
.count
=
326 r600VAPInputRoute0(&rmesa
->hw
.vir
[0].cmd
[R600_VIR_CNTL_0
],
327 vb
->AttribPtr
, inputs
, tab
, nr
);
328 R600_STATECHANGE(rmesa
, vir
[1]);
329 ((drm_r300_cmd_header_t
*) rmesa
->hw
.vir
[1].cmd
)->packet0
.count
=
330 r600VAPInputRoute1(&rmesa
->hw
.vir
[1].cmd
[R600_VIR_CNTL_0
], swizzle
,
334 /* Setup INPUT_CNTL. */
335 R600_STATECHANGE(rmesa
, vic
);
336 rmesa
->hw
.vic
.cmd
[R600_VIC_CNTL_0
] = r600VAPInputCntl0(ctx
, InputsRead
);
337 rmesa
->hw
.vic
.cmd
[R600_VIC_CNTL_1
] = r600VAPInputCntl1(ctx
, InputsRead
);
339 /* Setup OUTPUT_VTX_FMT. */
340 R600_STATECHANGE(rmesa
, vof
);
341 rmesa
->hw
.vof
.cmd
[R600_VOF_CNTL_0
] =
342 r600VAPOutputCntl0(ctx
, OutputsWritten
);
343 rmesa
->hw
.vof
.cmd
[R600_VOF_CNTL_1
] =
344 r600VAPOutputCntl1(ctx
, OutputsWritten
);
346 rmesa
->radeon
.tcl
.aos_count
= nr
;
348 return R600_FALLBACK_NONE
;
351 void r600EmitCacheFlush(r600ContextPtr rmesa
)
353 BATCH_LOCALS(&rmesa
->radeon
);
355 BEGIN_BATCH_NO_AUTOSTATE(4);
356 OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT
,
357 R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS
|
358 R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D
);
359 OUT_BATCH_REGVAL(R600_ZB_ZCACHE_CTLSTAT
,
360 R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
|
361 R600_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
);