src/mesa/drivers/dri/r600/r600_emit.h

   1 /*
   2  * Copyright (C) 2005 Vladimir Dergachev.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /*
  29  * Authors:
  30  *   Vladimir Dergachev <volodya@mindspring.com>
  31  *   Nicolai Haehnle <prefect_@gmx.net>
  32  *   Aapo Tahkola <aet@rasterburn.org>
  33  *   Ben Skeggs <darktama@iinet.net.au>
  34  *   Jerome Glisse <j.glisse@gmail.com>
  35  */
  36
  37 /* This files defines functions for accessing R600 hardware.
  38  */
  39 #ifndef __R600_EMIT_H__
  40 #define __R600_EMIT_H__
  41
  42 #include "main/glheader.h"
  43 #include "r600_context.h"
  44 #include "r600_cmdbuf.h"
  45 #include "radeon_reg.h"
  46
  47 static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn,
  48                                   int reg, int count)
  49 {
  50         if (count) {
  51                 return CP_PACKET0(reg, count - 1);
  52         }
  53         return CP_PACKET2;
  54 }
  55
  56 static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count)
  57 {
  58         drm_r300_cmd_header_t cmd;
  59
  60         cmd.u = 0;
  61         cmd.vpu.cmd_type = R300_CMD_VPU;
  62         cmd.vpu.count = count;
  63         cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8;
  64         cmd.vpu.adrlo = ((unsigned int)addr & 0x00FF);
  65
  66         return cmd.u;
  67 }
  68
  69 static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn,
  70                                  int addr, int count, int type, int clamp)
  71 {
  72         drm_r300_cmd_header_t cmd;
  73
  74         cmd.u = 0;
  75         cmd.r500fp.cmd_type = R300_CMD_R500FP;
  76         cmd.r500fp.count = count;
  77         cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8;
  78         cmd.r500fp.adrhi_flags |= type ? R500FP_CONSTANT_TYPE : 0;
  79         cmd.r500fp.adrhi_flags |= clamp ? R500FP_CONSTANT_CLAMP : 0;
  80         cmd.r500fp.adrlo = ((unsigned int)addr & 0x00FF);
  81
  82         return cmd.u;
  83 }
  84
  85 static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet)
  86 {
  87         drm_r300_cmd_header_t cmd;
  88
  89         cmd.u = 0;
  90         cmd.packet3.cmd_type = R300_CMD_PACKET3;
  91         cmd.packet3.packet = packet;
  92
  93         return cmd.u;
  94 }
  95
  96 static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn,
  97                                   unsigned short count)
  98 {
  99         drm_r300_cmd_header_t cmd;
 100
 101         cmd.u = 0;
 102
 103         cmd.delay.cmd_type = R300_CMD_CP_DELAY;
 104         cmd.delay.count = count;
 105
 106         return cmd.u;
 107 }
 108
 109 static INLINE uint32_t cmdwait(struct radeon_screen *rscrn,
 110                                unsigned char flags)
 111 {
 112         drm_r300_cmd_header_t cmd;
 113
 114         cmd.u = 0;
 115         cmd.wait.cmd_type = R300_CMD_WAIT;
 116         cmd.wait.flags = flags;
 117
 118         return cmd.u;
 119 }
 120
 121 static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn)
 122 {
 123         drm_r300_cmd_header_t cmd;
 124
 125         cmd.u = 0;
 126         cmd.header.cmd_type = R300_CMD_END3D;
 127
 128         return cmd.u;
 129 }
 130
 131 /**
 132  * Write the header of a packet3 to the command buffer.
 133  * Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards.
 134  */
 135 #define OUT_BATCH_PACKET3(packet, num_extra) do {\
 136     if (!b_l_rmesa->radeonScreen->kernel_mm) {          \
 137         OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\
 138                   R300_CMD_PACKET3_RAW)); \
 139     } else b_l_rmesa->cmdbuf.cs->section_cdw++;\
 140         OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
 141         } while(0)
 142
 143 /**
 144  * Must be sent to switch to 2d commands
 145  */
 146 void static INLINE end_3d(radeonContextPtr radeon)
 147 {
 148         BATCH_LOCALS(radeon);
 149
 150         if (!radeon->radeonScreen->kernel_mm) {
 151                 BEGIN_BATCH_NO_AUTOSTATE(1);
 152                 OUT_BATCH(cmdpacify(radeon->radeonScreen));
 153                 END_BATCH();
 154         }
 155 }
 156
 157 void static INLINE cp_delay(r600ContextPtr rmesa, unsigned short count)
 158 {
 159         BATCH_LOCALS(&rmesa->radeon);
 160
 161         if (!rmesa->radeon.radeonScreen->kernel_mm) {
 162                 BEGIN_BATCH_NO_AUTOSTATE(1);
 163                 OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count));
 164                 END_BATCH();
 165         }
 166 }
 167
 168 void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags)
 169 {
 170         BATCH_LOCALS(radeon);
 171         uint32_t wait_until;
 172
 173         if (!radeon->radeonScreen->kernel_mm) {
 174                 BEGIN_BATCH_NO_AUTOSTATE(1);
 175                 OUT_BATCH(cmdwait(radeon->radeonScreen, flags));
 176                 END_BATCH();
 177         } else {
 178                 switch(flags) {
 179                 case R300_WAIT_2D:
 180                         wait_until = (1 << 14);
 181                         break;
 182                 case R300_WAIT_3D:
 183                         wait_until = (1 << 15);
 184                         break;
 185                 case R300_NEW_WAIT_2D_3D:
 186                         wait_until = (1 << 14) | (1 << 15);
 187                         break;
 188                 case R300_NEW_WAIT_2D_2D_CLEAN:
 189                         wait_until = (1 << 14) | (1 << 16) | (1 << 18);
 190                         break;
 191                 case R300_NEW_WAIT_3D_3D_CLEAN:
 192                         wait_until = (1 << 15) | (1 << 17) | (1 << 18);
 193                         break;
 194                 case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
 195                         wait_until  = (1 << 14) | (1 << 16) | (1 << 18);
 196                         wait_until |= (1 << 15) | (1 << 17) | (1 << 18);
 197                         break;
 198                 default:
 199                         return;
 200                 }
 201                 BEGIN_BATCH_NO_AUTOSTATE(2);
 202                 OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
 203                 OUT_BATCH(wait_until);
 204                 END_BATCH();
 205         }
 206 }
 207
 208 extern int r600EmitArrays(GLcontext * ctx);
 209
 210 extern int r600PrimitiveType(r600ContextPtr rmesa, int prim);
 211 extern int r600NumVerts(r600ContextPtr rmesa, int num_verts, int prim);
 212
 213 extern void r600EmitCacheFlush(r600ContextPtr rmesa);
 214
 215 extern GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
 216                                  int *inputs, GLint * tab, GLuint nr);
 217 extern GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr);
 218 extern GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead);
 219 extern GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead);
 220 extern GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten);
 221 extern GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten);
 222
 223 #endif