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[mesa.git] / src / mesa / drivers / dri / r600 / r600_fragprog.c
1 /*
2 * Copyright (C) 2005 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 /**
29 * \file
30 *
31 * Fragment program compiler. Perform transformations on the intermediate
32 * representation until the program is in a form where we can translate
33 * it more or less directly into machine-readable form.
34 *
35 * \author Ben Skeggs <darktama@iinet.net.au>
36 * \author Jerome Glisse <j.glisse@gmail.com>
37 */
38
39 #include "main/glheader.h"
40 #include "main/macros.h"
41 #include "main/enums.h"
42 #include "shader/prog_instruction.h"
43 #include "shader/prog_parameter.h"
44 #include "shader/prog_print.h"
45
46 #include "r600_context.h"
47 #include "r600_fragprog.h"
48 #include "r600_fragprog_swizzle.h"
49 #include "r600_state.h"
50
51 #include "radeon_nqssadce.h"
52 #include "radeon_program_alu.h"
53
54
55 static void reset_srcreg(struct prog_src_register* reg)
56 {
57 _mesa_bzero(reg, sizeof(*reg));
58 reg->Swizzle = SWIZZLE_NOOP;
59 }
60
61 static struct prog_src_register shadow_ambient(struct gl_program *program, int tmu)
62 {
63 gl_state_index fail_value_tokens[STATE_LENGTH] = {
64 STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0
65 };
66 struct prog_src_register reg = { 0, };
67
68 fail_value_tokens[2] = tmu;
69 reg.File = PROGRAM_STATE_VAR;
70 reg.Index = _mesa_add_state_reference(program->Parameters, fail_value_tokens);
71 reg.Swizzle = SWIZZLE_WWWW;
72 return reg;
73 }
74
75 /**
76 * Transform TEX, TXP, TXB, and KIL instructions in the following way:
77 * - premultiply texture coordinates for RECT
78 * - extract operand swizzles
79 * - introduce a temporary register when write masks are needed
80 *
81 * \todo If/when r5xx uses the radeon_program architecture, this can probably
82 * be reused.
83 */
84 static GLboolean transform_TEX(
85 struct radeon_transform_context *t,
86 struct prog_instruction* orig_inst, void* data)
87 {
88 struct r600_fragment_program_compiler *compiler =
89 (struct r600_fragment_program_compiler*)data;
90 struct prog_instruction inst = *orig_inst;
91 struct prog_instruction* tgt;
92 GLboolean destredirect = GL_FALSE;
93
94 if (inst.Opcode != OPCODE_TEX &&
95 inst.Opcode != OPCODE_TXB &&
96 inst.Opcode != OPCODE_TXP &&
97 inst.Opcode != OPCODE_KIL)
98 return GL_FALSE;
99
100 if (inst.Opcode != OPCODE_KIL &&
101 t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) {
102 GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func;
103
104 if (comparefunc == GL_NEVER || comparefunc == GL_ALWAYS) {
105 tgt = radeonAppendInstructions(t->Program, 1);
106
107 tgt->Opcode = OPCODE_MOV;
108 tgt->DstReg = inst.DstReg;
109 if (comparefunc == GL_ALWAYS) {
110 tgt->SrcReg[0].File = PROGRAM_BUILTIN;
111 tgt->SrcReg[0].Swizzle = SWIZZLE_1111;
112 } else {
113 tgt->SrcReg[0] = shadow_ambient(t->Program, inst.TexSrcUnit);
114 }
115 return GL_TRUE;
116 }
117
118 inst.DstReg.File = PROGRAM_TEMPORARY;
119 inst.DstReg.Index = radeonFindFreeTemporary(t);
120 inst.DstReg.WriteMask = WRITEMASK_XYZW;
121 }
122
123
124 /* Hardware uses [0..1]x[0..1] range for rectangle textures
125 * instead of [0..Width]x[0..Height].
126 * Add a scaling instruction.
127 */
128 if (inst.Opcode != OPCODE_KIL && inst.TexSrcTarget == TEXTURE_RECT_INDEX) {
129 gl_state_index tokens[STATE_LENGTH] = {
130 STATE_INTERNAL, STATE_R600_TEXRECT_FACTOR, 0, 0,
131 0
132 };
133
134 int tempreg = radeonFindFreeTemporary(t);
135 int factor_index;
136
137 tokens[2] = inst.TexSrcUnit;
138 factor_index = _mesa_add_state_reference(t->Program->Parameters, tokens);
139
140 tgt = radeonAppendInstructions(t->Program, 1);
141
142 tgt->Opcode = OPCODE_MUL;
143 tgt->DstReg.File = PROGRAM_TEMPORARY;
144 tgt->DstReg.Index = tempreg;
145 tgt->SrcReg[0] = inst.SrcReg[0];
146 tgt->SrcReg[1].File = PROGRAM_STATE_VAR;
147 tgt->SrcReg[1].Index = factor_index;
148
149 reset_srcreg(&inst.SrcReg[0]);
150 inst.SrcReg[0].File = PROGRAM_TEMPORARY;
151 inst.SrcReg[0].Index = tempreg;
152 }
153
154 if (inst.Opcode != OPCODE_KIL) {
155 if (inst.DstReg.File != PROGRAM_TEMPORARY ||
156 inst.DstReg.WriteMask != WRITEMASK_XYZW) {
157 int tempreg = radeonFindFreeTemporary(t);
158
159 inst.DstReg.File = PROGRAM_TEMPORARY;
160 inst.DstReg.Index = tempreg;
161 inst.DstReg.WriteMask = WRITEMASK_XYZW;
162 destredirect = GL_TRUE;
163 }
164 }
165
166 if (inst.SrcReg[0].File != PROGRAM_TEMPORARY && inst.SrcReg[0].File != PROGRAM_INPUT) {
167 int tmpreg = radeonFindFreeTemporary(t);
168 tgt = radeonAppendInstructions(t->Program, 1);
169 tgt->Opcode = OPCODE_MOV;
170 tgt->DstReg.File = PROGRAM_TEMPORARY;
171 tgt->DstReg.Index = tmpreg;
172 tgt->SrcReg[0] = inst.SrcReg[0];
173
174 reset_srcreg(&inst.SrcReg[0]);
175 inst.SrcReg[0].File = PROGRAM_TEMPORARY;
176 inst.SrcReg[0].Index = tmpreg;
177 }
178
179 tgt = radeonAppendInstructions(t->Program, 1);
180 _mesa_copy_instructions(tgt, &inst, 1);
181
182 if (inst.Opcode != OPCODE_KIL &&
183 t->Program->ShadowSamplers & (1 << inst.TexSrcUnit)) {
184 GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func;
185 GLuint depthmode = compiler->fp->state.unit[inst.TexSrcUnit].depth_texture_mode;
186 int rcptemp = radeonFindFreeTemporary(t);
187 int pass, fail;
188
189 tgt = radeonAppendInstructions(t->Program, 3);
190
191 tgt[0].Opcode = OPCODE_RCP;
192 tgt[0].DstReg.File = PROGRAM_TEMPORARY;
193 tgt[0].DstReg.Index = rcptemp;
194 tgt[0].DstReg.WriteMask = WRITEMASK_W;
195 tgt[0].SrcReg[0] = inst.SrcReg[0];
196 tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW;
197
198 tgt[1].Opcode = OPCODE_MAD;
199 tgt[1].DstReg = inst.DstReg;
200 tgt[1].DstReg.WriteMask = orig_inst->DstReg.WriteMask;
201 tgt[1].SrcReg[0] = inst.SrcReg[0];
202 tgt[1].SrcReg[0].Swizzle = SWIZZLE_ZZZZ;
203 tgt[1].SrcReg[1].File = PROGRAM_TEMPORARY;
204 tgt[1].SrcReg[1].Index = rcptemp;
205 tgt[1].SrcReg[1].Swizzle = SWIZZLE_WWWW;
206 tgt[1].SrcReg[2].File = PROGRAM_TEMPORARY;
207 tgt[1].SrcReg[2].Index = inst.DstReg.Index;
208 if (depthmode == 0) /* GL_LUMINANCE */
209 tgt[1].SrcReg[2].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z);
210 else if (depthmode == 2) /* GL_ALPHA */
211 tgt[1].SrcReg[2].Swizzle = SWIZZLE_WWWW;
212
213 /* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
214 * r < tex <=> -tex+r < 0
215 * r >= tex <=> not (-tex+r < 0 */
216 if (comparefunc == GL_LESS || comparefunc == GL_GEQUAL)
217 tgt[1].SrcReg[2].NegateBase = tgt[0].SrcReg[2].NegateBase ^ NEGATE_XYZW;
218 else
219 tgt[1].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW;
220
221 tgt[2].Opcode = OPCODE_CMP;
222 tgt[2].DstReg = orig_inst->DstReg;
223 tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY;
224 tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index;
225
226 if (comparefunc == GL_LESS || comparefunc == GL_GREATER) {
227 pass = 1;
228 fail = 2;
229 } else {
230 pass = 2;
231 fail = 1;
232 }
233
234 tgt[2].SrcReg[pass].File = PROGRAM_BUILTIN;
235 tgt[2].SrcReg[pass].Swizzle = SWIZZLE_1111;
236 tgt[2].SrcReg[fail] = shadow_ambient(t->Program, inst.TexSrcUnit);
237 } else if (destredirect) {
238 tgt = radeonAppendInstructions(t->Program, 1);
239
240 tgt->Opcode = OPCODE_MOV;
241 tgt->DstReg = orig_inst->DstReg;
242 tgt->SrcReg[0].File = PROGRAM_TEMPORARY;
243 tgt->SrcReg[0].Index = inst.DstReg.Index;
244 }
245
246 return GL_TRUE;
247 }
248
249
250 static void update_params(r600ContextPtr r600, struct r600_fragment_program *fp)
251 {
252 struct gl_fragment_program *mp = &fp->mesa_program;
253
254 /* Ask Mesa nicely to fill in ParameterValues for us */
255 if (mp->Base.Parameters)
256 _mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters);
257 }
258
259
260 /**
261 * Transform the program to support fragment.position.
262 *
263 * Introduce a small fragment at the start of the program that will be
264 * the only code that directly reads the FRAG_ATTRIB_WPOS input.
265 * All other code pieces that reference that input will be rewritten
266 * to read from a newly allocated temporary.
267 *
268 * \todo if/when r5xx supports the radeon_program architecture, this is a
269 * likely candidate for code sharing.
270 */
271 static void insert_WPOS_trailer(struct r600_fragment_program_compiler *compiler)
272 {
273 GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead;
274
275 if (!(InputsRead & FRAG_BIT_WPOS))
276 return;
277
278 static gl_state_index tokens[STATE_LENGTH] = {
279 STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0
280 };
281 struct prog_instruction *fpi;
282 GLuint window_index;
283 int i = 0;
284 GLuint tempregi = _mesa_find_free_register(compiler->program, PROGRAM_TEMPORARY);
285
286 _mesa_insert_instructions(compiler->program, 0, 3);
287 fpi = compiler->program->Instructions;
288
289 /* perspective divide */
290 fpi[i].Opcode = OPCODE_RCP;
291
292 fpi[i].DstReg.File = PROGRAM_TEMPORARY;
293 fpi[i].DstReg.Index = tempregi;
294 fpi[i].DstReg.WriteMask = WRITEMASK_W;
295 fpi[i].DstReg.CondMask = COND_TR;
296
297 fpi[i].SrcReg[0].File = PROGRAM_INPUT;
298 fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
299 fpi[i].SrcReg[0].Swizzle = SWIZZLE_WWWW;
300 i++;
301
302 fpi[i].Opcode = OPCODE_MUL;
303
304 fpi[i].DstReg.File = PROGRAM_TEMPORARY;
305 fpi[i].DstReg.Index = tempregi;
306 fpi[i].DstReg.WriteMask = WRITEMASK_XYZ;
307 fpi[i].DstReg.CondMask = COND_TR;
308
309 fpi[i].SrcReg[0].File = PROGRAM_INPUT;
310 fpi[i].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
311 fpi[i].SrcReg[0].Swizzle = SWIZZLE_XYZW;
312
313 fpi[i].SrcReg[1].File = PROGRAM_TEMPORARY;
314 fpi[i].SrcReg[1].Index = tempregi;
315 fpi[i].SrcReg[1].Swizzle = SWIZZLE_WWWW;
316 i++;
317
318 /* viewport transformation */
319 window_index = _mesa_add_state_reference(compiler->program->Parameters, tokens);
320
321 fpi[i].Opcode = OPCODE_MAD;
322
323 fpi[i].DstReg.File = PROGRAM_TEMPORARY;
324 fpi[i].DstReg.Index = tempregi;
325 fpi[i].DstReg.WriteMask = WRITEMASK_XYZ;
326 fpi[i].DstReg.CondMask = COND_TR;
327
328 fpi[i].SrcReg[0].File = PROGRAM_TEMPORARY;
329 fpi[i].SrcReg[0].Index = tempregi;
330 fpi[i].SrcReg[0].Swizzle =
331 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
332
333 fpi[i].SrcReg[1].File = PROGRAM_STATE_VAR;
334 fpi[i].SrcReg[1].Index = window_index;
335 fpi[i].SrcReg[1].Swizzle =
336 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
337
338 fpi[i].SrcReg[2].File = PROGRAM_STATE_VAR;
339 fpi[i].SrcReg[2].Index = window_index;
340 fpi[i].SrcReg[2].Swizzle =
341 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ZERO);
342 i++;
343
344 for (; i < compiler->program->NumInstructions; ++i) {
345 int reg;
346 for (reg = 0; reg < 3; reg++) {
347 if (fpi[i].SrcReg[reg].File == PROGRAM_INPUT &&
348 fpi[i].SrcReg[reg].Index == FRAG_ATTRIB_WPOS) {
349 fpi[i].SrcReg[reg].File = PROGRAM_TEMPORARY;
350 fpi[i].SrcReg[reg].Index = tempregi;
351 }
352 }
353 }
354 }
355
356
357 static void nqssadce_init(struct nqssadce_state* s)
358 {
359 s->Outputs[FRAG_RESULT_COLOR].Sourced = WRITEMASK_XYZW;
360 s->Outputs[FRAG_RESULT_DEPTH].Sourced = WRITEMASK_W;
361 }
362
363
364 static GLuint build_dtm(GLuint depthmode)
365 {
366 switch(depthmode) {
367 default:
368 case GL_LUMINANCE: return 0;
369 case GL_INTENSITY: return 1;
370 case GL_ALPHA: return 2;
371 }
372 }
373
374 static GLuint build_func(GLuint comparefunc)
375 {
376 return comparefunc - GL_NEVER;
377 }
378
379
380 /**
381 * Collect all external state that is relevant for compiling the given
382 * fragment program.
383 */
384 static void build_state(
385 r600ContextPtr r600,
386 struct r600_fragment_program *fp,
387 struct r600_fragment_program_external_state *state)
388 {
389 int unit;
390
391 _mesa_bzero(state, sizeof(*state));
392
393 for(unit = 0; unit < 16; ++unit) {
394 if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) {
395 struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current;
396
397 state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode);
398 state->unit[unit].texture_compare_func = build_func(tex->CompareFunc);
399 }
400 }
401 }
402
403
404 void r600TranslateFragmentShader(r600ContextPtr r600,
405 struct r600_fragment_program *fp)
406 {
407 struct r600_fragment_program_external_state state;
408
409 build_state(r600, fp, &state);
410 if (_mesa_memcmp(&fp->state, &state, sizeof(state))) {
411 /* TODO: cache compiled programs */
412 fp->translated = GL_FALSE;
413 _mesa_memcpy(&fp->state, &state, sizeof(state));
414 }
415
416 if (!fp->translated) {
417 struct r600_fragment_program_compiler compiler;
418
419 compiler.r600 = r600;
420 compiler.fp = fp;
421 compiler.code = &fp->code;
422 compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base);
423
424 if (RADEON_DEBUG & DEBUG_PIXEL) {
425 _mesa_printf("Fragment Program: Initial program:\n");
426 _mesa_print_program(compiler.program);
427 }
428
429 insert_WPOS_trailer(&compiler);
430
431 struct radeon_program_transformation transformations[] = {
432 { &transform_TEX, &compiler },
433 { &radeonTransformALU, 0 },
434 { &radeonTransformTrigSimple, 0 }
435 };
436 radeonLocalTransform(
437 r600->radeon.glCtx,
438 compiler.program,
439 3, transformations);
440
441 if (RADEON_DEBUG & DEBUG_PIXEL) {
442 _mesa_printf("Fragment Program: After native rewrite:\n");
443 _mesa_print_program(compiler.program);
444 }
445
446 struct radeon_nqssadce_descr nqssadce = {
447 .Init = &nqssadce_init,
448 .IsNativeSwizzle = &r600FPIsNativeSwizzle,
449 .BuildSwizzle = &r600FPBuildSwizzle,
450 .RewriteDepthOut = GL_TRUE
451 };
452 radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce);
453
454 if (RADEON_DEBUG & DEBUG_PIXEL) {
455 _mesa_printf("Compiler: after NqSSA-DCE:\n");
456 _mesa_print_program(compiler.program);
457 }
458
459 if (!r600FragmentProgramEmit(&compiler))
460 fp->error = GL_TRUE;
461
462 /* Subtle: Rescue any parameters that have been added during transformations */
463 _mesa_free_parameter_list(fp->mesa_program.Base.Parameters);
464 fp->mesa_program.Base.Parameters = compiler.program->Parameters;
465 compiler.program->Parameters = 0;
466
467 _mesa_reference_program(r600->radeon.glCtx, &compiler.program, NULL);
468
469 if (!fp->error)
470 fp->translated = GL_TRUE;
471 if (fp->error || (RADEON_DEBUG & DEBUG_PIXEL))
472 r600FragmentProgramDump(fp, &fp->code);
473 r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM);
474 }
475
476 update_params(r600, fp);
477 }
478
479 /* just some random things... */
480 void r600FragmentProgramDump(
481 struct r600_fragment_program *fp,
482 struct r600_fragment_program_code *code)
483 {
484 int n, i, j;
485 static int pc = 0;
486
487 fprintf(stderr, "pc=%d*************************************\n", pc++);
488
489 fprintf(stderr, "Hardware program\n");
490 fprintf(stderr, "----------------\n");
491
492 for (n = 0; n < (code->cur_node + 1); n++) {
493 fprintf(stderr, "NODE %d: alu_offset: %d, tex_offset: %d, "
494 "alu_end: %d, tex_end: %d, flags: %08x\n", n,
495 code->node[n].alu_offset,
496 code->node[n].tex_offset,
497 code->node[n].alu_end, code->node[n].tex_end,
498 code->node[n].flags);
499
500 if (n > 0 || code->first_node_has_tex) {
501 fprintf(stderr, " TEX:\n");
502 for (i = code->node[n].tex_offset;
503 i <= code->node[n].tex_offset + code->node[n].tex_end;
504 ++i) {
505 const char *instr;
506
507 switch ((code->tex.
508 inst[i] >> R600_TEX_INST_SHIFT) &
509 15) {
510 case R600_TEX_OP_LD:
511 instr = "TEX";
512 break;
513 case R600_TEX_OP_KIL:
514 instr = "KIL";
515 break;
516 case R600_TEX_OP_TXP:
517 instr = "TXP";
518 break;
519 case R600_TEX_OP_TXB:
520 instr = "TXB";
521 break;
522 default:
523 instr = "UNKNOWN";
524 }
525
526 fprintf(stderr,
527 " %s t%i, %c%i, texture[%i] (%08x)\n",
528 instr,
529 (code->tex.
530 inst[i] >> R600_DST_ADDR_SHIFT) & 31,
531 't',
532 (code->tex.
533 inst[i] >> R600_SRC_ADDR_SHIFT) & 31,
534 (code->tex.
535 inst[i] & R600_TEX_ID_MASK) >>
536 R600_TEX_ID_SHIFT,
537 code->tex.inst[i]);
538 }
539 }
540
541 for (i = code->node[n].alu_offset;
542 i <= code->node[n].alu_offset + code->node[n].alu_end; ++i) {
543 char srcc[3][10], dstc[20];
544 char srca[3][10], dsta[20];
545 char argc[3][20];
546 char arga[3][20];
547 char flags[5], tmp[10];
548
549 for (j = 0; j < 3; ++j) {
550 int regc = code->alu.inst[i].inst1 >> (j * 6);
551 int rega = code->alu.inst[i].inst3 >> (j * 6);
552
553 sprintf(srcc[j], "%c%i",
554 (regc & 32) ? 'c' : 't', regc & 31);
555 sprintf(srca[j], "%c%i",
556 (rega & 32) ? 'c' : 't', rega & 31);
557 }
558
559 dstc[0] = 0;
560 sprintf(flags, "%s%s%s",
561 (code->alu.inst[i].
562 inst1 & R600_ALU_DSTC_REG_X) ? "x" : "",
563 (code->alu.inst[i].
564 inst1 & R600_ALU_DSTC_REG_Y) ? "y" : "",
565 (code->alu.inst[i].
566 inst1 & R600_ALU_DSTC_REG_Z) ? "z" : "");
567 if (flags[0] != 0) {
568 sprintf(dstc, "t%i.%s ",
569 (code->alu.inst[i].
570 inst1 >> R600_ALU_DSTC_SHIFT) & 31,
571 flags);
572 }
573 sprintf(flags, "%s%s%s",
574 (code->alu.inst[i].
575 inst1 & R600_ALU_DSTC_OUTPUT_X) ? "x" : "",
576 (code->alu.inst[i].
577 inst1 & R600_ALU_DSTC_OUTPUT_Y) ? "y" : "",
578 (code->alu.inst[i].
579 inst1 & R600_ALU_DSTC_OUTPUT_Z) ? "z" : "");
580 if (flags[0] != 0) {
581 sprintf(tmp, "o%i.%s",
582 (code->alu.inst[i].
583 inst1 >> R600_ALU_DSTC_SHIFT) & 31,
584 flags);
585 strcat(dstc, tmp);
586 }
587
588 dsta[0] = 0;
589 if (code->alu.inst[i].inst3 & R600_ALU_DSTA_REG) {
590 sprintf(dsta, "t%i.w ",
591 (code->alu.inst[i].
592 inst3 >> R600_ALU_DSTA_SHIFT) & 31);
593 }
594 if (code->alu.inst[i].inst3 & R600_ALU_DSTA_OUTPUT) {
595 sprintf(tmp, "o%i.w ",
596 (code->alu.inst[i].
597 inst3 >> R600_ALU_DSTA_SHIFT) & 31);
598 strcat(dsta, tmp);
599 }
600 if (code->alu.inst[i].inst3 & R600_ALU_DSTA_DEPTH) {
601 strcat(dsta, "Z");
602 }
603
604 fprintf(stderr,
605 "%3i: xyz: %3s %3s %3s -> %-20s (%08x)\n"
606 " w: %3s %3s %3s -> %-20s (%08x)\n", i,
607 srcc[0], srcc[1], srcc[2], dstc,
608 code->alu.inst[i].inst1, srca[0], srca[1],
609 srca[2], dsta, code->alu.inst[i].inst3);
610
611 for (j = 0; j < 3; ++j) {
612 int regc = code->alu.inst[i].inst0 >> (j * 7);
613 int rega = code->alu.inst[i].inst2 >> (j * 7);
614 int d;
615 char buf[20];
616
617 d = regc & 31;
618 if (d < 12) {
619 switch (d % 4) {
620 case R600_ALU_ARGC_SRC0C_XYZ:
621 sprintf(buf, "%s.xyz",
622 srcc[d / 4]);
623 break;
624 case R600_ALU_ARGC_SRC0C_XXX:
625 sprintf(buf, "%s.xxx",
626 srcc[d / 4]);
627 break;
628 case R600_ALU_ARGC_SRC0C_YYY:
629 sprintf(buf, "%s.yyy",
630 srcc[d / 4]);
631 break;
632 case R600_ALU_ARGC_SRC0C_ZZZ:
633 sprintf(buf, "%s.zzz",
634 srcc[d / 4]);
635 break;
636 }
637 } else if (d < 15) {
638 sprintf(buf, "%s.www", srca[d - 12]);
639 } else if (d == 20) {
640 sprintf(buf, "0.0");
641 } else if (d == 21) {
642 sprintf(buf, "1.0");
643 } else if (d == 22) {
644 sprintf(buf, "0.5");
645 } else if (d >= 23 && d < 32) {
646 d -= 23;
647 switch (d / 3) {
648 case 0:
649 sprintf(buf, "%s.yzx",
650 srcc[d % 3]);
651 break;
652 case 1:
653 sprintf(buf, "%s.zxy",
654 srcc[d % 3]);
655 break;
656 case 2:
657 sprintf(buf, "%s.Wzy",
658 srcc[d % 3]);
659 break;
660 }
661 } else {
662 sprintf(buf, "%i", d);
663 }
664
665 sprintf(argc[j], "%s%s%s%s",
666 (regc & 32) ? "-" : "",
667 (regc & 64) ? "|" : "",
668 buf, (regc & 64) ? "|" : "");
669
670 d = rega & 31;
671 if (d < 9) {
672 sprintf(buf, "%s.%c", srcc[d / 3],
673 'x' + (char)(d % 3));
674 } else if (d < 12) {
675 sprintf(buf, "%s.w", srca[d - 9]);
676 } else if (d == 16) {
677 sprintf(buf, "0.0");
678 } else if (d == 17) {
679 sprintf(buf, "1.0");
680 } else if (d == 18) {
681 sprintf(buf, "0.5");
682 } else {
683 sprintf(buf, "%i", d);
684 }
685
686 sprintf(arga[j], "%s%s%s%s",
687 (rega & 32) ? "-" : "",
688 (rega & 64) ? "|" : "",
689 buf, (rega & 64) ? "|" : "");
690 }
691
692 fprintf(stderr, " xyz: %8s %8s %8s op: %08x\n"
693 " w: %8s %8s %8s op: %08x\n",
694 argc[0], argc[1], argc[2],
695 code->alu.inst[i].inst0, arga[0], arga[1],
696 arga[2], code->alu.inst[i].inst2);
697 }
698 }
699 }