src/mesa/drivers/dri/r600/r600_ioctl.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.
   3 Copyright (C) 2004 Nicolai Haehnle.
   4 All Rights Reserved.
   5
   6 The Weather Channel (TM) funded Tungsten Graphics to develop the
   7 initial release of the Radeon 8500 driver under the XFree86 license.
   8 This notice must be preserved.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining
  11 a copy of this software and associated documentation files (the
  12 "Software"), to deal in the Software without restriction, including
  13 without limitation the rights to use, copy, modify, merge, publish,
  14 distribute, sublicense, and/or sell copies of the Software, and to
  15 permit persons to whom the Software is furnished to do so, subject to
  16 the following conditions:
  17
  18 The above copyright notice and this permission notice (including the
  19 next paragraph) shall be included in all copies or substantial
  20 portions of the Software.
  21
  22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  29
  30 **************************************************************************/
  31
  32 /**
  33  * \file
  34  *
  35  * \author Keith Whitwell <keith@tungstengraphics.com>
  36  *
  37  * \author Nicolai Haehnle <prefect_@gmx.net>
  38  */
  39
  40 #include <sched.h>
  41 #include <errno.h>
  42
  43 #include "main/glheader.h"
  44 #include "main/imports.h"
  45 #include "main/macros.h"
  46 #include "main/context.h"
  47 #include "swrast/swrast.h"
  48
  49 #include "radeon_common.h"
  50 #include "radeon_lock.h"
  51 #include "r600_context.h"
  52 #include "r600_ioctl.h"
  53 #include "r600_cmdbuf.h"
  54 #include "r600_state.h"
  55 #include "r600_vertprog.h"
  56 #include "radeon_reg.h"
  57 #include "r600_emit.h"
  58 #include "r600_fragprog.h"
  59 #include "r600_context.h"
  60
  61 #include "vblank.h"
  62
  63 #define R200_3D_DRAW_IMMD_2      0xC0003500
  64
  65 #define CLEARBUFFER_COLOR       0x1
  66 #define CLEARBUFFER_DEPTH       0x2
  67 #define CLEARBUFFER_STENCIL     0x4
  68
  69 static void r600EmitClearState(GLcontext * ctx);
  70
  71 static void r600UserClear(GLcontext *ctx, GLuint mask)
  72 {
  73         radeon_clear_tris(ctx, mask);
  74 }
  75
  76 static void r600ClearBuffer(r600ContextPtr r600, int flags,
  77                             struct radeon_renderbuffer *rrb,
  78                             struct radeon_renderbuffer *rrbd)
  79 {
  80         BATCH_LOCALS(&r600->radeon);
  81         GLcontext *ctx = r600->radeon.glCtx;
  82         __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
  83         GLuint cbpitch = 0;
  84         r600ContextPtr rmesa = r600;
  85
  86         if (RADEON_DEBUG & DEBUG_IOCTL)
  87                 fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
  88                         __FUNCTION__, rrb, dPriv->x, dPriv->y,
  89                         dPriv->w, dPriv->h);
  90
  91         if (rrb) {
  92                 cbpitch = (rrb->pitch / rrb->cpp);
  93                 if (rrb->cpp == 4)
  94                         cbpitch |= R600_COLOR_FORMAT_ARGB8888;
  95                 else
  96                         cbpitch |= R600_COLOR_FORMAT_RGB565;
  97
  98                 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
  99                         cbpitch |= R600_COLOR_TILE_ENABLE;
 100         }
 101         }
 102
 103         /* TODO in bufmgr */
 104         cp_wait(&r600->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 105         end_3d(&rmesa->radeon);
 106
 107         if (flags & CLEARBUFFER_COLOR) {
 108                 assert(rrb != 0);
 109                 BEGIN_BATCH_NO_AUTOSTATE(6);
 110                 OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1);
 111                 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 112                 OUT_BATCH_REGVAL(R600_RB3D_COLORPITCH0, cbpitch);
 113                 END_BATCH();
 114         }
 115 #if 1
 116         if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
 117                 assert(rrbd != 0);
 118                 cbpitch = (rrbd->pitch / rrbd->cpp);
 119                 if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
 120                         cbpitch |= R600_DEPTHMACROTILE_ENABLE;
 121         }
 122                 if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
 123             cbpitch |= R600_DEPTHMICROTILE_TILED;
 124         }
 125                 BEGIN_BATCH_NO_AUTOSTATE(6);
 126                 OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1);
 127                 OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 128                 OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, cbpitch);
 129                 END_BATCH();
 130         }
 131 #endif
 132         BEGIN_BATCH_NO_AUTOSTATE(6);
 133         OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1);
 134         if (flags & CLEARBUFFER_COLOR) {
 135                 OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
 136                           (ctx->Color.ColorMask[GCOMP] ? RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 : 0) |
 137                           (ctx->Color.ColorMask[RCOMP] ? RB3D_COLOR_CHANNEL_MASK_RED_MASK0 : 0) |
 138                           (ctx->Color.ColorMask[ACOMP] ? RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 : 0));
 139         } else {
 140                 OUT_BATCH(0);
 141         }
 142
 143
 144         {
 145                 uint32_t t1, t2;
 146
 147                 t1 = 0x0;
 148                 t2 = 0x0;
 149
 150                 if (flags & CLEARBUFFER_DEPTH) {
 151                         t1 |= R600_Z_ENABLE | R600_Z_WRITE_ENABLE;
 152                         t2 |=
 153                             (R600_ZS_ALWAYS << R600_Z_FUNC_SHIFT);
 154                 }
 155
 156                 if (flags & CLEARBUFFER_STENCIL) {
 157                         t1 |= R600_STENCIL_ENABLE;
 158                         t2 |=
 159                             (R600_ZS_ALWAYS <<
 160                              R600_S_FRONT_FUNC_SHIFT) |
 161                             (R600_ZS_REPLACE <<
 162                              R600_S_FRONT_SFAIL_OP_SHIFT) |
 163                             (R600_ZS_REPLACE <<
 164                              R600_S_FRONT_ZPASS_OP_SHIFT) |
 165                             (R600_ZS_REPLACE <<
 166                              R600_S_FRONT_ZFAIL_OP_SHIFT);
 167                 }
 168
 169                 OUT_BATCH_REGSEQ(R600_ZB_CNTL, 3);
 170                 OUT_BATCH(t1);
 171                 OUT_BATCH(t2);
 172                 OUT_BATCH(((ctx->Stencil.WriteMask[0] & R600_STENCILREF_MASK) <<
 173                    R600_STENCILWRITEMASK_SHIFT) |
 174                           (ctx->Stencil.Clear & R600_STENCILREF_MASK));
 175                 END_BATCH();
 176         }
 177
 178         if (!rmesa->radeon.radeonScreen->kernel_mm) {
 179                 BEGIN_BATCH_NO_AUTOSTATE(9);
 180                 OUT_BATCH(cmdpacket3(r600->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
 181                 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
 182                 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
 183                 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
 184                 OUT_BATCH_FLOAT32(1.0);
 185                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
 186                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
 187                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
 188                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
 189                 END_BATCH();
 190         } else {
 191                 OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
 192                 OUT_BATCH(R600_PRIM_TYPE_POINT | R600_PRIM_WALK_RING |
 193                           (1 << R600_PRIM_NUM_VERTICES_SHIFT));
 194                 OUT_BATCH_FLOAT32(dPriv->w / 2.0);
 195                 OUT_BATCH_FLOAT32(dPriv->h / 2.0);
 196                 OUT_BATCH_FLOAT32(ctx->Depth.Clear);
 197                 OUT_BATCH_FLOAT32(1.0);
 198                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
 199                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
 200                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
 201                 OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
 202         }
 203
 204         r600EmitCacheFlush(rmesa);
 205         cp_wait(&r600->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 206
 207         R600_STATECHANGE(r600, cb);
 208         R600_STATECHANGE(r600, cmk);
 209         R600_STATECHANGE(r600, zs);
 210 }
 211
 212 static void r600EmitClearState(GLcontext * ctx)
 213 {
 214         r600ContextPtr r600 = R600_CONTEXT(ctx);
 215         BATCH_LOCALS(&r600->radeon);
 216         __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
 217         int i;
 218         GLuint vap_cntl;
 219
 220         /* State atom dirty tracking is a little subtle here.
 221          *
 222          * On the one hand, we need to make sure base state is emitted
 223          * here if we start with an empty batch buffer, otherwise clear
 224          * works incorrectly with multiple processes. Therefore, the first
 225          * BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
 226          *
 227          * On the other hand, implicit state emission clears the state atom
 228          * dirty bits, so we have to call R600_STATECHANGE later than the
 229          * first BEGIN_BATCH.
 230          *
 231          * The final trickiness is that, because we change state, we need
 232          * to ensure that any stored swtcl primitives are flushed properly
 233          * before we start changing state. See the R600_NEWPRIM in r600Clear
 234          * for this.
 235          */
 236         BEGIN_BATCH(31);
 237         OUT_BATCH_REGSEQ(R600_VAP_PROG_STREAM_CNTL_0, 1);
 238
 239         OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) |
 240                    ((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT)));
 241
 242         OUT_BATCH_REGVAL(R600_FG_FOG_BLEND, 0);
 243         OUT_BATCH_REGVAL(R600_VAP_PROG_STREAM_CNTL_EXT_0,
 244            ((((R600_SWIZZLE_SELECT_X << R600_SWIZZLE_SELECT_X_SHIFT) |
 245                (R600_SWIZZLE_SELECT_Y << R600_SWIZZLE_SELECT_Y_SHIFT) |
 246                (R600_SWIZZLE_SELECT_Z << R600_SWIZZLE_SELECT_Z_SHIFT) |
 247                (R600_SWIZZLE_SELECT_W << R600_SWIZZLE_SELECT_W_SHIFT) |
 248                ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT))
 249               << R600_SWIZZLE0_SHIFT) |
 250              (((R600_SWIZZLE_SELECT_X << R600_SWIZZLE_SELECT_X_SHIFT) |
 251                (R600_SWIZZLE_SELECT_Y << R600_SWIZZLE_SELECT_Y_SHIFT) |
 252                (R600_SWIZZLE_SELECT_Z << R600_SWIZZLE_SELECT_Z_SHIFT) |
 253                (R600_SWIZZLE_SELECT_W << R600_SWIZZLE_SELECT_W_SHIFT) |
 254                ((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT))
 255               << R600_SWIZZLE1_SHIFT)));
 256
 257         /* R600_VAP_INPUT_CNTL_0, R600_VAP_INPUT_CNTL_1 */
 258         OUT_BATCH_REGSEQ(R600_VAP_VTX_STATE_CNTL, 2);
 259         OUT_BATCH((R600_SEL_USER_COLOR_0 << R600_COLOR_0_ASSEMBLY_SHIFT));
 260         OUT_BATCH(R600_INPUT_CNTL_POS | R600_INPUT_CNTL_COLOR | R600_INPUT_CNTL_TC0);
 261
 262         /* comes from fglrx startup of clear */
 263         OUT_BATCH_REGSEQ(R600_SE_VTE_CNTL, 2);
 264         OUT_BATCH(R600_VTX_W0_FMT | R600_VPORT_X_SCALE_ENA |
 265                   R600_VPORT_X_OFFSET_ENA | R600_VPORT_Y_SCALE_ENA |
 266                   R600_VPORT_Y_OFFSET_ENA | R600_VPORT_Z_SCALE_ENA |
 267                   R600_VPORT_Z_OFFSET_ENA);
 268         OUT_BATCH(0x8);
 269
 270         OUT_BATCH_REGVAL(R600_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
 271
 272         OUT_BATCH_REGSEQ(R600_VAP_OUTPUT_VTX_FMT_0, 2);
 273         OUT_BATCH(R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
 274                   R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
 275         OUT_BATCH(0); /* no textures */
 276
 277         OUT_BATCH_REGVAL(R600_TX_ENABLE, 0);
 278
 279         OUT_BATCH_REGSEQ(R600_SE_VPORT_XSCALE, 6);
 280         OUT_BATCH_FLOAT32(1.0);
 281         OUT_BATCH_FLOAT32(dPriv->x);
 282         OUT_BATCH_FLOAT32(1.0);
 283         OUT_BATCH_FLOAT32(dPriv->y);
 284         OUT_BATCH_FLOAT32(1.0);
 285         OUT_BATCH_FLOAT32(0.0);
 286
 287         OUT_BATCH_REGVAL(R600_FG_ALPHA_FUNC, 0);
 288
 289         OUT_BATCH_REGSEQ(R600_RB3D_CBLEND, 2);
 290         OUT_BATCH(0x0);
 291         OUT_BATCH(0x0);
 292         END_BATCH();
 293
 294         R600_STATECHANGE(r600, vir[0]);
 295         R600_STATECHANGE(r600, fogs);
 296         R600_STATECHANGE(r600, vir[1]);
 297         R600_STATECHANGE(r600, vic);
 298         R600_STATECHANGE(r600, vte);
 299         R600_STATECHANGE(r600, vof);
 300         R600_STATECHANGE(r600, txe);
 301         R600_STATECHANGE(r600, vpt);
 302         R600_STATECHANGE(r600, at);
 303         R600_STATECHANGE(r600, bld);
 304         R600_STATECHANGE(r600, ps);
 305
 306         R600_STATECHANGE(r600, vap_clip_cntl);
 307
 308         BEGIN_BATCH_NO_AUTOSTATE(2);
 309         OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE);
 310         END_BATCH();
 311
 312         BEGIN_BATCH_NO_AUTOSTATE(2);
 313         OUT_BATCH_REGVAL(R600_GA_POINT_SIZE,
 314                 ((dPriv->w * 6) << R600_POINTSIZE_X_SHIFT) |
 315                 ((dPriv->h * 6) << R600_POINTSIZE_Y_SHIFT));
 316         END_BATCH();
 317
 318
 319         R600_STATECHANGE(r600, ri);
 320         R600_STATECHANGE(r600, rc);
 321         R600_STATECHANGE(r600, rr);
 322
 323         BEGIN_BATCH(14);
 324         OUT_BATCH_REGSEQ(R600_RS_IP_0, 8);
 325         for (i = 0; i < 8; ++i)
 326                 OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3));
 327
 328         OUT_BATCH_REGSEQ(R600_RS_COUNT, 2);
 329         OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN);
 330         OUT_BATCH(0x0);
 331
 332         OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE);
 333         END_BATCH();
 334
 335         R600_STATECHANGE(r600, fp);
 336         R600_STATECHANGE(r600, fpi[0]);
 337         R600_STATECHANGE(r600, fpi[1]);
 338         R600_STATECHANGE(r600, fpi[2]);
 339         R600_STATECHANGE(r600, fpi[3]);
 340
 341         BEGIN_BATCH(17);
 342         OUT_BATCH_REGSEQ(R600_US_CONFIG, 3);
 343         OUT_BATCH(0x0);
 344         OUT_BATCH(0x0);
 345         OUT_BATCH(0x0);
 346         OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4);
 347         OUT_BATCH(0x0);
 348         OUT_BATCH(0x0);
 349         OUT_BATCH(0x0);
 350         OUT_BATCH(R600_RGBA_OUT);
 351
 352         OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0,
 353                          FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
 354         OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0,
 355                          FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
 356         OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0,
 357                          FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
 358         OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0,
 359                          FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
 360         END_BATCH();
 361
 362         BEGIN_BATCH(2);
 363         OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
 364         END_BATCH();
 365
 366         vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
 367                     (5 << R600_PVS_NUM_CNTLRS_SHIFT) |
 368                     (12 << R600_VF_MAX_VTX_NUM_SHIFT));
 369
 370         if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
 371                 vap_cntl |= (2 << R600_PVS_NUM_FPUS_SHIFT);
 372         else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
 373                  (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
 374                  (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
 375                 vap_cntl |= (5 << R600_PVS_NUM_FPUS_SHIFT);
 376         else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
 377                  (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
 378                 vap_cntl |= (6 << R600_PVS_NUM_FPUS_SHIFT);
 379         else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
 380                  (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
 381                 vap_cntl |= (8 << R600_PVS_NUM_FPUS_SHIFT);
 382         else
 383                 vap_cntl |= (4 << R600_PVS_NUM_FPUS_SHIFT);
 384
 385         R600_STATECHANGE(r600, vap_cntl);
 386
 387         BEGIN_BATCH(2);
 388         OUT_BATCH_REGVAL(R600_VAP_CNTL, vap_cntl);
 389         END_BATCH();
 390
 391         {
 392                 struct radeon_state_atom vpu;
 393                 uint32_t _cmd[10];
 394                 R600_STATECHANGE(r600, pvs);
 395                 R600_STATECHANGE(r600, vpi);
 396
 397                 BEGIN_BATCH(4);
 398                 OUT_BATCH_REGSEQ(R600_VAP_PVS_CODE_CNTL_0, 3);
 399                 OUT_BATCH((0 << R600_PVS_FIRST_INST_SHIFT) |
 400                           (0 << R600_PVS_XYZW_VALID_INST_SHIFT) |
 401                           (1 << R600_PVS_LAST_INST_SHIFT));
 402                 OUT_BATCH((0 << R600_PVS_CONST_BASE_OFFSET_SHIFT) |
 403                           (0 << R600_PVS_MAX_CONST_ADDR_SHIFT));
 404                 OUT_BATCH(1 << R600_PVS_LAST_VTX_SRC_INST_SHIFT);
 405                 END_BATCH();
 406
 407                 vpu.check = check_vpu;
 408                 vpu.cmd = _cmd;
 409                 vpu.cmd[0] = cmdvpu(r600->radeon.radeonScreen, 0, 2);
 410
 411                 vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
 412                                          0, 0xf, PVS_DST_REG_OUT);
 413                 vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y,
 414                                       PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W,
 415                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 416                 vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0,
 417                                       PVS_SRC_SELECT_FORCE_0,
 418                                       PVS_SRC_SELECT_FORCE_0,
 419                                       PVS_SRC_SELECT_FORCE_0,
 420                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 421                 vpu.cmd[4] = 0x0;
 422
 423                 vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf,
 424                                          PVS_DST_REG_OUT);
 425                 vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
 426                                       PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
 427                                       PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
 428
 429                                       VSF_FLAG_NONE);
 430                 vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
 431                                       PVS_SRC_SELECT_FORCE_0,
 432                                       PVS_SRC_SELECT_FORCE_0,
 433                                       PVS_SRC_SELECT_FORCE_0,
 434                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
 435                 vpu.cmd[8] = 0x0;
 436
 437                 r600->vap_flush_needed = GL_TRUE;
 438                 emit_vpu(ctx, &vpu);
 439         }
 440 }
 441
 442 static void r600KernelClear(GLcontext *ctx, GLuint flags)
 443 {
 444         r600ContextPtr r600 = R600_CONTEXT(ctx);
 445         __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
 446         struct radeon_framebuffer *rfb = dPriv->driverPrivate;
 447         struct radeon_renderbuffer *rrb;
 448         struct radeon_renderbuffer *rrbd;
 449         int bits = 0;
 450
 451         /* Make sure it fits there. */
 452         rcommonEnsureCmdBufSpace(&r600->radeon, 421 * 3, __FUNCTION__);
 453         if (flags || bits)
 454                 r600EmitClearState(ctx);
 455         rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
 456         if (rrbd && (flags & BUFFER_BIT_DEPTH))
 457                 bits |= CLEARBUFFER_DEPTH;
 458
 459         if (rrbd && (flags & BUFFER_BIT_STENCIL))
 460                 bits |= CLEARBUFFER_STENCIL;
 461
 462         if (flags & BUFFER_BIT_COLOR0) {
 463                 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
 464                 r600ClearBuffer(r600, CLEARBUFFER_COLOR, rrb, NULL);
 465                 bits = 0;
 466         }
 467
 468         if (flags & BUFFER_BIT_FRONT_LEFT) {
 469                 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
 470                 r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd);
 471                 bits = 0;
 472         }
 473
 474         if (flags & BUFFER_BIT_BACK_LEFT) {
 475                 rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
 476                 r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd);
 477                 bits = 0;
 478         }
 479
 480         if (bits)
 481                 r600ClearBuffer(r600, bits, NULL, rrbd);
 482
 483         COMMIT_BATCH();
 484 }
 485
 486 /**
 487  * Buffer clear
 488  */
 489 static void r600Clear(GLcontext * ctx, GLbitfield mask)
 490 {
 491         r600ContextPtr r600 = R600_CONTEXT(ctx);
 492         __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
 493         const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
 494         GLbitfield swrast_mask = 0, tri_mask = 0;
 495         int i;
 496         struct gl_framebuffer *fb = ctx->DrawBuffer;
 497
 498         if (RADEON_DEBUG & DEBUG_IOCTL)
 499                 fprintf(stderr, "r600Clear\n");
 500
 501         if (!r600->radeon.radeonScreen->driScreen->dri2.enabled) {
 502                 LOCK_HARDWARE(&r600->radeon);
 503                 UNLOCK_HARDWARE(&r600->radeon);
 504                 if (dPriv->numClipRects == 0)
 505                         return;
 506         }
 507
 508         /* Flush swtcl vertices if necessary, because we will change hardware
 509          * state during clear. See also the state-related comment in
 510          * r600EmitClearState.
 511          */
 512         R600_NEWPRIM(r600);
 513
 514         if (colorMask == ~0)
 515           tri_mask |= (mask & BUFFER_BITS_COLOR);
 516
 517
 518         /* HW stencil */
 519         if (mask & BUFFER_BIT_STENCIL) {
 520                 tri_mask |= BUFFER_BIT_STENCIL;
 521         }
 522
 523         /* HW depth */
 524         if (mask & BUFFER_BIT_DEPTH) {
 525                 tri_mask |= BUFFER_BIT_DEPTH;
 526         }
 527
 528         /* If we're doing a tri pass for depth/stencil, include a likely color
 529          * buffer with it.
 530          */
 531
 532         for (i = 0; i < BUFFER_COUNT; i++) {
 533           GLuint bufBit = 1 << i;
 534           if ((tri_mask) & bufBit) {
 535             if (!fb->Attachment[i].Renderbuffer->ClassID) {
 536               tri_mask &= ~bufBit;
 537               swrast_mask |= bufBit;
 538             }
 539           }
 540         }
 541
 542         /* SW fallback clearing */
 543         swrast_mask = mask & ~tri_mask;
 544
 545         if (tri_mask) {
 546                 if (r600->radeon.radeonScreen->kernel_mm)
 547                         r600UserClear(ctx, tri_mask);
 548                 else
 549                         r600KernelClear(ctx, tri_mask);
 550         }
 551         if (swrast_mask) {
 552                 if (RADEON_DEBUG & DEBUG_FALLBACKS)
 553                         fprintf(stderr, "%s: swrast clear, mask: %x\n",
 554                                 __FUNCTION__, swrast_mask);
 555                 _swrast_Clear(ctx, swrast_mask);
 556         }
 557 }
 558
 559
 560 void r600InitIoctlFuncs(struct dd_function_table *functions)
 561 {
 562         functions->Clear = r600Clear;
 563         functions->Finish = radeonFinish;
 564         functions->Flush = radeonFlush;
 565 }