src/mesa/drivers/dri/r600/r600_reg.h

   1 /*
   2  * RadeonHD R6xx, R7xx Register documentation
   3  *
   4  * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
   5  * Copyright (C) 2008-2009  Matthias Hopf
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included
  15  * in all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  21  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef _R600_REG_H_
  26 #define _R600_REG_H_
  27
  28 /*
  29  * Register definitions
  30  */
  31
  32 #include "r600_reg_auto_r6xx.h"
  33 #include "r600_reg_r6xx.h"
  34 #include "r600_reg_r7xx.h"
  35
  36
  37 /* SET_*_REG offsets + ends */
  38 enum
  39 {
  40     SET_CONFIG_REG_offset                = 0x00008000,
  41     SET_CONFIG_REG_end                   = 0x0000ac00,
  42     SET_CONTEXT_REG_offset               = 0x00028000,
  43     SET_CONTEXT_REG_end                  = 0x00029000,
  44     SET_ALU_CONST_offset                 = 0x00030000,
  45     SET_ALU_CONST_end                    = 0x00032000,
  46     SET_RESOURCE_offset                  = 0x00038000,
  47     SET_RESOURCE_end                     = 0x0003c000,
  48     SET_SAMPLER_offset                   = 0x0003c000,
  49     SET_SAMPLER_end                      = 0x0003cff0,
  50     SET_CTL_CONST_offset                 = 0x0003cff0,
  51     SET_CTL_CONST_end                    = 0x0003e200,
  52     SET_LOOP_CONST_offset                = 0x0003e200,
  53     SET_LOOP_CONST_end                   = 0x0003e380,
  54     SET_BOOL_CONST_offset                = 0x0003e380,
  55     SET_BOOL_CONST_end                   = 0x00040000,
  56 };
  57
  58 /* packet3 IT_SURFACE_BASE_UPDATE bits */
  59 enum
  60 {
  61     DEPTH_BASE                           = (1 << 0),
  62     COLOR0_BASE                          = (1 << 1),
  63     COLOR1_BASE                          = (1 << 2),
  64     COLOR2_BASE                          = (1 << 3),
  65     COLOR3_BASE                          = (1 << 4),
  66     COLOR4_BASE                          = (1 << 5),
  67     COLOR5_BASE                          = (1 << 6),
  68     COLOR6_BASE                          = (1 << 7),
  69     COLOR7_BASE                          = (1 << 8),
  70     STRMOUT_BASE0                        = (1 << 9),
  71     STRMOUT_BASE1                        = (1 << 10),
  72     STRMOUT_BASE2                        = (1 << 11),
  73     STRMOUT_BASE3                        = (1 << 12),
  74     COHER_BASE0                          = (1 << 13),
  75     COHER_BASE1                          = (1 << 14),
  76 };
  77
  78 /* Packet3 commands */
  79 enum
  80 {
  81     IT_NOP                               = 0x10,
  82     IT_INDIRECT_BUFFER_END               = 0x17,
  83     IT_SET_PREDICATION                   = 0x20,
  84     IT_REG_RMW                           = 0x21,
  85     IT_COND_EXEC                         = 0x22,
  86     IT_PRED_EXEC                         = 0x23,
  87     IT_START_3D_CMDBUF                   = 0x24,
  88     IT_DRAW_INDEX_2                      = 0x27,
  89     IT_CONTEXT_CONTROL                   = 0x28,
  90     IT_DRAW_INDEX_IMMD_BE                = 0x29,
  91     IT_INDEX_TYPE                        = 0x2A,
  92     IT_DRAW_INDEX                        = 0x2B,
  93     IT_DRAW_INDEX_AUTO                   = 0x2D,
  94     IT_DRAW_INDEX_IMMD                   = 0x2E,
  95     IT_NUM_INSTANCES                     = 0x2F,
  96     IT_STRMOUT_BUFFER_UPDATE             = 0x34,
  97     IT_INDIRECT_BUFFER_MP                = 0x38,
  98     IT_MEM_SEMAPHORE                     = 0x39,
  99     IT_MPEG_INDEX                        = 0x3A,
 100     IT_WAIT_REG_MEM                      = 0x3C,
 101     IT_MEM_WRITE                         = 0x3D,
 102     IT_INDIRECT_BUFFER                   = 0x32,
 103     IT_CP_INTERRUPT                      = 0x40,
 104     IT_SURFACE_SYNC                      = 0x43,
 105     IT_ME_INITIALIZE                     = 0x44,
 106     IT_COND_WRITE                        = 0x45,
 107     IT_EVENT_WRITE                       = 0x46,
 108     IT_EVENT_WRITE_EOP                   = 0x47,
 109     IT_ONE_REG_WRITE                     = 0x57,
 110     IT_SET_CONFIG_REG                    = 0x68,
 111     IT_SET_CONTEXT_REG                   = 0x69,
 112     IT_SET_ALU_CONST                     = 0x6A,
 113     IT_SET_BOOL_CONST                    = 0x6B,
 114     IT_SET_LOOP_CONST                    = 0x6C,
 115     IT_SET_RESOURCE                      = 0x6D,
 116     IT_SET_SAMPLER                       = 0x6E,
 117     IT_SET_CTL_CONST                     = 0x6F,
 118     IT_SURFACE_BASE_UPDATE               = 0x73,
 119 };
 120
 121 #endif