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Merge branch 'mesa_7_5_branch'
[mesa.git] / src / mesa / drivers / dri / r600 / r600_reg_auto_r6xx.h
1 /*
2 * RadeonHD R6xx, R7xx Register documentation
3 *
4 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008-2009 Matthias Hopf
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef _AUTOREGS
26 #define _AUTOREGS
27
28 enum {
29
30 VGT_VTX_VECT_EJECT_REG = 0x000088b0,
31 PRIM_COUNT_mask = 0x3ff << 0,
32 PRIM_COUNT_shift = 0,
33 VGT_LAST_COPY_STATE = 0x000088c0,
34 SRC_STATE_ID_mask = 0x07 << 0,
35 SRC_STATE_ID_shift = 0,
36 DST_STATE_ID_mask = 0x07 << 16,
37 DST_STATE_ID_shift = 16,
38 VGT_CACHE_INVALIDATION = 0x000088c4,
39 CACHE_INVALIDATION_mask = 0x03 << 0,
40 CACHE_INVALIDATION_shift = 0,
41 VC_ONLY = 0x00,
42 TC_ONLY = 0x01,
43 VC_AND_TC = 0x02,
44 VS_NO_EXTRA_BUFFER_bit = 1 << 5,
45 VGT_GS_PER_ES = 0x000088c8,
46 VGT_ES_PER_GS = 0x000088cc,
47 VGT_GS_VERTEX_REUSE = 0x000088d4,
48 VERT_REUSE_mask = 0x1f << 0,
49 VERT_REUSE_shift = 0,
50 VGT_MC_LAT_CNTL = 0x000088d8,
51 MC_TIME_STAMP_RES_mask = 0x03 << 0,
52 MC_TIME_STAMP_RES_shift = 0,
53 X_0_992_MAX_LATENCY = 0x00,
54 X_0_496_MAX_LATENCY = 0x01,
55 X_0_248_MAX_LATENCY = 0x02,
56 X_0_124_MAX_LATENCY = 0x03,
57 VGT_GS_PER_VS = 0x000088e8,
58 GS_PER_VS_mask = 0x0f << 0,
59 GS_PER_VS_shift = 0,
60 VGT_CNTL_STATUS = 0x000088f0,
61 VGT_OUT_INDX_BUSY_bit = 1 << 0,
62 VGT_OUT_BUSY_bit = 1 << 1,
63 VGT_PT_BUSY_bit = 1 << 2,
64 VGT_TE_BUSY_bit = 1 << 3,
65 VGT_VR_BUSY_bit = 1 << 4,
66 VGT_GRP_BUSY_bit = 1 << 5,
67 VGT_DMA_REQ_BUSY_bit = 1 << 6,
68 VGT_DMA_BUSY_bit = 1 << 7,
69 VGT_GS_BUSY_bit = 1 << 8,
70 VGT_BUSY_bit = 1 << 9,
71 VGT_PRIMITIVE_TYPE = 0x00008958,
72 VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0,
73 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0,
74 DI_PT_NONE = 0x00,
75 DI_PT_POINTLIST = 0x01,
76 DI_PT_LINELIST = 0x02,
77 DI_PT_LINESTRIP = 0x03,
78 DI_PT_TRILIST = 0x04,
79 DI_PT_TRIFAN = 0x05,
80 DI_PT_TRISTRIP = 0x06,
81 DI_PT_UNUSED_0 = 0x07,
82 DI_PT_UNUSED_1 = 0x08,
83 DI_PT_UNUSED_2 = 0x09,
84 DI_PT_LINELIST_ADJ = 0x0a,
85 DI_PT_LINESTRIP_ADJ = 0x0b,
86 DI_PT_TRILIST_ADJ = 0x0c,
87 DI_PT_TRISTRIP_ADJ = 0x0d,
88 DI_PT_UNUSED_3 = 0x0e,
89 DI_PT_UNUSED_4 = 0x0f,
90 DI_PT_TRI_WITH_WFLAGS = 0x10,
91 DI_PT_RECTLIST = 0x11,
92 DI_PT_LINELOOP = 0x12,
93 DI_PT_QUADLIST = 0x13,
94 DI_PT_QUADSTRIP = 0x14,
95 DI_PT_POLYGON = 0x15,
96 DI_PT_2D_COPY_RECT_LIST_V0 = 0x16,
97 DI_PT_2D_COPY_RECT_LIST_V1 = 0x17,
98 DI_PT_2D_COPY_RECT_LIST_V2 = 0x18,
99 DI_PT_2D_COPY_RECT_LIST_V3 = 0x19,
100 DI_PT_2D_FILL_RECT_LIST = 0x1a,
101 DI_PT_2D_LINE_STRIP = 0x1b,
102 DI_PT_2D_TRI_STRIP = 0x1c,
103 VGT_INDEX_TYPE = 0x0000895c,
104 INDEX_TYPE_mask = 0x03 << 0,
105 INDEX_TYPE_shift = 0,
106 DI_INDEX_SIZE_16_BIT = 0x00,
107 DI_INDEX_SIZE_32_BIT = 0x01,
108 VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960,
109 VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964,
110 VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968,
111 VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c,
112 VGT_NUM_INDICES = 0x00008970,
113 VGT_NUM_INSTANCES = 0x00008974,
114 PA_CL_CNTL_STATUS = 0x00008a10,
115 CL_BUSY_bit = 1 << 31,
116 PA_CL_ENHANCE = 0x00008a14,
117 CLIP_VTX_REORDER_ENA_bit = 1 << 0,
118 NUM_CLIP_SEQ_mask = 0x03 << 1,
119 NUM_CLIP_SEQ_shift = 1,
120 CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3,
121 VE_NAN_PROC_DISABLE_bit = 1 << 4,
122 PA_SU_CNTL_STATUS = 0x00008a50,
123 SU_BUSY_bit = 1 << 31,
124 PA_SC_LINE_STIPPLE_STATE = 0x00008b10,
125 CURRENT_PTR_mask = 0x0f << 0,
126 CURRENT_PTR_shift = 0,
127 CURRENT_COUNT_mask = 0xff << 8,
128 CURRENT_COUNT_shift = 8,
129 PA_SC_MULTI_CHIP_CNTL = 0x00008b20,
130 LOG2_NUM_CHIPS_mask = 0x07 << 0,
131 LOG2_NUM_CHIPS_shift = 0,
132 MULTI_CHIP_TILE_SIZE_mask = 0x03 << 3,
133 MULTI_CHIP_TILE_SIZE_shift = 3,
134 X_16_X_16_PIXEL_TILE_PER_CHIP = 0x00,
135 X_32_X_32_PIXEL_TILE_PER_CHIP = 0x01,
136 X_64_X_64_PIXEL_TILE_PER_CHIP = 0x02,
137 X_128X128_PIXEL_TILE_PER_CHIP = 0x03,
138 CHIP_TILE_X_LOC_mask = 0x07 << 5,
139 CHIP_TILE_X_LOC_shift = 5,
140 CHIP_TILE_Y_LOC_mask = 0x07 << 8,
141 CHIP_TILE_Y_LOC_shift = 8,
142 CHIP_SUPER_TILE_B_bit = 1 << 11,
143 PA_SC_AA_SAMPLE_LOCS_2S = 0x00008b40,
144 S0_X_mask = 0x0f << 0,
145 S0_X_shift = 0,
146 S0_Y_mask = 0x0f << 4,
147 S0_Y_shift = 4,
148 S1_X_mask = 0x0f << 8,
149 S1_X_shift = 8,
150 S1_Y_mask = 0x0f << 12,
151 S1_Y_shift = 12,
152 PA_SC_AA_SAMPLE_LOCS_4S = 0x00008b44,
153 /* S0_X_mask = 0x0f << 0, */
154 /* S0_X_shift = 0, */
155 /* S0_Y_mask = 0x0f << 4, */
156 /* S0_Y_shift = 4, */
157 /* S1_X_mask = 0x0f << 8, */
158 /* S1_X_shift = 8, */
159 /* S1_Y_mask = 0x0f << 12, */
160 /* S1_Y_shift = 12, */
161 S2_X_mask = 0x0f << 16,
162 S2_X_shift = 16,
163 S2_Y_mask = 0x0f << 20,
164 S2_Y_shift = 20,
165 S3_X_mask = 0x0f << 24,
166 S3_X_shift = 24,
167 S3_Y_mask = 0x0f << 28,
168 S3_Y_shift = 28,
169 PA_SC_AA_SAMPLE_LOCS_8S_WD0 = 0x00008b48,
170 /* S0_X_mask = 0x0f << 0, */
171 /* S0_X_shift = 0, */
172 /* S0_Y_mask = 0x0f << 4, */
173 /* S0_Y_shift = 4, */
174 /* S1_X_mask = 0x0f << 8, */
175 /* S1_X_shift = 8, */
176 /* S1_Y_mask = 0x0f << 12, */
177 /* S1_Y_shift = 12, */
178 /* S2_X_mask = 0x0f << 16, */
179 /* S2_X_shift = 16, */
180 /* S2_Y_mask = 0x0f << 20, */
181 /* S2_Y_shift = 20, */
182 /* S3_X_mask = 0x0f << 24, */
183 /* S3_X_shift = 24, */
184 /* S3_Y_mask = 0x0f << 28, */
185 /* S3_Y_shift = 28, */
186 PA_SC_AA_SAMPLE_LOCS_8S_WD1 = 0x00008b4c,
187 S4_X_mask = 0x0f << 0,
188 S4_X_shift = 0,
189 S4_Y_mask = 0x0f << 4,
190 S4_Y_shift = 4,
191 S5_X_mask = 0x0f << 8,
192 S5_X_shift = 8,
193 S5_Y_mask = 0x0f << 12,
194 S5_Y_shift = 12,
195 S6_X_mask = 0x0f << 16,
196 S6_X_shift = 16,
197 S6_Y_mask = 0x0f << 20,
198 S6_Y_shift = 20,
199 S7_X_mask = 0x0f << 24,
200 S7_X_shift = 24,
201 S7_Y_mask = 0x0f << 28,
202 S7_Y_shift = 28,
203 PA_SC_CNTL_STATUS = 0x00008be0,
204 MPASS_OVERFLOW_bit = 1 << 30,
205 PA_SC_ENHANCE = 0x00008bf0,
206 FORCE_EOV_MAX_CLK_CNT_mask = 0xfff << 0,
207 FORCE_EOV_MAX_CLK_CNT_shift = 0,
208 FORCE_EOV_MAX_TILE_CNT_mask = 0xfff << 12,
209 FORCE_EOV_MAX_TILE_CNT_shift = 12,
210 SQ_CONFIG = 0x00008c00,
211 VC_ENABLE_bit = 1 << 0,
212 EXPORT_SRC_C_bit = 1 << 1,
213 DX9_CONSTS_bit = 1 << 2,
214 ALU_INST_PREFER_VECTOR_bit = 1 << 3,
215 SQ_CONFIG__DX10_CLAMP_bit = 1 << 4,
216 ALU_PREFER_ONE_WATERFALL_bit = 1 << 5,
217 ALU_MAX_ONE_WATERFALL_bit = 1 << 6,
218 CLAUSE_SEQ_PRIO_mask = 0x03 << 8,
219 CLAUSE_SEQ_PRIO_shift = 8,
220 SQ_CL_PRIO_RND_ROBIN = 0x00,
221 SQ_CL_PRIO_MACRO_SEQ = 0x01,
222 SQ_CL_PRIO_NONE = 0x02,
223 PS_PRIO_mask = 0x03 << 24,
224 PS_PRIO_shift = 24,
225 VS_PRIO_mask = 0x03 << 26,
226 VS_PRIO_shift = 26,
227 GS_PRIO_mask = 0x03 << 28,
228 GS_PRIO_shift = 28,
229 ES_PRIO_mask = 0x03 << 30,
230 ES_PRIO_shift = 30,
231 SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04,
232 NUM_PS_GPRS_mask = 0xff << 0,
233 NUM_PS_GPRS_shift = 0,
234 NUM_VS_GPRS_mask = 0xff << 16,
235 NUM_VS_GPRS_shift = 16,
236 NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28,
237 NUM_CLAUSE_TEMP_GPRS_shift = 28,
238 SQ_GPR_RESOURCE_MGMT_2 = 0x00008c08,
239 NUM_GS_GPRS_mask = 0xff << 0,
240 NUM_GS_GPRS_shift = 0,
241 NUM_ES_GPRS_mask = 0xff << 16,
242 NUM_ES_GPRS_shift = 16,
243 SQ_THREAD_RESOURCE_MGMT = 0x00008c0c,
244 NUM_PS_THREADS_mask = 0xff << 0,
245 NUM_PS_THREADS_shift = 0,
246 NUM_VS_THREADS_mask = 0xff << 8,
247 NUM_VS_THREADS_shift = 8,
248 NUM_GS_THREADS_mask = 0xff << 16,
249 NUM_GS_THREADS_shift = 16,
250 NUM_ES_THREADS_mask = 0xff << 24,
251 NUM_ES_THREADS_shift = 24,
252 SQ_STACK_RESOURCE_MGMT_1 = 0x00008c10,
253 NUM_PS_STACK_ENTRIES_mask = 0xfff << 0,
254 NUM_PS_STACK_ENTRIES_shift = 0,
255 NUM_VS_STACK_ENTRIES_mask = 0xfff << 16,
256 NUM_VS_STACK_ENTRIES_shift = 16,
257 SQ_STACK_RESOURCE_MGMT_2 = 0x00008c14,
258 NUM_GS_STACK_ENTRIES_mask = 0xfff << 0,
259 NUM_GS_STACK_ENTRIES_shift = 0,
260 NUM_ES_STACK_ENTRIES_mask = 0xfff << 16,
261 NUM_ES_STACK_ENTRIES_shift = 16,
262 SQ_ESGS_RING_BASE = 0x00008c40,
263 SQ_ESGS_RING_SIZE = 0x00008c44,
264 SQ_GSVS_RING_BASE = 0x00008c48,
265 SQ_GSVS_RING_SIZE = 0x00008c4c,
266 SQ_ESTMP_RING_BASE = 0x00008c50,
267 SQ_ESTMP_RING_SIZE = 0x00008c54,
268 SQ_GSTMP_RING_BASE = 0x00008c58,
269 SQ_GSTMP_RING_SIZE = 0x00008c5c,
270 SQ_VSTMP_RING_BASE = 0x00008c60,
271 SQ_VSTMP_RING_SIZE = 0x00008c64,
272 SQ_PSTMP_RING_BASE = 0x00008c68,
273 SQ_PSTMP_RING_SIZE = 0x00008c6c,
274 SQ_FBUF_RING_BASE = 0x00008c70,
275 SQ_FBUF_RING_SIZE = 0x00008c74,
276 SQ_REDUC_RING_BASE = 0x00008c78,
277 SQ_REDUC_RING_SIZE = 0x00008c7c,
278 SQ_ALU_WORD1_OP3 = 0x00008dfc,
279 SRC2_SEL_mask = 0x1ff << 0,
280 SRC2_SEL_shift = 0,
281 SQ_ALU_SRC_0 = 0xf8,
282 SQ_ALU_SRC_1 = 0xf9,
283 SQ_ALU_SRC_1_INT = 0xfa,
284 SQ_ALU_SRC_M_1_INT = 0xfb,
285 SQ_ALU_SRC_0_5 = 0xfc,
286 SQ_ALU_SRC_LITERAL = 0xfd,
287 SQ_ALU_SRC_PV = 0xfe,
288 SQ_ALU_SRC_PS = 0xff,
289 SRC2_REL_bit = 1 << 9,
290 SRC2_CHAN_mask = 0x03 << 10,
291 SRC2_CHAN_shift = 10,
292 SQ_CHAN_X = 0x00,
293 SQ_CHAN_Y = 0x01,
294 SQ_CHAN_Z = 0x02,
295 SQ_CHAN_W = 0x03,
296 SRC2_NEG_bit = 1 << 12,
297 SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13,
298 SQ_ALU_WORD1_OP3__ALU_INST_shift = 13,
299 SQ_OP3_INST_MUL_LIT = 0x0c,
300 SQ_OP3_INST_MUL_LIT_M2 = 0x0d,
301 SQ_OP3_INST_MUL_LIT_M4 = 0x0e,
302 SQ_OP3_INST_MUL_LIT_D2 = 0x0f,
303 SQ_OP3_INST_MULADD = 0x10,
304 SQ_OP3_INST_MULADD_M2 = 0x11,
305 SQ_OP3_INST_MULADD_M4 = 0x12,
306 SQ_OP3_INST_MULADD_D2 = 0x13,
307 SQ_OP3_INST_MULADD_IEEE = 0x14,
308 SQ_OP3_INST_MULADD_IEEE_M2 = 0x15,
309 SQ_OP3_INST_MULADD_IEEE_M4 = 0x16,
310 SQ_OP3_INST_MULADD_IEEE_D2 = 0x17,
311 SQ_OP3_INST_CNDE = 0x18,
312 SQ_OP3_INST_CNDGT = 0x19,
313 SQ_OP3_INST_CNDGE = 0x1a,
314 SQ_OP3_INST_CNDE_INT = 0x1c,
315 SQ_OP3_INST_CNDGT_INT = 0x1d,
316 SQ_OP3_INST_CNDGE_INT = 0x1e,
317 SQ_TEX_WORD2 = 0x00008dfc,
318 OFFSET_X_mask = 0x1f << 0,
319 OFFSET_X_shift = 0,
320 OFFSET_Y_mask = 0x1f << 5,
321 OFFSET_Y_shift = 5,
322 OFFSET_Z_mask = 0x1f << 10,
323 OFFSET_Z_shift = 10,
324 SAMPLER_ID_mask = 0x1f << 15,
325 SAMPLER_ID_shift = 15,
326 SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20,
327 SQ_TEX_WORD2__SRC_SEL_X_shift = 20,
328 SQ_SEL_X = 0x00,
329 SQ_SEL_Y = 0x01,
330 SQ_SEL_Z = 0x02,
331 SQ_SEL_W = 0x03,
332 SQ_SEL_0 = 0x04,
333 SQ_SEL_1 = 0x05,
334 SRC_SEL_Y_mask = 0x07 << 23,
335 SRC_SEL_Y_shift = 23,
336 /* SQ_SEL_X = 0x00, */
337 /* SQ_SEL_Y = 0x01, */
338 /* SQ_SEL_Z = 0x02, */
339 /* SQ_SEL_W = 0x03, */
340 /* SQ_SEL_0 = 0x04, */
341 /* SQ_SEL_1 = 0x05, */
342 SRC_SEL_Z_mask = 0x07 << 26,
343 SRC_SEL_Z_shift = 26,
344 /* SQ_SEL_X = 0x00, */
345 /* SQ_SEL_Y = 0x01, */
346 /* SQ_SEL_Z = 0x02, */
347 /* SQ_SEL_W = 0x03, */
348 /* SQ_SEL_0 = 0x04, */
349 /* SQ_SEL_1 = 0x05, */
350 SRC_SEL_W_mask = 0x07 << 29,
351 SRC_SEL_W_shift = 29,
352 /* SQ_SEL_X = 0x00, */
353 /* SQ_SEL_Y = 0x01, */
354 /* SQ_SEL_Z = 0x02, */
355 /* SQ_SEL_W = 0x03, */
356 /* SQ_SEL_0 = 0x04, */
357 /* SQ_SEL_1 = 0x05, */
358 SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc,
359 BURST_COUNT_mask = 0x0f << 17,
360 BURST_COUNT_shift = 17,
361 END_OF_PROGRAM_bit = 1 << 21,
362 VALID_PIXEL_MODE_bit = 1 << 22,
363 SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23,
364 SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 23,
365 SQ_CF_INST_MEM_STREAM0 = 0x20,
366 SQ_CF_INST_MEM_STREAM1 = 0x21,
367 SQ_CF_INST_MEM_STREAM2 = 0x22,
368 SQ_CF_INST_MEM_STREAM3 = 0x23,
369 SQ_CF_INST_MEM_SCRATCH = 0x24,
370 SQ_CF_INST_MEM_REDUCTION = 0x25,
371 SQ_CF_INST_MEM_RING = 0x26,
372 SQ_CF_INST_EXPORT = 0x27,
373 SQ_CF_INST_EXPORT_DONE = 0x28,
374 WHOLE_QUAD_MODE_bit = 1 << 30,
375 BARRIER_bit = 1 << 31,
376 SQ_CF_ALU_WORD1 = 0x00008dfc,
377 KCACHE_MODE1_mask = 0x03 << 0,
378 KCACHE_MODE1_shift = 0,
379 SQ_CF_KCACHE_NOP = 0x00,
380 SQ_CF_KCACHE_LOCK_1 = 0x01,
381 SQ_CF_KCACHE_LOCK_2 = 0x02,
382 SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03,
383 KCACHE_ADDR0_mask = 0xff << 2,
384 KCACHE_ADDR0_shift = 2,
385 KCACHE_ADDR1_mask = 0xff << 10,
386 KCACHE_ADDR1_shift = 10,
387 SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18,
388 SQ_CF_ALU_WORD1__COUNT_shift = 18,
389 SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
390 SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26,
391 SQ_CF_ALU_WORD1__CF_INST_shift = 26,
392 SQ_CF_INST_ALU = 0x08,
393 SQ_CF_INST_ALU_PUSH_BEFORE = 0x09,
394 SQ_CF_INST_ALU_POP_AFTER = 0x0a,
395 SQ_CF_INST_ALU_POP2_AFTER = 0x0b,
396 SQ_CF_INST_ALU_CONTINUE = 0x0d,
397 SQ_CF_INST_ALU_BREAK = 0x0e,
398 SQ_CF_INST_ALU_ELSE_AFTER = 0x0f,
399 /* WHOLE_QUAD_MODE_bit = 1 << 30, */
400 /* BARRIER_bit = 1 << 31, */
401 SQ_TEX_WORD1 = 0x00008dfc,
402 SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0,
403 SQ_TEX_WORD1__DST_GPR_shift = 0,
404 SQ_TEX_WORD1__DST_REL_bit = 1 << 7,
405 SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9,
406 SQ_TEX_WORD1__DST_SEL_X_shift = 9,
407 /* SQ_SEL_X = 0x00, */
408 /* SQ_SEL_Y = 0x01, */
409 /* SQ_SEL_Z = 0x02, */
410 /* SQ_SEL_W = 0x03, */
411 /* SQ_SEL_0 = 0x04, */
412 /* SQ_SEL_1 = 0x05, */
413 SQ_SEL_MASK = 0x07,
414 SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12,
415 SQ_TEX_WORD1__DST_SEL_Y_shift = 12,
416 /* SQ_SEL_X = 0x00, */
417 /* SQ_SEL_Y = 0x01, */
418 /* SQ_SEL_Z = 0x02, */
419 /* SQ_SEL_W = 0x03, */
420 /* SQ_SEL_0 = 0x04, */
421 /* SQ_SEL_1 = 0x05, */
422 /* SQ_SEL_MASK = 0x07, */
423 SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15,
424 SQ_TEX_WORD1__DST_SEL_Z_shift = 15,
425 /* SQ_SEL_X = 0x00, */
426 /* SQ_SEL_Y = 0x01, */
427 /* SQ_SEL_Z = 0x02, */
428 /* SQ_SEL_W = 0x03, */
429 /* SQ_SEL_0 = 0x04, */
430 /* SQ_SEL_1 = 0x05, */
431 /* SQ_SEL_MASK = 0x07, */
432 SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18,
433 SQ_TEX_WORD1__DST_SEL_W_shift = 18,
434 /* SQ_SEL_X = 0x00, */
435 /* SQ_SEL_Y = 0x01, */
436 /* SQ_SEL_Z = 0x02, */
437 /* SQ_SEL_W = 0x03, */
438 /* SQ_SEL_0 = 0x04, */
439 /* SQ_SEL_1 = 0x05, */
440 /* SQ_SEL_MASK = 0x07, */
441 SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21,
442 SQ_TEX_WORD1__LOD_BIAS_shift = 21,
443 COORD_TYPE_X_bit = 1 << 28,
444 COORD_TYPE_Y_bit = 1 << 29,
445 COORD_TYPE_Z_bit = 1 << 30,
446 COORD_TYPE_W_bit = 1 << 31,
447 SQ_VTX_WORD0 = 0x00008dfc,
448 VTX_INST_mask = 0x1f << 0,
449 VTX_INST_shift = 0,
450 SQ_VTX_INST_FETCH = 0x00,
451 SQ_VTX_INST_SEMANTIC = 0x01,
452 FETCH_TYPE_mask = 0x03 << 5,
453 FETCH_TYPE_shift = 5,
454 SQ_VTX_FETCH_VERTEX_DATA = 0x00,
455 SQ_VTX_FETCH_INSTANCE_DATA = 0x01,
456 SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02,
457 FETCH_WHOLE_QUAD_bit = 1 << 7,
458 BUFFER_ID_mask = 0xff << 8,
459 BUFFER_ID_shift = 8,
460 SRC_GPR_mask = 0x7f << 16,
461 SRC_GPR_shift = 16,
462 SRC_REL_bit = 1 << 23,
463 SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24,
464 SQ_VTX_WORD0__SRC_SEL_X_shift = 24,
465 /* SQ_SEL_X = 0x00, */
466 /* SQ_SEL_Y = 0x01, */
467 /* SQ_SEL_Z = 0x02, */
468 /* SQ_SEL_W = 0x03, */
469 MEGA_FETCH_COUNT_mask = 0x3f << 26,
470 MEGA_FETCH_COUNT_shift = 26,
471 SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc,
472 SEL_X_mask = 0x07 << 0,
473 SEL_X_shift = 0,
474 /* SQ_SEL_X = 0x00, */
475 /* SQ_SEL_Y = 0x01, */
476 /* SQ_SEL_Z = 0x02, */
477 /* SQ_SEL_W = 0x03, */
478 /* SQ_SEL_0 = 0x04, */
479 /* SQ_SEL_1 = 0x05, */
480 /* SQ_SEL_MASK = 0x07, */
481 SEL_Y_mask = 0x07 << 3,
482 SEL_Y_shift = 3,
483 /* SQ_SEL_X = 0x00, */
484 /* SQ_SEL_Y = 0x01, */
485 /* SQ_SEL_Z = 0x02, */
486 /* SQ_SEL_W = 0x03, */
487 /* SQ_SEL_0 = 0x04, */
488 /* SQ_SEL_1 = 0x05, */
489 /* SQ_SEL_MASK = 0x07, */
490 SEL_Z_mask = 0x07 << 6,
491 SEL_Z_shift = 6,
492 /* SQ_SEL_X = 0x00, */
493 /* SQ_SEL_Y = 0x01, */
494 /* SQ_SEL_Z = 0x02, */
495 /* SQ_SEL_W = 0x03, */
496 /* SQ_SEL_0 = 0x04, */
497 /* SQ_SEL_1 = 0x05, */
498 /* SQ_SEL_MASK = 0x07, */
499 SEL_W_mask = 0x07 << 9,
500 SEL_W_shift = 9,
501 /* SQ_SEL_X = 0x00, */
502 /* SQ_SEL_Y = 0x01, */
503 /* SQ_SEL_Z = 0x02, */
504 /* SQ_SEL_W = 0x03, */
505 /* SQ_SEL_0 = 0x04, */
506 /* SQ_SEL_1 = 0x05, */
507 /* SQ_SEL_MASK = 0x07, */
508 SQ_ALU_WORD1 = 0x00008dfc,
509 ENCODING_mask = 0x07 << 15,
510 ENCODING_shift = 15,
511 BANK_SWIZZLE_mask = 0x07 << 18,
512 BANK_SWIZZLE_shift = 18,
513 SQ_ALU_VEC_012 = 0x00,
514 SQ_ALU_VEC_021 = 0x01,
515 SQ_ALU_VEC_120 = 0x02,
516 SQ_ALU_VEC_102 = 0x03,
517 SQ_ALU_VEC_201 = 0x04,
518 SQ_ALU_VEC_210 = 0x05,
519 SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21,
520 SQ_ALU_WORD1__DST_GPR_shift = 21,
521 SQ_ALU_WORD1__DST_REL_bit = 1 << 28,
522 DST_CHAN_mask = 0x03 << 29,
523 DST_CHAN_shift = 29,
524 CHAN_X = 0x00,
525 CHAN_Y = 0x01,
526 CHAN_Z = 0x02,
527 CHAN_W = 0x03,
528 SQ_ALU_WORD1__CLAMP_bit = 1 << 31,
529 SQ_CF_ALU_WORD0 = 0x00008dfc,
530 SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0,
531 SQ_CF_ALU_WORD0__ADDR_shift = 0,
532 KCACHE_BANK0_mask = 0x0f << 22,
533 KCACHE_BANK0_shift = 22,
534 KCACHE_BANK1_mask = 0x0f << 26,
535 KCACHE_BANK1_shift = 26,
536 KCACHE_MODE0_mask = 0x03 << 30,
537 KCACHE_MODE0_shift = 30,
538 /* SQ_CF_KCACHE_NOP = 0x00, */
539 /* SQ_CF_KCACHE_LOCK_1 = 0x01, */
540 /* SQ_CF_KCACHE_LOCK_2 = 0x02, */
541 /* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */
542 SQ_VTX_WORD2 = 0x00008dfc,
543 SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0,
544 SQ_VTX_WORD2__OFFSET_shift = 0,
545 SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16,
546 SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16,
547 SQ_ENDIAN_NONE = 0x00,
548 SQ_ENDIAN_8IN16 = 0x01,
549 SQ_ENDIAN_8IN32 = 0x02,
550 CONST_BUF_NO_STRIDE_bit = 1 << 18,
551 MEGA_FETCH_bit = 1 << 19,
552 SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
553 SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
554 SRC0_ABS_bit = 1 << 0,
555 SRC1_ABS_bit = 1 << 1,
556 UPDATE_EXECUTE_MASK_bit = 1 << 2,
557 UPDATE_PRED_bit = 1 << 3,
558 WRITE_MASK_bit = 1 << 4,
559 SQ_ALU_WORD1_OP2_V2__OMOD_mask = 0x03 << 5,
560 SQ_ALU_WORD1_OP2_V2__OMOD_shift = 5,
561 SQ_ALU_OMOD_OFF = 0x00,
562 SQ_ALU_OMOD_M2 = 0x01,
563 SQ_ALU_OMOD_M4 = 0x02,
564 SQ_ALU_OMOD_D2 = 0x03,
565 SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
566 SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
567 SQ_OP2_INST_ADD = 0x00,
568 SQ_OP2_INST_MUL = 0x01,
569 SQ_OP2_INST_MUL_IEEE = 0x02,
570 SQ_OP2_INST_MAX = 0x03,
571 SQ_OP2_INST_MIN = 0x04,
572 SQ_OP2_INST_MAX_DX10 = 0x05,
573 SQ_OP2_INST_MIN_DX10 = 0x06,
574 SQ_OP2_INST_SETE = 0x08,
575 SQ_OP2_INST_SETGT = 0x09,
576 SQ_OP2_INST_SETGE = 0x0a,
577 SQ_OP2_INST_SETNE = 0x0b,
578 SQ_OP2_INST_SETE_DX10 = 0x0c,
579 SQ_OP2_INST_SETGT_DX10 = 0x0d,
580 SQ_OP2_INST_SETGE_DX10 = 0x0e,
581 SQ_OP2_INST_SETNE_DX10 = 0x0f,
582 SQ_OP2_INST_FRACT = 0x10,
583 SQ_OP2_INST_TRUNC = 0x11,
584 SQ_OP2_INST_CEIL = 0x12,
585 SQ_OP2_INST_RNDNE = 0x13,
586 SQ_OP2_INST_FLOOR = 0x14,
587 SQ_OP2_INST_MOVA = 0x15,
588 SQ_OP2_INST_MOVA_FLOOR = 0x16,
589 SQ_OP2_INST_MOVA_INT = 0x18,
590 SQ_OP2_INST_MOV = 0x19,
591 SQ_OP2_INST_NOP = 0x1a,
592 SQ_OP2_INST_PRED_SETGT_UINT = 0x1e,
593 SQ_OP2_INST_PRED_SETGE_UINT = 0x1f,
594 SQ_OP2_INST_PRED_SETE = 0x20,
595 SQ_OP2_INST_PRED_SETGT = 0x21,
596 SQ_OP2_INST_PRED_SETGE = 0x22,
597 SQ_OP2_INST_PRED_SETNE = 0x23,
598 SQ_OP2_INST_PRED_SET_INV = 0x24,
599 SQ_OP2_INST_PRED_SET_POP = 0x25,
600 SQ_OP2_INST_PRED_SET_CLR = 0x26,
601 SQ_OP2_INST_PRED_SET_RESTORE = 0x27,
602 SQ_OP2_INST_PRED_SETE_PUSH = 0x28,
603 SQ_OP2_INST_PRED_SETGT_PUSH = 0x29,
604 SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a,
605 SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b,
606 SQ_OP2_INST_KILLE = 0x2c,
607 SQ_OP2_INST_KILLGT = 0x2d,
608 SQ_OP2_INST_KILLGE = 0x2e,
609 SQ_OP2_INST_KILLNE = 0x2f,
610 SQ_OP2_INST_AND_INT = 0x30,
611 SQ_OP2_INST_OR_INT = 0x31,
612 SQ_OP2_INST_XOR_INT = 0x32,
613 SQ_OP2_INST_NOT_INT = 0x33,
614 SQ_OP2_INST_ADD_INT = 0x34,
615 SQ_OP2_INST_SUB_INT = 0x35,
616 SQ_OP2_INST_MAX_INT = 0x36,
617 SQ_OP2_INST_MIN_INT = 0x37,
618 SQ_OP2_INST_MAX_UINT = 0x38,
619 SQ_OP2_INST_MIN_UINT = 0x39,
620 SQ_OP2_INST_SETE_INT = 0x3a,
621 SQ_OP2_INST_SETGT_INT = 0x3b,
622 SQ_OP2_INST_SETGE_INT = 0x3c,
623 SQ_OP2_INST_SETNE_INT = 0x3d,
624 SQ_OP2_INST_SETGT_UINT = 0x3e,
625 SQ_OP2_INST_SETGE_UINT = 0x3f,
626 SQ_OP2_INST_KILLGT_UINT = 0x40,
627 SQ_OP2_INST_KILLGE_UINT = 0x41,
628 SQ_OP2_INST_PRED_SETE_INT = 0x42,
629 SQ_OP2_INST_PRED_SETGT_INT = 0x43,
630 SQ_OP2_INST_PRED_SETGE_INT = 0x44,
631 SQ_OP2_INST_PRED_SETNE_INT = 0x45,
632 SQ_OP2_INST_KILLE_INT = 0x46,
633 SQ_OP2_INST_KILLGT_INT = 0x47,
634 SQ_OP2_INST_KILLGE_INT = 0x48,
635 SQ_OP2_INST_KILLNE_INT = 0x49,
636 SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a,
637 SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b,
638 SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c,
639 SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d,
640 SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e,
641 SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f,
642 SQ_OP2_INST_DOT4 = 0x50,
643 SQ_OP2_INST_DOT4_IEEE = 0x51,
644 SQ_OP2_INST_CUBE = 0x52,
645 SQ_OP2_INST_MAX4 = 0x53,
646 SQ_OP2_INST_MOVA_GPR_INT = 0x60,
647 SQ_OP2_INST_EXP_IEEE = 0x61,
648 SQ_OP2_INST_LOG_CLAMPED = 0x62,
649 SQ_OP2_INST_LOG_IEEE = 0x63,
650 SQ_OP2_INST_RECIP_CLAMPED = 0x64,
651 SQ_OP2_INST_RECIP_FF = 0x65,
652 SQ_OP2_INST_RECIP_IEEE = 0x66,
653 SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67,
654 SQ_OP2_INST_RECIPSQRT_FF = 0x68,
655 SQ_OP2_INST_RECIPSQRT_IEEE = 0x69,
656 SQ_OP2_INST_SQRT_IEEE = 0x6a,
657 SQ_OP2_INST_FLT_TO_INT = 0x6b,
658 SQ_OP2_INST_INT_TO_FLT = 0x6c,
659 SQ_OP2_INST_UINT_TO_FLT = 0x6d,
660 SQ_OP2_INST_SIN = 0x6e,
661 SQ_OP2_INST_COS = 0x6f,
662 SQ_OP2_INST_ASHR_INT = 0x70,
663 SQ_OP2_INST_LSHR_INT = 0x71,
664 SQ_OP2_INST_LSHL_INT = 0x72,
665 SQ_OP2_INST_MULLO_INT = 0x73,
666 SQ_OP2_INST_MULHI_INT = 0x74,
667 SQ_OP2_INST_MULLO_UINT = 0x75,
668 SQ_OP2_INST_MULHI_UINT = 0x76,
669 SQ_OP2_INST_RECIP_INT = 0x77,
670 SQ_OP2_INST_RECIP_UINT = 0x78,
671 SQ_OP2_INST_FLT_TO_UINT = 0x79,
672 SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc,
673 ARRAY_SIZE_mask = 0xfff << 0,
674 ARRAY_SIZE_shift = 0,
675 COMP_MASK_mask = 0x0f << 12,
676 COMP_MASK_shift = 12,
677 SQ_CF_WORD0 = 0x00008dfc,
678 SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc,
679 ARRAY_BASE_mask = 0x1fff << 0,
680 ARRAY_BASE_shift = 0,
681 SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13,
682 SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13,
683 SQ_EXPORT_PIXEL = 0x00,
684 SQ_EXPORT_POS = 0x01,
685 SQ_EXPORT_PARAM = 0x02,
686 X_UNUSED_FOR_SX_EXPORTS = 0x03,
687 RW_GPR_mask = 0x7f << 15,
688 RW_GPR_shift = 15,
689 RW_REL_bit = 1 << 22,
690 INDEX_GPR_mask = 0x7f << 23,
691 INDEX_GPR_shift = 23,
692 ELEM_SIZE_mask = 0x03 << 30,
693 ELEM_SIZE_shift = 30,
694 SQ_VTX_WORD1 = 0x00008dfc,
695 SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9,
696 SQ_VTX_WORD1__DST_SEL_X_shift = 9,
697 /* SQ_SEL_X = 0x00, */
698 /* SQ_SEL_Y = 0x01, */
699 /* SQ_SEL_Z = 0x02, */
700 /* SQ_SEL_W = 0x03, */
701 /* SQ_SEL_0 = 0x04, */
702 /* SQ_SEL_1 = 0x05, */
703 /* SQ_SEL_MASK = 0x07, */
704 SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12,
705 SQ_VTX_WORD1__DST_SEL_Y_shift = 12,
706 /* SQ_SEL_X = 0x00, */
707 /* SQ_SEL_Y = 0x01, */
708 /* SQ_SEL_Z = 0x02, */
709 /* SQ_SEL_W = 0x03, */
710 /* SQ_SEL_0 = 0x04, */
711 /* SQ_SEL_1 = 0x05, */
712 /* SQ_SEL_MASK = 0x07, */
713 SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15,
714 SQ_VTX_WORD1__DST_SEL_Z_shift = 15,
715 /* SQ_SEL_X = 0x00, */
716 /* SQ_SEL_Y = 0x01, */
717 /* SQ_SEL_Z = 0x02, */
718 /* SQ_SEL_W = 0x03, */
719 /* SQ_SEL_0 = 0x04, */
720 /* SQ_SEL_1 = 0x05, */
721 /* SQ_SEL_MASK = 0x07, */
722 SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18,
723 SQ_VTX_WORD1__DST_SEL_W_shift = 18,
724 /* SQ_SEL_X = 0x00, */
725 /* SQ_SEL_Y = 0x01, */
726 /* SQ_SEL_Z = 0x02, */
727 /* SQ_SEL_W = 0x03, */
728 /* SQ_SEL_0 = 0x04, */
729 /* SQ_SEL_1 = 0x05, */
730 /* SQ_SEL_MASK = 0x07, */
731 USE_CONST_FIELDS_bit = 1 << 21,
732 SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22,
733 SQ_VTX_WORD1__DATA_FORMAT_shift = 22,
734 SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28,
735 SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28,
736 SQ_NUM_FORMAT_NORM = 0x00,
737 SQ_NUM_FORMAT_INT = 0x01,
738 SQ_NUM_FORMAT_SCALED = 0x02,
739 SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30,
740 SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31,
741 SQ_ALU_WORD1_OP2 = 0x00008dfc,
742 /* SRC0_ABS_bit = 1 << 0, */
743 /* SRC1_ABS_bit = 1 << 1, */
744 /* UPDATE_EXECUTE_MASK_bit = 1 << 2, */
745 /* UPDATE_PRED_bit = 1 << 3, */
746 /* WRITE_MASK_bit = 1 << 4, */
747 FOG_MERGE_bit = 1 << 5,
748 SQ_ALU_WORD1_OP2__OMOD_mask = 0x03 << 6,
749 SQ_ALU_WORD1_OP2__OMOD_shift = 6,
750 /* SQ_ALU_OMOD_OFF = 0x00, */
751 /* SQ_ALU_OMOD_M2 = 0x01, */
752 /* SQ_ALU_OMOD_M4 = 0x02, */
753 /* SQ_ALU_OMOD_D2 = 0x03, */
754 SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
755 SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
756 /* SQ_OP2_INST_ADD = 0x00, */
757 /* SQ_OP2_INST_MUL = 0x01, */
758 /* SQ_OP2_INST_MUL_IEEE = 0x02, */
759 /* SQ_OP2_INST_MAX = 0x03, */
760 /* SQ_OP2_INST_MIN = 0x04, */
761 /* SQ_OP2_INST_MAX_DX10 = 0x05, */
762 /* SQ_OP2_INST_MIN_DX10 = 0x06, */
763 /* SQ_OP2_INST_SETE = 0x08, */
764 /* SQ_OP2_INST_SETGT = 0x09, */
765 /* SQ_OP2_INST_SETGE = 0x0a, */
766 /* SQ_OP2_INST_SETNE = 0x0b, */
767 /* SQ_OP2_INST_SETE_DX10 = 0x0c, */
768 /* SQ_OP2_INST_SETGT_DX10 = 0x0d, */
769 /* SQ_OP2_INST_SETGE_DX10 = 0x0e, */
770 /* SQ_OP2_INST_SETNE_DX10 = 0x0f, */
771 /* SQ_OP2_INST_FRACT = 0x10, */
772 /* SQ_OP2_INST_TRUNC = 0x11, */
773 /* SQ_OP2_INST_CEIL = 0x12, */
774 /* SQ_OP2_INST_RNDNE = 0x13, */
775 /* SQ_OP2_INST_FLOOR = 0x14, */
776 /* SQ_OP2_INST_MOVA = 0x15, */
777 /* SQ_OP2_INST_MOVA_FLOOR = 0x16, */
778 /* SQ_OP2_INST_MOVA_INT = 0x18, */
779 /* SQ_OP2_INST_MOV = 0x19, */
780 /* SQ_OP2_INST_NOP = 0x1a, */
781 /* SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, */
782 /* SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, */
783 /* SQ_OP2_INST_PRED_SETE = 0x20, */
784 /* SQ_OP2_INST_PRED_SETGT = 0x21, */
785 /* SQ_OP2_INST_PRED_SETGE = 0x22, */
786 /* SQ_OP2_INST_PRED_SETNE = 0x23, */
787 /* SQ_OP2_INST_PRED_SET_INV = 0x24, */
788 /* SQ_OP2_INST_PRED_SET_POP = 0x25, */
789 /* SQ_OP2_INST_PRED_SET_CLR = 0x26, */
790 /* SQ_OP2_INST_PRED_SET_RESTORE = 0x27, */
791 /* SQ_OP2_INST_PRED_SETE_PUSH = 0x28, */
792 /* SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, */
793 /* SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, */
794 /* SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, */
795 /* SQ_OP2_INST_KILLE = 0x2c, */
796 /* SQ_OP2_INST_KILLGT = 0x2d, */
797 /* SQ_OP2_INST_KILLGE = 0x2e, */
798 /* SQ_OP2_INST_KILLNE = 0x2f, */
799 /* SQ_OP2_INST_AND_INT = 0x30, */
800 /* SQ_OP2_INST_OR_INT = 0x31, */
801 /* SQ_OP2_INST_XOR_INT = 0x32, */
802 /* SQ_OP2_INST_NOT_INT = 0x33, */
803 /* SQ_OP2_INST_ADD_INT = 0x34, */
804 /* SQ_OP2_INST_SUB_INT = 0x35, */
805 /* SQ_OP2_INST_MAX_INT = 0x36, */
806 /* SQ_OP2_INST_MIN_INT = 0x37, */
807 /* SQ_OP2_INST_MAX_UINT = 0x38, */
808 /* SQ_OP2_INST_MIN_UINT = 0x39, */
809 /* SQ_OP2_INST_SETE_INT = 0x3a, */
810 /* SQ_OP2_INST_SETGT_INT = 0x3b, */
811 /* SQ_OP2_INST_SETGE_INT = 0x3c, */
812 /* SQ_OP2_INST_SETNE_INT = 0x3d, */
813 /* SQ_OP2_INST_SETGT_UINT = 0x3e, */
814 /* SQ_OP2_INST_SETGE_UINT = 0x3f, */
815 /* SQ_OP2_INST_KILLGT_UINT = 0x40, */
816 /* SQ_OP2_INST_KILLGE_UINT = 0x41, */
817 /* SQ_OP2_INST_PRED_SETE_INT = 0x42, */
818 /* SQ_OP2_INST_PRED_SETGT_INT = 0x43, */
819 /* SQ_OP2_INST_PRED_SETGE_INT = 0x44, */
820 /* SQ_OP2_INST_PRED_SETNE_INT = 0x45, */
821 /* SQ_OP2_INST_KILLE_INT = 0x46, */
822 /* SQ_OP2_INST_KILLGT_INT = 0x47, */
823 /* SQ_OP2_INST_KILLGE_INT = 0x48, */
824 /* SQ_OP2_INST_KILLNE_INT = 0x49, */
825 /* SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, */
826 /* SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, */
827 /* SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, */
828 /* SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, */
829 /* SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, */
830 /* SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, */
831 /* SQ_OP2_INST_DOT4 = 0x50, */
832 /* SQ_OP2_INST_DOT4_IEEE = 0x51, */
833 /* SQ_OP2_INST_CUBE = 0x52, */
834 /* SQ_OP2_INST_MAX4 = 0x53, */
835 /* SQ_OP2_INST_MOVA_GPR_INT = 0x60, */
836 /* SQ_OP2_INST_EXP_IEEE = 0x61, */
837 /* SQ_OP2_INST_LOG_CLAMPED = 0x62, */
838 /* SQ_OP2_INST_LOG_IEEE = 0x63, */
839 /* SQ_OP2_INST_RECIP_CLAMPED = 0x64, */
840 /* SQ_OP2_INST_RECIP_FF = 0x65, */
841 /* SQ_OP2_INST_RECIP_IEEE = 0x66, */
842 /* SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x67, */
843 /* SQ_OP2_INST_RECIPSQRT_FF = 0x68, */
844 /* SQ_OP2_INST_RECIPSQRT_IEEE = 0x69, */
845 /* SQ_OP2_INST_SQRT_IEEE = 0x6a, */
846 /* SQ_OP2_INST_FLT_TO_INT = 0x6b, */
847 /* SQ_OP2_INST_INT_TO_FLT = 0x6c, */
848 /* SQ_OP2_INST_UINT_TO_FLT = 0x6d, */
849 /* SQ_OP2_INST_SIN = 0x6e, */
850 /* SQ_OP2_INST_COS = 0x6f, */
851 /* SQ_OP2_INST_ASHR_INT = 0x70, */
852 /* SQ_OP2_INST_LSHR_INT = 0x71, */
853 /* SQ_OP2_INST_LSHL_INT = 0x72, */
854 /* SQ_OP2_INST_MULLO_INT = 0x73, */
855 /* SQ_OP2_INST_MULHI_INT = 0x74, */
856 /* SQ_OP2_INST_MULLO_UINT = 0x75, */
857 /* SQ_OP2_INST_MULHI_UINT = 0x76, */
858 /* SQ_OP2_INST_RECIP_INT = 0x77, */
859 /* SQ_OP2_INST_RECIP_UINT = 0x78, */
860 /* SQ_OP2_INST_FLT_TO_UINT = 0x79, */
861 SQ_CF_WORD1 = 0x00008dfc,
862 POP_COUNT_mask = 0x07 << 0,
863 POP_COUNT_shift = 0,
864 CF_CONST_mask = 0x1f << 3,
865 CF_CONST_shift = 3,
866 COND_mask = 0x03 << 8,
867 COND_shift = 8,
868 SQ_CF_COND_ACTIVE = 0x00,
869 SQ_CF_COND_FALSE = 0x01,
870 SQ_CF_COND_BOOL = 0x02,
871 SQ_CF_COND_NOT_BOOL = 0x03,
872 SQ_CF_WORD1__COUNT_mask = 0x07 << 10,
873 SQ_CF_WORD1__COUNT_shift = 10,
874 CALL_COUNT_mask = 0x3f << 13,
875 CALL_COUNT_shift = 13,
876 COUNT_3_bit = 1 << 19,
877 /* END_OF_PROGRAM_bit = 1 << 21, */
878 /* VALID_PIXEL_MODE_bit = 1 << 22, */
879 SQ_CF_WORD1__CF_INST_mask = 0x7f << 23,
880 SQ_CF_WORD1__CF_INST_shift = 23,
881 SQ_CF_INST_NOP = 0x00,
882 SQ_CF_INST_TEX = 0x01,
883 SQ_CF_INST_VTX = 0x02,
884 SQ_CF_INST_VTX_TC = 0x03,
885 SQ_CF_INST_LOOP_START = 0x04,
886 SQ_CF_INST_LOOP_END = 0x05,
887 SQ_CF_INST_LOOP_START_DX10 = 0x06,
888 SQ_CF_INST_LOOP_START_NO_AL = 0x07,
889 SQ_CF_INST_LOOP_CONTINUE = 0x08,
890 SQ_CF_INST_LOOP_BREAK = 0x09,
891 SQ_CF_INST_JUMP = 0x0a,
892 SQ_CF_INST_PUSH = 0x0b,
893 SQ_CF_INST_PUSH_ELSE = 0x0c,
894 SQ_CF_INST_ELSE = 0x0d,
895 SQ_CF_INST_POP = 0x0e,
896 SQ_CF_INST_POP_JUMP = 0x0f,
897 SQ_CF_INST_POP_PUSH = 0x10,
898 SQ_CF_INST_POP_PUSH_ELSE = 0x11,
899 SQ_CF_INST_CALL = 0x12,
900 SQ_CF_INST_CALL_FS = 0x13,
901 SQ_CF_INST_RETURN = 0x14,
902 SQ_CF_INST_EMIT_VERTEX = 0x15,
903 SQ_CF_INST_EMIT_CUT_VERTEX = 0x16,
904 SQ_CF_INST_CUT_VERTEX = 0x17,
905 SQ_CF_INST_KILL = 0x18,
906 /* WHOLE_QUAD_MODE_bit = 1 << 30, */
907 /* BARRIER_bit = 1 << 31, */
908 SQ_VTX_WORD1_SEM = 0x00008dfc,
909 SEMANTIC_ID_mask = 0xff << 0,
910 SEMANTIC_ID_shift = 0,
911 SQ_TEX_WORD0 = 0x00008dfc,
912 TEX_INST_mask = 0x1f << 0,
913 TEX_INST_shift = 0,
914 SQ_TEX_INST_VTX_FETCH = 0x00,
915 SQ_TEX_INST_VTX_SEMANTIC = 0x01,
916 SQ_TEX_INST_LD = 0x03,
917 SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04,
918 SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05,
919 SQ_TEX_INST_GET_LOD = 0x06,
920 SQ_TEX_INST_GET_GRADIENTS_H = 0x07,
921 SQ_TEX_INST_GET_GRADIENTS_V = 0x08,
922 SQ_TEX_INST_GET_LERP = 0x09,
923 SQ_TEX_INST_RESERVED_10 = 0x0a,
924 SQ_TEX_INST_SET_GRADIENTS_H = 0x0b,
925 SQ_TEX_INST_SET_GRADIENTS_V = 0x0c,
926 SQ_TEX_INST_PASS = 0x0d,
927 X_Z_SET_INDEX_FOR_ARRAY_OF_CUBEMAPS = 0x0e,
928 SQ_TEX_INST_SAMPLE = 0x10,
929 SQ_TEX_INST_SAMPLE_L = 0x11,
930 SQ_TEX_INST_SAMPLE_LB = 0x12,
931 SQ_TEX_INST_SAMPLE_LZ = 0x13,
932 SQ_TEX_INST_SAMPLE_G = 0x14,
933 SQ_TEX_INST_SAMPLE_G_L = 0x15,
934 SQ_TEX_INST_SAMPLE_G_LB = 0x16,
935 SQ_TEX_INST_SAMPLE_G_LZ = 0x17,
936 SQ_TEX_INST_SAMPLE_C = 0x18,
937 SQ_TEX_INST_SAMPLE_C_L = 0x19,
938 SQ_TEX_INST_SAMPLE_C_LB = 0x1a,
939 SQ_TEX_INST_SAMPLE_C_LZ = 0x1b,
940 SQ_TEX_INST_SAMPLE_C_G = 0x1c,
941 SQ_TEX_INST_SAMPLE_C_G_L = 0x1d,
942 SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e,
943 SQ_TEX_INST_SAMPLE_C_G_LZ = 0x1f,
944 BC_FRAC_MODE_bit = 1 << 5,
945 /* FETCH_WHOLE_QUAD_bit = 1 << 7, */
946 RESOURCE_ID_mask = 0xff << 8,
947 RESOURCE_ID_shift = 8,
948 /* SRC_GPR_mask = 0x7f << 16, */
949 /* SRC_GPR_shift = 16, */
950 /* SRC_REL_bit = 1 << 23, */
951 SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
952 SQ_VTX_WORD1_GPR = 0x00008dfc,
953 SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0,
954 SQ_VTX_WORD1_GPR__DST_GPR_shift = 0,
955 SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7,
956 SQ_ALU_WORD0 = 0x00008dfc,
957 SRC0_SEL_mask = 0x1ff << 0,
958 SRC0_SEL_shift = 0,
959 /* SQ_ALU_SRC_0 = 0xf8, */
960 /* SQ_ALU_SRC_1 = 0xf9, */
961 /* SQ_ALU_SRC_1_INT = 0xfa, */
962 /* SQ_ALU_SRC_M_1_INT = 0xfb, */
963 /* SQ_ALU_SRC_0_5 = 0xfc, */
964 /* SQ_ALU_SRC_LITERAL = 0xfd, */
965 /* SQ_ALU_SRC_PV = 0xfe, */
966 /* SQ_ALU_SRC_PS = 0xff, */
967 SRC0_REL_bit = 1 << 9,
968 SRC0_CHAN_mask = 0x03 << 10,
969 SRC0_CHAN_shift = 10,
970 /* SQ_CHAN_X = 0x00, */
971 /* SQ_CHAN_Y = 0x01, */
972 /* SQ_CHAN_Z = 0x02, */
973 /* SQ_CHAN_W = 0x03, */
974 SRC0_NEG_bit = 1 << 12,
975 SRC1_SEL_mask = 0x1ff << 13,
976 SRC1_SEL_shift = 13,
977 /* SQ_ALU_SRC_0 = 0xf8, */
978 /* SQ_ALU_SRC_1 = 0xf9, */
979 /* SQ_ALU_SRC_1_INT = 0xfa, */
980 /* SQ_ALU_SRC_M_1_INT = 0xfb, */
981 /* SQ_ALU_SRC_0_5 = 0xfc, */
982 /* SQ_ALU_SRC_LITERAL = 0xfd, */
983 /* SQ_ALU_SRC_PV = 0xfe, */
984 /* SQ_ALU_SRC_PS = 0xff, */
985 SRC1_REL_bit = 1 << 22,
986 SRC1_CHAN_mask = 0x03 << 23,
987 SRC1_CHAN_shift = 23,
988 /* SQ_CHAN_X = 0x00, */
989 /* SQ_CHAN_Y = 0x01, */
990 /* SQ_CHAN_Z = 0x02, */
991 /* SQ_CHAN_W = 0x03, */
992 SRC1_NEG_bit = 1 << 25,
993 INDEX_MODE_mask = 0x07 << 26,
994 INDEX_MODE_shift = 26,
995 SQ_INDEX_AR_X = 0x00,
996 SQ_INDEX_AR_Y = 0x01,
997 SQ_INDEX_AR_Z = 0x02,
998 SQ_INDEX_AR_W = 0x03,
999 SQ_INDEX_LOOP = 0x04,
1000 PRED_SEL_mask = 0x03 << 29,
1001 PRED_SEL_shift = 29,
1002 SQ_PRED_SEL_OFF = 0x00,
1003 SQ_PRED_SEL_ZERO = 0x02,
1004 SQ_PRED_SEL_ONE = 0x03,
1005 LAST_bit = 1 << 31,
1006 SX_EXPORT_BUFFER_SIZES = 0x0000900c,
1007 COLOR_BUFFER_SIZE_mask = 0xff << 0,
1008 COLOR_BUFFER_SIZE_shift = 0,
1009 POSITION_BUFFER_SIZE_mask = 0xff << 8,
1010 POSITION_BUFFER_SIZE_shift = 8,
1011 SMX_BUFFER_SIZE_mask = 0xff << 16,
1012 SMX_BUFFER_SIZE_shift = 16,
1013 SX_MEMORY_EXPORT_BASE = 0x00009010,
1014 SX_MEMORY_EXPORT_SIZE = 0x00009014,
1015 SPI_CONFIG_CNTL = 0x00009100,
1016 GPR_WRITE_PRIORITY_mask = 0x1f << 0,
1017 GPR_WRITE_PRIORITY_shift = 0,
1018 X_PRIORITY_ORDER = 0x00,
1019 X_PRIORITY_ORDER_VS = 0x01,
1020 DISABLE_INTERP_1_bit = 1 << 5,
1021 DEBUG_THREAD_TYPE_SEL_mask = 0x03 << 6,
1022 DEBUG_THREAD_TYPE_SEL_shift = 6,
1023 DEBUG_GROUP_SEL_mask = 0x1f << 8,
1024 DEBUG_GROUP_SEL_shift = 8,
1025 DEBUG_GRBM_OVERRIDE_bit = 1 << 13,
1026 SPI_CONFIG_CNTL_1 = 0x0000913c,
1027 VTX_DONE_DELAY_mask = 0x0f << 0,
1028 VTX_DONE_DELAY_shift = 0,
1029 X_DELAY_10_CLKS = 0x00,
1030 X_DELAY_11_CLKS = 0x01,
1031 X_DELAY_12_CLKS = 0x02,
1032 X_DELAY_13_CLKS = 0x03,
1033 X_DELAY_14_CLKS = 0x04,
1034 X_DELAY_15_CLKS = 0x05,
1035 X_DELAY_16_CLKS = 0x06,
1036 X_DELAY_17_CLKS = 0x07,
1037 X_DELAY_2_CLKS = 0x08,
1038 X_DELAY_3_CLKS = 0x09,
1039 X_DELAY_4_CLKS = 0x0a,
1040 X_DELAY_5_CLKS = 0x0b,
1041 X_DELAY_6_CLKS = 0x0c,
1042 X_DELAY_7_CLKS = 0x0d,
1043 X_DELAY_8_CLKS = 0x0e,
1044 X_DELAY_9_CLKS = 0x0f,
1045 INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4,
1046 TD_FILTER4 = 0x00009400,
1047 WEIGHT_1_mask = 0x7ff << 0,
1048 WEIGHT_1_shift = 0,
1049 WEIGHT_0_mask = 0x7ff << 11,
1050 WEIGHT_0_shift = 11,
1051 WEIGHT_PAIR_bit = 1 << 22,
1052 PHASE_mask = 0x0f << 23,
1053 PHASE_shift = 23,
1054 DIRECTION_bit = 1 << 27,
1055 TD_FILTER4_1 = 0x00009404,
1056 TD_FILTER4_1_num = 35,
1057 /* WEIGHT_1_mask = 0x7ff << 0, */
1058 /* WEIGHT_1_shift = 0, */
1059 /* WEIGHT_0_mask = 0x7ff << 11, */
1060 /* WEIGHT_0_shift = 11, */
1061 TD_CNTL = 0x00009490,
1062 SYNC_PHASE_SH_mask = 0x03 << 0,
1063 SYNC_PHASE_SH_shift = 0,
1064 SYNC_PHASE_VC_SMX_mask = 0x03 << 4,
1065 SYNC_PHASE_VC_SMX_shift = 4,
1066 TD0_CNTL = 0x00009494,
1067 TD0_CNTL_num = 4,
1068 ID_OVERRIDE_mask = 0x03 << 28,
1069 ID_OVERRIDE_shift = 28,
1070 TD0_STATUS = 0x000094a4,
1071 TD0_STATUS_num = 4,
1072 BUSY_bit = 1 << 31,
1073 TA_CNTL = 0x00009504,
1074 GRADIENT_CREDIT_mask = 0x1f << 0,
1075 GRADIENT_CREDIT_shift = 0,
1076 WALKER_CREDIT_mask = 0x1f << 8,
1077 WALKER_CREDIT_shift = 8,
1078 ALIGNER_CREDIT_mask = 0x1f << 16,
1079 ALIGNER_CREDIT_shift = 16,
1080 TD_FIFO_CREDIT_mask = 0x3ff << 22,
1081 TD_FIFO_CREDIT_shift = 22,
1082 TA_CNTL_AUX = 0x00009508,
1083 DISABLE_CUBE_WRAP_bit = 1 << 0,
1084 SYNC_GRADIENT_bit = 1 << 24,
1085 SYNC_WALKER_bit = 1 << 25,
1086 SYNC_ALIGNER_bit = 1 << 26,
1087 BILINEAR_PRECISION_bit = 1 << 31,
1088 TA0_CNTL = 0x00009510,
1089 /* ID_OVERRIDE_mask = 0x03 << 28, */
1090 /* ID_OVERRIDE_shift = 28, */
1091 TA1_CNTL = 0x00009514,
1092 /* ID_OVERRIDE_mask = 0x03 << 28, */
1093 /* ID_OVERRIDE_shift = 28, */
1094 TA2_CNTL = 0x00009518,
1095 /* ID_OVERRIDE_mask = 0x03 << 28, */
1096 /* ID_OVERRIDE_shift = 28, */
1097 TA3_CNTL = 0x0000951c,
1098 /* ID_OVERRIDE_mask = 0x03 << 28, */
1099 /* ID_OVERRIDE_shift = 28, */
1100 TA0_STATUS = 0x00009520,
1101 FG_PFIFO_EMPTYB_bit = 1 << 12,
1102 FG_LFIFO_EMPTYB_bit = 1 << 13,
1103 FG_SFIFO_EMPTYB_bit = 1 << 14,
1104 FL_PFIFO_EMPTYB_bit = 1 << 16,
1105 FL_LFIFO_EMPTYB_bit = 1 << 17,
1106 FL_SFIFO_EMPTYB_bit = 1 << 18,
1107 FA_PFIFO_EMPTYB_bit = 1 << 20,
1108 FA_LFIFO_EMPTYB_bit = 1 << 21,
1109 FA_SFIFO_EMPTYB_bit = 1 << 22,
1110 IN_BUSY_bit = 1 << 24,
1111 FG_BUSY_bit = 1 << 25,
1112 FL_BUSY_bit = 1 << 27,
1113 TA_BUSY_bit = 1 << 28,
1114 FA_BUSY_bit = 1 << 29,
1115 AL_BUSY_bit = 1 << 30,
1116 /* BUSY_bit = 1 << 31, */
1117 TA1_STATUS = 0x00009524,
1118 /* FG_PFIFO_EMPTYB_bit = 1 << 12, */
1119 /* FG_LFIFO_EMPTYB_bit = 1 << 13, */
1120 /* FG_SFIFO_EMPTYB_bit = 1 << 14, */
1121 /* FL_PFIFO_EMPTYB_bit = 1 << 16, */
1122 /* FL_LFIFO_EMPTYB_bit = 1 << 17, */
1123 /* FL_SFIFO_EMPTYB_bit = 1 << 18, */
1124 /* FA_PFIFO_EMPTYB_bit = 1 << 20, */
1125 /* FA_LFIFO_EMPTYB_bit = 1 << 21, */
1126 /* FA_SFIFO_EMPTYB_bit = 1 << 22, */
1127 /* IN_BUSY_bit = 1 << 24, */
1128 /* FG_BUSY_bit = 1 << 25, */
1129 /* FL_BUSY_bit = 1 << 27, */
1130 /* TA_BUSY_bit = 1 << 28, */
1131 /* FA_BUSY_bit = 1 << 29, */
1132 /* AL_BUSY_bit = 1 << 30, */
1133 /* BUSY_bit = 1 << 31, */
1134 TA2_STATUS = 0x00009528,
1135 /* FG_PFIFO_EMPTYB_bit = 1 << 12, */
1136 /* FG_LFIFO_EMPTYB_bit = 1 << 13, */
1137 /* FG_SFIFO_EMPTYB_bit = 1 << 14, */
1138 /* FL_PFIFO_EMPTYB_bit = 1 << 16, */
1139 /* FL_LFIFO_EMPTYB_bit = 1 << 17, */
1140 /* FL_SFIFO_EMPTYB_bit = 1 << 18, */
1141 /* FA_PFIFO_EMPTYB_bit = 1 << 20, */
1142 /* FA_LFIFO_EMPTYB_bit = 1 << 21, */
1143 /* FA_SFIFO_EMPTYB_bit = 1 << 22, */
1144 /* IN_BUSY_bit = 1 << 24, */
1145 /* FG_BUSY_bit = 1 << 25, */
1146 /* FL_BUSY_bit = 1 << 27, */
1147 /* TA_BUSY_bit = 1 << 28, */
1148 /* FA_BUSY_bit = 1 << 29, */
1149 /* AL_BUSY_bit = 1 << 30, */
1150 /* BUSY_bit = 1 << 31, */
1151 TA3_STATUS = 0x0000952c,
1152 /* FG_PFIFO_EMPTYB_bit = 1 << 12, */
1153 /* FG_LFIFO_EMPTYB_bit = 1 << 13, */
1154 /* FG_SFIFO_EMPTYB_bit = 1 << 14, */
1155 /* FL_PFIFO_EMPTYB_bit = 1 << 16, */
1156 /* FL_LFIFO_EMPTYB_bit = 1 << 17, */
1157 /* FL_SFIFO_EMPTYB_bit = 1 << 18, */
1158 /* FA_PFIFO_EMPTYB_bit = 1 << 20, */
1159 /* FA_LFIFO_EMPTYB_bit = 1 << 21, */
1160 /* FA_SFIFO_EMPTYB_bit = 1 << 22, */
1161 /* IN_BUSY_bit = 1 << 24, */
1162 /* FG_BUSY_bit = 1 << 25, */
1163 /* FL_BUSY_bit = 1 << 27, */
1164 /* TA_BUSY_bit = 1 << 28, */
1165 /* FA_BUSY_bit = 1 << 29, */
1166 /* AL_BUSY_bit = 1 << 30, */
1167 /* BUSY_bit = 1 << 31, */
1168 TC_STATUS = 0x00009600,
1169 TC_BUSY_bit = 1 << 0,
1170 TC_INVALIDATE = 0x00009604,
1171 START_bit = 1 << 0,
1172 TC_CNTL = 0x00009608,
1173 FORCE_HIT_bit = 1 << 0,
1174 FORCE_MISS_bit = 1 << 1,
1175 L2_SIZE_mask = 0x0f << 5,
1176 L2_SIZE_shift = 5,
1177 _256K = 0x00,
1178 _224K = 0x01,
1179 _192K = 0x02,
1180 _160K = 0x03,
1181 _128K = 0x04,
1182 _96K = 0x05,
1183 _64K = 0x06,
1184 _32K = 0x07,
1185 L2_DISABLE_LATE_HIT_bit = 1 << 9,
1186 DISABLE_VERT_PERF_bit = 1 << 10,
1187 DISABLE_INVAL_BUSY_bit = 1 << 11,
1188 DISABLE_INVAL_SAME_SURFACE_bit = 1 << 12,
1189 PARTITION_MODE_mask = 0x03 << 13,
1190 PARTITION_MODE_shift = 13,
1191 X_VERTEX = 0x00,
1192 MISS_ARB_MODE_bit = 1 << 15,
1193 HIT_ARB_MODE_bit = 1 << 16,
1194 DISABLE_WRITE_DELAY_bit = 1 << 17,
1195 HIT_FIFO_DEPTH_bit = 1 << 18,
1196 VC_CNTL = 0x00009700,
1197 L2_INVALIDATE_bit = 1 << 0,
1198 RESERVED_bit = 1 << 1,
1199 CC_FORCE_MISS_bit = 1 << 2,
1200 MI_CHAN_SEL_mask = 0x03 << 3,
1201 MI_CHAN_SEL_shift = 3,
1202 X_MC0_USES_CH_0_1 = 0x00,
1203 X_MC0_USES_CH_0_3 = 0x01,
1204 X_VC_MC0_IS_ACTIVE = 0x02,
1205 X_VC_MC1_IS_DISABLED = 0x03,
1206 MI_STEER_DISABLE_bit = 1 << 5,
1207 MI_CREDIT_CTR_mask = 0x0f << 6,
1208 MI_CREDIT_CTR_shift = 6,
1209 MI_CREDIT_WE_bit = 1 << 10,
1210 MI_REQ_STALL_THLD_mask = 0x07 << 11,
1211 MI_REQ_STALL_THLD_shift = 11,
1212 X_LATENCY_EXCEEDS_399_CLOCKS = 0x00,
1213 X_LATENCY_EXCEEDS_415_CLOCKS = 0x01,
1214 X_LATENCY_EXCEEDS_431_CLOCKS = 0x02,
1215 X_LATENCY_EXCEEDS_447_CLOCKS = 0x03,
1216 X_LATENCY_EXCEEDS_463_CLOCKS = 0x04,
1217 X_LATENCY_EXCEEDS_479_CLOCKS = 0x05,
1218 X_LATENCY_EXCEEDS_495_CLOCKS = 0x06,
1219 X_LATENCY_EXCEEDS_511_CLOCKS = 0x07,
1220 VC_CNTL__MI_TIMESTAMP_RES_mask = 0x1f << 14,
1221 VC_CNTL__MI_TIMESTAMP_RES_shift = 14,
1222 X_1X_SYSTEM_CLOCK = 0x00,
1223 X_2X_SYSTEM_CLOCK = 0x01,
1224 X_4X_SYSTEM_CLOCK = 0x02,
1225 X_8X_SYSTEM_CLOCK = 0x03,
1226 X_16X_SYSTEM_CLOCK = 0x04,
1227 X_32X_SYSTEM_CLOCK = 0x05,
1228 X_64X_SYSTEM_CLOCK = 0x06,
1229 X_128X_SYSTEM_CLOCK = 0x07,
1230 X_256X_SYSTEM_CLOCK = 0x08,
1231 X_512X_SYSTEM_CLOCK = 0x09,
1232 X_1024X_SYSTEM_CLOCK = 0x0a,
1233 X_2048X_SYSTEM_CLOCK = 0x0b,
1234 X_4092X_SYSTEM_CLOCK = 0x0c,
1235 X_8192X_SYSTEM_CLOCK = 0x0d,
1236 X_16384X_SYSTEM_CLOCK = 0x0e,
1237 X_32768X_SYSTEM_CLOCK = 0x0f,
1238 VC_CNTL_STATUS = 0x00009704,
1239 RP_BUSY_bit = 1 << 0,
1240 RG_BUSY_bit = 1 << 1,
1241 VC_BUSY_bit = 1 << 2,
1242 CLAMP_DETECT_bit = 1 << 3,
1243 VC_CONFIG = 0x00009718,
1244 WRITE_DIS_bit = 1 << 0,
1245 GPR_DATA_PHASE_ADJ_mask = 0x07 << 1,
1246 GPR_DATA_PHASE_ADJ_shift = 1,
1247 X_LATENCY_BASE_0_CYCLES = 0x00,
1248 X_LATENCY_BASE_1_CYCLES = 0x01,
1249 X_LATENCY_BASE_2_CYCLES = 0x02,
1250 X_LATENCY_BASE_3_CYCLES = 0x03,
1251 TD_SIMD_SYNC_ADJ_mask = 0x07 << 4,
1252 TD_SIMD_SYNC_ADJ_shift = 4,
1253 X_0_CYCLES_DELAY = 0x00,
1254 X_1_CYCLES_DELAY = 0x01,
1255 X_2_CYCLES_DELAY = 0x02,
1256 X_3_CYCLES_DELAY = 0x03,
1257 X_4_CYCLES_DELAY = 0x04,
1258 X_5_CYCLES_DELAY = 0x05,
1259 X_6_CYCLES_DELAY = 0x06,
1260 X_7_CYCLES_DELAY = 0x07,
1261 SMX_DC_CTL0 = 0x0000a020,
1262 WR_GATHER_STREAM0_bit = 1 << 0,
1263 WR_GATHER_STREAM1_bit = 1 << 1,
1264 WR_GATHER_STREAM2_bit = 1 << 2,
1265 WR_GATHER_STREAM3_bit = 1 << 3,
1266 WR_GATHER_SCRATCH_bit = 1 << 4,
1267 WR_GATHER_REDUC_BUF_bit = 1 << 5,
1268 WR_GATHER_RING_BUF_bit = 1 << 6,
1269 WR_GATHER_F_BUF_bit = 1 << 7,
1270 DISABLE_CACHES_bit = 1 << 8,
1271 AUTO_FLUSH_INVAL_EN_bit = 1 << 10,
1272 AUTO_FLUSH_EN_bit = 1 << 11,
1273 AUTO_FLUSH_CNT_mask = 0xffff << 12,
1274 AUTO_FLUSH_CNT_shift = 12,
1275 MC_RD_STALL_FACTOR_mask = 0x03 << 28,
1276 MC_RD_STALL_FACTOR_shift = 28,
1277 MC_WR_STALL_FACTOR_mask = 0x03 << 30,
1278 MC_WR_STALL_FACTOR_shift = 30,
1279 SMX_DC_CTL1 = 0x0000a024,
1280 OP_FIFO_SKID_mask = 0x7f << 0,
1281 OP_FIFO_SKID_shift = 0,
1282 CACHE_LINE_SIZE_bit = 1 << 8,
1283 MULTI_FLUSH_MODE_bit = 1 << 9,
1284 MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_mask = 0x0f << 10,
1285 MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID_shift = 10,
1286 DISABLE_WR_GATHER_RD_HIT_FORCE_EVICT_bit = 1 << 16,
1287 DISABLE_WR_GATHER_RD_HIT_COMP_VLDS_CHECK_bit = 1 << 17,
1288 DISABLE_FLUSH_ES_ALSO_INVALS_bit = 1 << 18,
1289 DISABLE_FLUSH_GS_ALSO_INVALS_bit = 1 << 19,
1290 SMX_DC_CTL2 = 0x0000a028,
1291 INVALIDATE_CACHES_bit = 1 << 0,
1292 CACHES_INVALID_bit = 1 << 1,
1293 CACHES_DIRTY_bit = 1 << 2,
1294 FLUSH_ALL_bit = 1 << 4,
1295 FLUSH_GS_THREADS_bit = 1 << 8,
1296 FLUSH_ES_THREADS_bit = 1 << 9,
1297 SMX_DC_MC_INTF_CTL = 0x0000a02c,
1298 MC_RD_REQ_CRED_mask = 0xff << 0,
1299 MC_RD_REQ_CRED_shift = 0,
1300 MC_WR_REQ_CRED_mask = 0xff << 16,
1301 MC_WR_REQ_CRED_shift = 16,
1302 TD_PS_SAMPLER0_BORDER_RED = 0x0000a400,
1303 TD_PS_SAMPLER0_BORDER_RED_num = 18,
1304 TD_PS_SAMPLER0_BORDER_RED_offset = 16,
1305 TD_PS_SAMPLER0_BORDER_GREEN = 0x0000a404,
1306 TD_PS_SAMPLER0_BORDER_GREEN_num = 18,
1307 TD_PS_SAMPLER0_BORDER_GREEN_offset = 16,
1308 TD_PS_SAMPLER0_BORDER_BLUE = 0x0000a408,
1309 TD_PS_SAMPLER0_BORDER_BLUE_num = 18,
1310 TD_PS_SAMPLER0_BORDER_BLUE_offset = 16,
1311 TD_PS_SAMPLER0_BORDER_ALPHA = 0x0000a40c,
1312 TD_PS_SAMPLER0_BORDER_ALPHA_num = 18,
1313 TD_PS_SAMPLER0_BORDER_ALPHA_offset = 16,
1314 TD_VS_SAMPLER0_BORDER_RED = 0x0000a600,
1315 TD_VS_SAMPLER0_BORDER_RED_num = 18,
1316 TD_VS_SAMPLER0_BORDER_RED_offset = 16,
1317 TD_VS_SAMPLER0_BORDER_GREEN = 0x0000a604,
1318 TD_VS_SAMPLER0_BORDER_GREEN_num = 18,
1319 TD_VS_SAMPLER0_BORDER_GREEN_offset = 16,
1320 TD_VS_SAMPLER0_BORDER_BLUE = 0x0000a608,
1321 TD_VS_SAMPLER0_BORDER_BLUE_num = 18,
1322 TD_VS_SAMPLER0_BORDER_BLUE_offset = 16,
1323 TD_VS_SAMPLER0_BORDER_ALPHA = 0x0000a60c,
1324 TD_VS_SAMPLER0_BORDER_ALPHA_num = 18,
1325 TD_VS_SAMPLER0_BORDER_ALPHA_offset = 16,
1326 TD_GS_SAMPLER0_BORDER_RED = 0x0000a800,
1327 TD_GS_SAMPLER0_BORDER_RED_num = 18,
1328 TD_GS_SAMPLER0_BORDER_RED_offset = 16,
1329 TD_GS_SAMPLER0_BORDER_GREEN = 0x0000a804,
1330 TD_GS_SAMPLER0_BORDER_GREEN_num = 18,
1331 TD_GS_SAMPLER0_BORDER_GREEN_offset = 16,
1332 TD_GS_SAMPLER0_BORDER_BLUE = 0x0000a808,
1333 TD_GS_SAMPLER0_BORDER_BLUE_num = 18,
1334 TD_GS_SAMPLER0_BORDER_BLUE_offset = 16,
1335 TD_GS_SAMPLER0_BORDER_ALPHA = 0x0000a80c,
1336 TD_GS_SAMPLER0_BORDER_ALPHA_num = 18,
1337 TD_GS_SAMPLER0_BORDER_ALPHA_offset = 16,
1338 TD_PS_SAMPLER0_CLEARTYPE_KERNEL = 0x0000aa00,
1339 TD_PS_SAMPLER0_CLEARTYPE_KERNEL_num = 18,
1340 TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_mask = 0x07 << 0,
1341 TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH_shift = 0,
1342 TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_mask = 0x07 << 3,
1343 TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT_shift = 3,
1344 DB_DEPTH_SIZE = 0x00028000,
1345 PITCH_TILE_MAX_mask = 0x3ff << 0,
1346 PITCH_TILE_MAX_shift = 0,
1347 SLICE_TILE_MAX_mask = 0xfffff << 10,
1348 SLICE_TILE_MAX_shift = 10,
1349 DB_DEPTH_VIEW = 0x00028004,
1350 SLICE_START_mask = 0x7ff << 0,
1351 SLICE_START_shift = 0,
1352 SLICE_MAX_mask = 0x7ff << 13,
1353 SLICE_MAX_shift = 13,
1354 DB_DEPTH_BASE = 0x0002800c,
1355 DB_DEPTH_INFO = 0x00028010,
1356 DB_DEPTH_INFO__FORMAT_mask = 0x07 << 0,
1357 DB_DEPTH_INFO__FORMAT_shift = 0,
1358 DEPTH_INVALID = 0x00,
1359 DEPTH_16 = 0x01,
1360 DEPTH_X8_24 = 0x02,
1361 DEPTH_8_24 = 0x03,
1362 DEPTH_X8_24_FLOAT = 0x04,
1363 DEPTH_8_24_FLOAT = 0x05,
1364 DEPTH_32_FLOAT = 0x06,
1365 DEPTH_X24_8_32_FLOAT = 0x07,
1366 DB_DEPTH_INFO__READ_SIZE_bit = 1 << 3,
1367 DB_DEPTH_INFO__ARRAY_MODE_mask = 0x0f << 15,
1368 DB_DEPTH_INFO__ARRAY_MODE_shift = 15,
1369 ARRAY_2D_TILED_THIN1 = 0x04,
1370 TILE_SURFACE_ENABLE_bit = 1 << 25,
1371 TILE_COMPACT_bit = 1 << 26,
1372 ZRANGE_PRECISION_bit = 1 << 31,
1373 DB_HTILE_DATA_BASE = 0x00028014,
1374 DB_STENCIL_CLEAR = 0x00028028,
1375 DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0,
1376 DB_STENCIL_CLEAR__CLEAR_shift = 0,
1377 MIN_mask = 0xff << 16,
1378 MIN_shift = 16,
1379 DB_DEPTH_CLEAR = 0x0002802c,
1380 PA_SC_SCREEN_SCISSOR_TL = 0x00028030,
1381 PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
1382 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0,
1383 PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
1384 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16,
1385 PA_SC_SCREEN_SCISSOR_BR = 0x00028034,
1386 PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
1387 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0,
1388 PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
1389 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16,
1390 CB_COLOR0_BASE = 0x00028040,
1391 CB_COLOR0_BASE_num = 8,
1392 CB_COLOR0_SIZE = 0x00028060,
1393 CB_COLOR0_SIZE_num = 8,
1394 /* PITCH_TILE_MAX_mask = 0x3ff << 0, */
1395 /* PITCH_TILE_MAX_shift = 0, */
1396 /* SLICE_TILE_MAX_mask = 0xfffff << 10, */
1397 /* SLICE_TILE_MAX_shift = 10, */
1398 CB_COLOR0_VIEW = 0x00028080,
1399 CB_COLOR0_VIEW_num = 8,
1400 /* SLICE_START_mask = 0x7ff << 0, */
1401 /* SLICE_START_shift = 0, */
1402 /* SLICE_MAX_mask = 0x7ff << 13, */
1403 /* SLICE_MAX_shift = 13, */
1404 CB_COLOR0_INFO = 0x000280a0,
1405 CB_COLOR0_INFO_num = 8,
1406 ENDIAN_mask = 0x03 << 0,
1407 ENDIAN_shift = 0,
1408 ENDIAN_NONE = 0x00,
1409 ENDIAN_8IN16 = 0x01,
1410 ENDIAN_8IN32 = 0x02,
1411 ENDIAN_8IN64 = 0x03,
1412 CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2,
1413 CB_COLOR0_INFO__FORMAT_shift = 2,
1414 COLOR_INVALID = 0x00,
1415 COLOR_8 = 0x01,
1416 COLOR_4_4 = 0x02,
1417 COLOR_3_3_2 = 0x03,
1418 COLOR_16 = 0x05,
1419 COLOR_16_FLOAT = 0x06,
1420 COLOR_8_8 = 0x07,
1421 COLOR_5_6_5 = 0x08,
1422 COLOR_6_5_5 = 0x09,
1423 COLOR_1_5_5_5 = 0x0a,
1424 COLOR_4_4_4_4 = 0x0b,
1425 COLOR_5_5_5_1 = 0x0c,
1426 COLOR_32 = 0x0d,
1427 COLOR_32_FLOAT = 0x0e,
1428 COLOR_16_16 = 0x0f,
1429 COLOR_16_16_FLOAT = 0x10,
1430 COLOR_8_24 = 0x11,
1431 COLOR_8_24_FLOAT = 0x12,
1432 COLOR_24_8 = 0x13,
1433 COLOR_24_8_FLOAT = 0x14,
1434 COLOR_10_11_11 = 0x15,
1435 COLOR_10_11_11_FLOAT = 0x16,
1436 COLOR_11_11_10 = 0x17,
1437 COLOR_11_11_10_FLOAT = 0x18,
1438 COLOR_2_10_10_10 = 0x19,
1439 COLOR_8_8_8_8 = 0x1a,
1440 COLOR_10_10_10_2 = 0x1b,
1441 COLOR_X24_8_32_FLOAT = 0x1c,
1442 COLOR_32_32 = 0x1d,
1443 COLOR_32_32_FLOAT = 0x1e,
1444 COLOR_16_16_16_16 = 0x1f,
1445 COLOR_16_16_16_16_FLOAT = 0x20,
1446 COLOR_32_32_32_32 = 0x22,
1447 COLOR_32_32_32_32_FLOAT = 0x23,
1448 CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8,
1449 CB_COLOR0_INFO__ARRAY_MODE_shift = 8,
1450 ARRAY_LINEAR_GENERAL = 0x00,
1451 ARRAY_LINEAR_ALIGNED = 0x01,
1452 /* ARRAY_2D_TILED_THIN1 = 0x04, */
1453 NUMBER_TYPE_mask = 0x07 << 12,
1454 NUMBER_TYPE_shift = 12,
1455 NUMBER_UNORM = 0x00,
1456 NUMBER_SNORM = 0x01,
1457 NUMBER_USCALED = 0x02,
1458 NUMBER_SSCALED = 0x03,
1459 NUMBER_UINT = 0x04,
1460 NUMBER_SINT = 0x05,
1461 NUMBER_SRGB = 0x06,
1462 NUMBER_FLOAT = 0x07,
1463 CB_COLOR0_INFO__READ_SIZE_bit = 1 << 15,
1464 COMP_SWAP_mask = 0x03 << 16,
1465 COMP_SWAP_shift = 16,
1466 SWAP_STD = 0x00,
1467 SWAP_ALT = 0x01,
1468 SWAP_STD_REV = 0x02,
1469 SWAP_ALT_REV = 0x03,
1470 CB_COLOR0_INFO__TILE_MODE_mask = 0x03 << 18,
1471 CB_COLOR0_INFO__TILE_MODE_shift = 18,
1472 TILE_DISABLE = 0x00,
1473 TILE_CLEAR_ENABLE = 0x01,
1474 TILE_FRAG_ENABLE = 0x02,
1475 BLEND_CLAMP_bit = 1 << 20,
1476 CLEAR_COLOR_bit = 1 << 21,
1477 BLEND_BYPASS_bit = 1 << 22,
1478 BLEND_FLOAT32_bit = 1 << 23,
1479 SIMPLE_FLOAT_bit = 1 << 24,
1480 CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 25,
1481 /* TILE_COMPACT_bit = 1 << 26, */
1482 SOURCE_FORMAT_bit = 1 << 27,
1483 CB_COLOR0_TILE = 0x000280c0,
1484 CB_COLOR0_TILE_num = 8,
1485 CB_COLOR0_FRAG = 0x000280e0,
1486 CB_COLOR0_FRAG_num = 8,
1487 CB_COLOR0_MASK = 0x00028100,
1488 CB_COLOR0_MASK_num = 8,
1489 CMASK_BLOCK_MAX_mask = 0xfff << 0,
1490 CMASK_BLOCK_MAX_shift = 0,
1491 FMASK_TILE_MAX_mask = 0xfffff << 12,
1492 FMASK_TILE_MAX_shift = 12,
1493 CB_CLEAR_RED = 0x00028120,
1494 CB_CLEAR_GREEN = 0x00028124,
1495 CB_CLEAR_BLUE = 0x00028128,
1496 CB_CLEAR_ALPHA = 0x0002812c,
1497 SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140,
1498 SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16,
1499 SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0,
1500 SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0,
1501 SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180,
1502 SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16,
1503 SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0,
1504 SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0,
1505 SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0,
1506 SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16,
1507 SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0,
1508 SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0,
1509 PA_SC_WINDOW_OFFSET = 0x00028200,
1510 WINDOW_X_OFFSET_mask = 0x7fff << 0,
1511 WINDOW_X_OFFSET_shift = 0,
1512 WINDOW_Y_OFFSET_mask = 0x7fff << 16,
1513 WINDOW_Y_OFFSET_shift = 16,
1514 PA_SC_WINDOW_SCISSOR_TL = 0x00028204,
1515 PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x3fff << 0,
1516 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0,
1517 PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x3fff << 16,
1518 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16,
1519 WINDOW_OFFSET_DISABLE_bit = 1 << 31,
1520 PA_SC_WINDOW_SCISSOR_BR = 0x00028208,
1521 PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x3fff << 0,
1522 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0,
1523 PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x3fff << 16,
1524 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16,
1525 PA_SC_CLIPRECT_RULE = 0x0002820c,
1526 CLIP_RULE_mask = 0xffff << 0,
1527 CLIP_RULE_shift = 0,
1528 PA_SC_CLIPRECT_0_TL = 0x00028210,
1529 PA_SC_CLIPRECT_0_TL_num = 4,
1530 PA_SC_CLIPRECT_0_TL_offset = 8,
1531 PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x3fff << 0,
1532 PA_SC_CLIPRECT_0_TL__TL_X_shift = 0,
1533 PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x3fff << 16,
1534 PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16,
1535 PA_SC_CLIPRECT_0_BR = 0x00028214,
1536 PA_SC_CLIPRECT_0_BR_num = 4,
1537 PA_SC_CLIPRECT_0_BR_offset = 8,
1538 PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x3fff << 0,
1539 PA_SC_CLIPRECT_0_BR__BR_X_shift = 0,
1540 PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x3fff << 16,
1541 PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16,
1542 CB_TARGET_MASK = 0x00028238,
1543 TARGET0_ENABLE_mask = 0x0f << 0,
1544 TARGET0_ENABLE_shift = 0,
1545 TARGET1_ENABLE_mask = 0x0f << 4,
1546 TARGET1_ENABLE_shift = 4,
1547 TARGET2_ENABLE_mask = 0x0f << 8,
1548 TARGET2_ENABLE_shift = 8,
1549 TARGET3_ENABLE_mask = 0x0f << 12,
1550 TARGET3_ENABLE_shift = 12,
1551 TARGET4_ENABLE_mask = 0x0f << 16,
1552 TARGET4_ENABLE_shift = 16,
1553 TARGET5_ENABLE_mask = 0x0f << 20,
1554 TARGET5_ENABLE_shift = 20,
1555 TARGET6_ENABLE_mask = 0x0f << 24,
1556 TARGET6_ENABLE_shift = 24,
1557 TARGET7_ENABLE_mask = 0x0f << 28,
1558 TARGET7_ENABLE_shift = 28,
1559 CB_SHADER_MASK = 0x0002823c,
1560 OUTPUT0_ENABLE_mask = 0x0f << 0,
1561 OUTPUT0_ENABLE_shift = 0,
1562 OUTPUT1_ENABLE_mask = 0x0f << 4,
1563 OUTPUT1_ENABLE_shift = 4,
1564 OUTPUT2_ENABLE_mask = 0x0f << 8,
1565 OUTPUT2_ENABLE_shift = 8,
1566 OUTPUT3_ENABLE_mask = 0x0f << 12,
1567 OUTPUT3_ENABLE_shift = 12,
1568 OUTPUT4_ENABLE_mask = 0x0f << 16,
1569 OUTPUT4_ENABLE_shift = 16,
1570 OUTPUT5_ENABLE_mask = 0x0f << 20,
1571 OUTPUT5_ENABLE_shift = 20,
1572 OUTPUT6_ENABLE_mask = 0x0f << 24,
1573 OUTPUT6_ENABLE_shift = 24,
1574 OUTPUT7_ENABLE_mask = 0x0f << 28,
1575 OUTPUT7_ENABLE_shift = 28,
1576 PA_SC_GENERIC_SCISSOR_TL = 0x00028240,
1577 PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x3fff << 0,
1578 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0,
1579 PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x3fff << 16,
1580 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16,
1581 /* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */
1582 PA_SC_GENERIC_SCISSOR_BR = 0x00028244,
1583 PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x3fff << 0,
1584 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0,
1585 PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x3fff << 16,
1586 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16,
1587 PA_SC_VPORT_SCISSOR_0_TL = 0x00028250,
1588 PA_SC_VPORT_SCISSOR_0_TL_num = 16,
1589 PA_SC_VPORT_SCISSOR_0_TL_offset = 8,
1590 PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x3fff << 0,
1591 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0,
1592 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x3fff << 16,
1593 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16,
1594 /* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */
1595 PA_SC_VPORT_SCISSOR_0_BR = 0x00028254,
1596 PA_SC_VPORT_SCISSOR_0_BR_num = 16,
1597 PA_SC_VPORT_SCISSOR_0_BR_offset = 8,
1598 PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x3fff << 0,
1599 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0,
1600 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x3fff << 16,
1601 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16,
1602 PA_SC_VPORT_ZMIN_0 = 0x000282d0,
1603 PA_SC_VPORT_ZMIN_0_num = 16,
1604 PA_SC_VPORT_ZMIN_0_offset = 8,
1605 PA_SC_VPORT_ZMAX_0 = 0x000282d4,
1606 PA_SC_VPORT_ZMAX_0_num = 16,
1607 PA_SC_VPORT_ZMAX_0_offset = 8,
1608 SX_MISC = 0x00028350,
1609 MULTIPASS_bit = 1 << 0,
1610 SQ_VTX_SEMANTIC_0 = 0x00028380,
1611 SQ_VTX_SEMANTIC_0_num = 32,
1612 /* SEMANTIC_ID_mask = 0xff << 0, */
1613 /* SEMANTIC_ID_shift = 0, */
1614 VGT_MAX_VTX_INDX = 0x00028400,
1615 VGT_MIN_VTX_INDX = 0x00028404,
1616 VGT_INDX_OFFSET = 0x00028408,
1617 VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c,
1618 SX_ALPHA_TEST_CONTROL = 0x00028410,
1619 ALPHA_FUNC_mask = 0x07 << 0,
1620 ALPHA_FUNC_shift = 0,
1621 REF_NEVER = 0x00,
1622 REF_LESS = 0x01,
1623 REF_EQUAL = 0x02,
1624 REF_LEQUAL = 0x03,
1625 REF_GREATER = 0x04,
1626 REF_NOTEQUAL = 0x05,
1627 REF_GEQUAL = 0x06,
1628 REF_ALWAYS = 0x07,
1629 ALPHA_TEST_ENABLE_bit = 1 << 3,
1630 ALPHA_TEST_BYPASS_bit = 1 << 8,
1631 CB_BLEND_RED = 0x00028414,
1632 CB_BLEND_GREEN = 0x00028418,
1633 CB_BLEND_BLUE = 0x0002841c,
1634 CB_BLEND_ALPHA = 0x00028420,
1635 CB_FOG_RED = 0x00028424,
1636 CB_FOG_GREEN = 0x00028428,
1637 CB_FOG_BLUE = 0x0002842c,
1638 DB_STENCILREFMASK = 0x00028430,
1639 STENCILREF_mask = 0xff << 0,
1640 STENCILREF_shift = 0,
1641 STENCILMASK_mask = 0xff << 8,
1642 STENCILMASK_shift = 8,
1643 STENCILWRITEMASK_mask = 0xff << 16,
1644 STENCILWRITEMASK_shift = 16,
1645 DB_STENCILREFMASK_BF = 0x00028434,
1646 STENCILREF_BF_mask = 0xff << 0,
1647 STENCILREF_BF_shift = 0,
1648 STENCILMASK_BF_mask = 0xff << 8,
1649 STENCILMASK_BF_shift = 8,
1650 STENCILWRITEMASK_BF_mask = 0xff << 16,
1651 STENCILWRITEMASK_BF_shift = 16,
1652 SX_ALPHA_REF = 0x00028438,
1653 PA_CL_VPORT_XSCALE_0 = 0x0002843c,
1654 PA_CL_VPORT_XSCALE_0_num = 16,
1655 PA_CL_VPORT_XSCALE_0_offset = 24,
1656 PA_CL_VPORT_XOFFSET_0 = 0x00028440,
1657 PA_CL_VPORT_XOFFSET_0_num = 16,
1658 PA_CL_VPORT_XOFFSET_0_offset = 24,
1659 PA_CL_VPORT_YSCALE_0 = 0x00028444,
1660 PA_CL_VPORT_YSCALE_0_num = 16,
1661 PA_CL_VPORT_YSCALE_0_offset = 24,
1662 PA_CL_VPORT_YOFFSET_0 = 0x00028448,
1663 PA_CL_VPORT_YOFFSET_0_num = 16,
1664 PA_CL_VPORT_YOFFSET_0_offset = 24,
1665 PA_CL_VPORT_ZSCALE_0 = 0x0002844c,
1666 PA_CL_VPORT_ZSCALE_0_num = 16,
1667 PA_CL_VPORT_ZSCALE_0_offset = 24,
1668 PA_CL_VPORT_ZOFFSET_0 = 0x00028450,
1669 PA_CL_VPORT_ZOFFSET_0_num = 16,
1670 PA_CL_VPORT_ZOFFSET_0_offset = 24,
1671 SPI_VS_OUT_ID_0 = 0x00028614,
1672 SPI_VS_OUT_ID_0_num = 10,
1673 SEMANTIC_0_mask = 0xff << 0,
1674 SEMANTIC_0_shift = 0,
1675 SEMANTIC_1_mask = 0xff << 8,
1676 SEMANTIC_1_shift = 8,
1677 SEMANTIC_2_mask = 0xff << 16,
1678 SEMANTIC_2_shift = 16,
1679 SEMANTIC_3_mask = 0xff << 24,
1680 SEMANTIC_3_shift = 24,
1681 SPI_PS_INPUT_CNTL_0 = 0x00028644,
1682 SPI_PS_INPUT_CNTL_0_num = 32,
1683 SEMANTIC_mask = 0xff << 0,
1684 SEMANTIC_shift = 0,
1685 DEFAULT_VAL_mask = 0x03 << 8,
1686 DEFAULT_VAL_shift = 8,
1687 X_0_0F = 0x00,
1688 FLAT_SHADE_bit = 1 << 10,
1689 SEL_CENTROID_bit = 1 << 11,
1690 SEL_LINEAR_bit = 1 << 12,
1691 CYL_WRAP_mask = 0x0f << 13,
1692 CYL_WRAP_shift = 13,
1693 PT_SPRITE_TEX_bit = 1 << 17,
1694 SEL_SAMPLE_bit = 1 << 18,
1695 SPI_VS_OUT_CONFIG = 0x000286c4,
1696 VS_PER_COMPONENT_bit = 1 << 0,
1697 VS_EXPORT_COUNT_mask = 0x1f << 1,
1698 VS_EXPORT_COUNT_shift = 1,
1699 VS_EXPORTS_FOG_bit = 1 << 8,
1700 VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9,
1701 VS_OUT_FOG_VEC_ADDR_shift = 9,
1702 SPI_PS_IN_CONTROL_0 = 0x000286cc,
1703 NUM_INTERP_mask = 0x3f << 0,
1704 NUM_INTERP_shift = 0,
1705 POSITION_ENA_bit = 1 << 8,
1706 POSITION_CENTROID_bit = 1 << 9,
1707 POSITION_ADDR_mask = 0x1f << 10,
1708 POSITION_ADDR_shift = 10,
1709 PARAM_GEN_mask = 0x0f << 15,
1710 PARAM_GEN_shift = 15,
1711 PARAM_GEN_ADDR_mask = 0x7f << 19,
1712 PARAM_GEN_ADDR_shift = 19,
1713 BARYC_SAMPLE_CNTL_mask = 0x03 << 26,
1714 BARYC_SAMPLE_CNTL_shift = 26,
1715 CENTROIDS_ONLY = 0x00,
1716 CENTERS_ONLY = 0x01,
1717 CENTROIDS_AND_CENTERS = 0x02,
1718 UNDEF = 0x03,
1719 PERSP_GRADIENT_ENA_bit = 1 << 28,
1720 LINEAR_GRADIENT_ENA_bit = 1 << 29,
1721 POSITION_SAMPLE_bit = 1 << 30,
1722 BARYC_AT_SAMPLE_ENA_bit = 1 << 31,
1723 SPI_PS_IN_CONTROL_1 = 0x000286d0,
1724 GEN_INDEX_PIX_bit = 1 << 0,
1725 GEN_INDEX_PIX_ADDR_mask = 0x7f << 1,
1726 GEN_INDEX_PIX_ADDR_shift = 1,
1727 FRONT_FACE_ENA_bit = 1 << 8,
1728 FRONT_FACE_CHAN_mask = 0x03 << 9,
1729 FRONT_FACE_CHAN_shift = 9,
1730 FRONT_FACE_ALL_BITS_bit = 1 << 11,
1731 FRONT_FACE_ADDR_mask = 0x1f << 12,
1732 FRONT_FACE_ADDR_shift = 12,
1733 FOG_ADDR_mask = 0x7f << 17,
1734 FOG_ADDR_shift = 17,
1735 FIXED_PT_POSITION_ENA_bit = 1 << 24,
1736 FIXED_PT_POSITION_ADDR_mask = 0x1f << 25,
1737 FIXED_PT_POSITION_ADDR_shift = 25,
1738 SPI_INTERP_CONTROL_0 = 0x000286d4,
1739 FLAT_SHADE_ENA_bit = 1 << 0,
1740 PNT_SPRITE_ENA_bit = 1 << 1,
1741 PNT_SPRITE_OVRD_X_mask = 0x07 << 2,
1742 PNT_SPRITE_OVRD_X_shift = 2,
1743 SPI_PNT_SPRITE_SEL_0 = 0x00,
1744 SPI_PNT_SPRITE_SEL_1 = 0x01,
1745 SPI_PNT_SPRITE_SEL_S = 0x02,
1746 SPI_PNT_SPRITE_SEL_T = 0x03,
1747 SPI_PNT_SPRITE_SEL_NONE = 0x04,
1748 PNT_SPRITE_OVRD_Y_mask = 0x07 << 5,
1749 PNT_SPRITE_OVRD_Y_shift = 5,
1750 /* SPI_PNT_SPRITE_SEL_0 = 0x00, */
1751 /* SPI_PNT_SPRITE_SEL_1 = 0x01, */
1752 /* SPI_PNT_SPRITE_SEL_S = 0x02, */
1753 /* SPI_PNT_SPRITE_SEL_T = 0x03, */
1754 /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
1755 PNT_SPRITE_OVRD_Z_mask = 0x07 << 8,
1756 PNT_SPRITE_OVRD_Z_shift = 8,
1757 /* SPI_PNT_SPRITE_SEL_0 = 0x00, */
1758 /* SPI_PNT_SPRITE_SEL_1 = 0x01, */
1759 /* SPI_PNT_SPRITE_SEL_S = 0x02, */
1760 /* SPI_PNT_SPRITE_SEL_T = 0x03, */
1761 /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
1762 PNT_SPRITE_OVRD_W_mask = 0x07 << 11,
1763 PNT_SPRITE_OVRD_W_shift = 11,
1764 /* SPI_PNT_SPRITE_SEL_0 = 0x00, */
1765 /* SPI_PNT_SPRITE_SEL_1 = 0x01, */
1766 /* SPI_PNT_SPRITE_SEL_S = 0x02, */
1767 /* SPI_PNT_SPRITE_SEL_T = 0x03, */
1768 /* SPI_PNT_SPRITE_SEL_NONE = 0x04, */
1769 PNT_SPRITE_TOP_1_bit = 1 << 14,
1770 SPI_INPUT_Z = 0x000286d8,
1771 PROVIDE_Z_TO_SPI_bit = 1 << 0,
1772 SPI_FOG_CNTL = 0x000286dc,
1773 PASS_FOG_THROUGH_PS_bit = 1 << 0,
1774 PIXEL_FOG_FUNC_mask = 0x03 << 1,
1775 PIXEL_FOG_FUNC_shift = 1,
1776 SPI_FOG_NONE = 0x00,
1777 SPI_FOG_EXP = 0x01,
1778 SPI_FOG_EXP2 = 0x02,
1779 SPI_FOG_LINEAR = 0x03,
1780 PIXEL_FOG_SRC_SEL_bit = 1 << 3,
1781 VS_FOG_CLAMP_DISABLE_bit = 1 << 4,
1782 SPI_FOG_FUNC_SCALE = 0x000286e0,
1783 SPI_FOG_FUNC_BIAS = 0x000286e4,
1784 CB_BLEND0_CONTROL = 0x00028780,
1785 CB_BLEND0_CONTROL_num = 8,
1786 COLOR_SRCBLEND_mask = 0x1f << 0,
1787 COLOR_SRCBLEND_shift = 0,
1788 COLOR_COMB_FCN_mask = 0x07 << 5,
1789 COLOR_COMB_FCN_shift = 5,
1790 COLOR_DESTBLEND_mask = 0x1f << 8,
1791 COLOR_DESTBLEND_shift = 8,
1792 OPACITY_WEIGHT_bit = 1 << 13,
1793 ALPHA_SRCBLEND_mask = 0x1f << 16,
1794 ALPHA_SRCBLEND_shift = 16,
1795 ALPHA_COMB_FCN_mask = 0x07 << 21,
1796 ALPHA_COMB_FCN_shift = 21,
1797 ALPHA_DESTBLEND_mask = 0x1f << 24,
1798 ALPHA_DESTBLEND_shift = 24,
1799 SEPARATE_ALPHA_BLEND_bit = 1 << 29,
1800 VGT_DMA_BASE_HI = 0x000287e4,
1801 VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0,
1802 VGT_DMA_BASE_HI__BASE_ADDR_shift = 0,
1803 VGT_DMA_BASE = 0x000287e8,
1804 VGT_DRAW_INITIATOR = 0x000287f0,
1805 SOURCE_SELECT_mask = 0x03 << 0,
1806 SOURCE_SELECT_shift = 0,
1807 DI_SRC_SEL_DMA = 0x00,
1808 DI_SRC_SEL_IMMEDIATE = 0x01,
1809 DI_SRC_SEL_AUTO_INDEX = 0x02,
1810 DI_SRC_SEL_RESERVED = 0x03,
1811 MAJOR_MODE_mask = 0x03 << 2,
1812 MAJOR_MODE_shift = 2,
1813 DI_MAJOR_MODE_0 = 0x00,
1814 DI_MAJOR_MODE_1 = 0x01,
1815 SPRITE_EN_bit = 1 << 4,
1816 NOT_EOP_bit = 1 << 5,
1817 USE_OPAQUE_bit = 1 << 6,
1818 VGT_IMMED_DATA = 0x000287f4,
1819 VGT_EVENT_ADDRESS_REG = 0x000287f8,
1820 ADDRESS_LOW_mask = 0xfffffff << 0,
1821 ADDRESS_LOW_shift = 0,
1822 DB_DEPTH_CONTROL = 0x00028800,
1823 STENCIL_ENABLE_bit = 1 << 0,
1824 Z_ENABLE_bit = 1 << 1,
1825 Z_WRITE_ENABLE_bit = 1 << 2,
1826 ZFUNC_mask = 0x07 << 4,
1827 ZFUNC_shift = 4,
1828 FRAG_NEVER = 0x00,
1829 FRAG_LESS = 0x01,
1830 FRAG_EQUAL = 0x02,
1831 FRAG_LEQUAL = 0x03,
1832 FRAG_GREATER = 0x04,
1833 FRAG_NOTEQUAL = 0x05,
1834 FRAG_GEQUAL = 0x06,
1835 FRAG_ALWAYS = 0x07,
1836 BACKFACE_ENABLE_bit = 1 << 7,
1837 STENCILFUNC_mask = 0x07 << 8,
1838 STENCILFUNC_shift = 8,
1839 /* REF_NEVER = 0x00, */
1840 /* REF_LESS = 0x01, */
1841 /* REF_EQUAL = 0x02, */
1842 /* REF_LEQUAL = 0x03, */
1843 /* REF_GREATER = 0x04, */
1844 /* REF_NOTEQUAL = 0x05, */
1845 /* REF_GEQUAL = 0x06, */
1846 /* REF_ALWAYS = 0x07, */
1847 STENCILFAIL_mask = 0x07 << 11,
1848 STENCILFAIL_shift = 11,
1849 STENCIL_KEEP = 0x00,
1850 STENCIL_ZERO = 0x01,
1851 STENCIL_REPLACE = 0x02,
1852 STENCIL_INCR_CLAMP = 0x03,
1853 STENCIL_DECR_CLAMP = 0x04,
1854 STENCIL_INVERT = 0x05,
1855 STENCIL_INCR_WRAP = 0x06,
1856 STENCIL_DECR_WRAP = 0x07,
1857 STENCILZPASS_mask = 0x07 << 14,
1858 STENCILZPASS_shift = 14,
1859 /* STENCIL_KEEP = 0x00, */
1860 /* STENCIL_ZERO = 0x01, */
1861 /* STENCIL_REPLACE = 0x02, */
1862 /* STENCIL_INCR_CLAMP = 0x03, */
1863 /* STENCIL_DECR_CLAMP = 0x04, */
1864 /* STENCIL_INVERT = 0x05, */
1865 /* STENCIL_INCR_WRAP = 0x06, */
1866 /* STENCIL_DECR_WRAP = 0x07, */
1867 STENCILZFAIL_mask = 0x07 << 17,
1868 STENCILZFAIL_shift = 17,
1869 /* STENCIL_KEEP = 0x00, */
1870 /* STENCIL_ZERO = 0x01, */
1871 /* STENCIL_REPLACE = 0x02, */
1872 /* STENCIL_INCR_CLAMP = 0x03, */
1873 /* STENCIL_DECR_CLAMP = 0x04, */
1874 /* STENCIL_INVERT = 0x05, */
1875 /* STENCIL_INCR_WRAP = 0x06, */
1876 /* STENCIL_DECR_WRAP = 0x07, */
1877 STENCILFUNC_BF_mask = 0x07 << 20,
1878 STENCILFUNC_BF_shift = 20,
1879 /* REF_NEVER = 0x00, */
1880 /* REF_LESS = 0x01, */
1881 /* REF_EQUAL = 0x02, */
1882 /* REF_LEQUAL = 0x03, */
1883 /* REF_GREATER = 0x04, */
1884 /* REF_NOTEQUAL = 0x05, */
1885 /* REF_GEQUAL = 0x06, */
1886 /* REF_ALWAYS = 0x07, */
1887 STENCILFAIL_BF_mask = 0x07 << 23,
1888 STENCILFAIL_BF_shift = 23,
1889 /* STENCIL_KEEP = 0x00, */
1890 /* STENCIL_ZERO = 0x01, */
1891 /* STENCIL_REPLACE = 0x02, */
1892 /* STENCIL_INCR_CLAMP = 0x03, */
1893 /* STENCIL_DECR_CLAMP = 0x04, */
1894 /* STENCIL_INVERT = 0x05, */
1895 /* STENCIL_INCR_WRAP = 0x06, */
1896 /* STENCIL_DECR_WRAP = 0x07, */
1897 STENCILZPASS_BF_mask = 0x07 << 26,
1898 STENCILZPASS_BF_shift = 26,
1899 /* STENCIL_KEEP = 0x00, */
1900 /* STENCIL_ZERO = 0x01, */
1901 /* STENCIL_REPLACE = 0x02, */
1902 /* STENCIL_INCR_CLAMP = 0x03, */
1903 /* STENCIL_DECR_CLAMP = 0x04, */
1904 /* STENCIL_INVERT = 0x05, */
1905 /* STENCIL_INCR_WRAP = 0x06, */
1906 /* STENCIL_DECR_WRAP = 0x07, */
1907 STENCILZFAIL_BF_mask = 0x07 << 29,
1908 STENCILZFAIL_BF_shift = 29,
1909 /* STENCIL_KEEP = 0x00, */
1910 /* STENCIL_ZERO = 0x01, */
1911 /* STENCIL_REPLACE = 0x02, */
1912 /* STENCIL_INCR_CLAMP = 0x03, */
1913 /* STENCIL_DECR_CLAMP = 0x04, */
1914 /* STENCIL_INVERT = 0x05, */
1915 /* STENCIL_INCR_WRAP = 0x06, */
1916 /* STENCIL_DECR_WRAP = 0x07, */
1917 CB_BLEND_CONTROL = 0x00028804,
1918 /* COLOR_SRCBLEND_mask = 0x1f << 0, */
1919 /* COLOR_SRCBLEND_shift = 0, */
1920 BLEND_ZERO = 0x00,
1921 BLEND_ONE = 0x01,
1922 BLEND_SRC_COLOR = 0x02,
1923 BLEND_ONE_MINUS_SRC_COLOR = 0x03,
1924 BLEND_SRC_ALPHA = 0x04,
1925 BLEND_ONE_MINUS_SRC_ALPHA = 0x05,
1926 BLEND_DST_ALPHA = 0x06,
1927 BLEND_ONE_MINUS_DST_ALPHA = 0x07,
1928 BLEND_DST_COLOR = 0x08,
1929 BLEND_ONE_MINUS_DST_COLOR = 0x09,
1930 BLEND_SRC_ALPHA_SATURATE = 0x0a,
1931 BLEND_BOTH_SRC_ALPHA = 0x0b,
1932 BLEND_BOTH_INV_SRC_ALPHA = 0x0c,
1933 BLEND_CONSTANT_COLOR = 0x0d,
1934 BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e,
1935 BLEND_SRC1_COLOR = 0x0f,
1936 BLEND_INV_SRC1_COLOR = 0x10,
1937 BLEND_SRC1_ALPHA = 0x11,
1938 BLEND_INV_SRC1_ALPHA = 0x12,
1939 BLEND_CONSTANT_ALPHA = 0x13,
1940 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14,
1941 /* COLOR_COMB_FCN_mask = 0x07 << 5, */
1942 /* COLOR_COMB_FCN_shift = 5, */
1943 COMB_DST_PLUS_SRC = 0x00,
1944 COMB_SRC_MINUS_DST = 0x01,
1945 COMB_MIN_DST_SRC = 0x02,
1946 COMB_MAX_DST_SRC = 0x03,
1947 COMB_DST_MINUS_SRC = 0x04,
1948 /* COLOR_DESTBLEND_mask = 0x1f << 8, */
1949 /* COLOR_DESTBLEND_shift = 8, */
1950 /* BLEND_ZERO = 0x00, */
1951 /* BLEND_ONE = 0x01, */
1952 /* BLEND_SRC_COLOR = 0x02, */
1953 /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
1954 /* BLEND_SRC_ALPHA = 0x04, */
1955 /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
1956 /* BLEND_DST_ALPHA = 0x06, */
1957 /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
1958 /* BLEND_DST_COLOR = 0x08, */
1959 /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
1960 /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
1961 /* BLEND_BOTH_SRC_ALPHA = 0x0b, */
1962 /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
1963 /* BLEND_CONSTANT_COLOR = 0x0d, */
1964 /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
1965 /* BLEND_SRC1_COLOR = 0x0f, */
1966 /* BLEND_INV_SRC1_COLOR = 0x10, */
1967 /* BLEND_SRC1_ALPHA = 0x11, */
1968 /* BLEND_INV_SRC1_ALPHA = 0x12, */
1969 /* BLEND_CONSTANT_ALPHA = 0x13, */
1970 /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
1971 /* OPACITY_WEIGHT_bit = 1 << 13, */
1972 /* ALPHA_SRCBLEND_mask = 0x1f << 16, */
1973 /* ALPHA_SRCBLEND_shift = 16, */
1974 /* BLEND_ZERO = 0x00, */
1975 /* BLEND_ONE = 0x01, */
1976 /* BLEND_SRC_COLOR = 0x02, */
1977 /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
1978 /* BLEND_SRC_ALPHA = 0x04, */
1979 /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
1980 /* BLEND_DST_ALPHA = 0x06, */
1981 /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
1982 /* BLEND_DST_COLOR = 0x08, */
1983 /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
1984 /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
1985 /* BLEND_BOTH_SRC_ALPHA = 0x0b, */
1986 /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
1987 /* BLEND_CONSTANT_COLOR = 0x0d, */
1988 /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
1989 /* BLEND_SRC1_COLOR = 0x0f, */
1990 /* BLEND_INV_SRC1_COLOR = 0x10, */
1991 /* BLEND_SRC1_ALPHA = 0x11, */
1992 /* BLEND_INV_SRC1_ALPHA = 0x12, */
1993 /* BLEND_CONSTANT_ALPHA = 0x13, */
1994 /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
1995 /* ALPHA_COMB_FCN_mask = 0x07 << 21, */
1996 /* ALPHA_COMB_FCN_shift = 21, */
1997 /* COMB_DST_PLUS_SRC = 0x00, */
1998 /* COMB_SRC_MINUS_DST = 0x01, */
1999 /* COMB_MIN_DST_SRC = 0x02, */
2000 /* COMB_MAX_DST_SRC = 0x03, */
2001 /* COMB_DST_MINUS_SRC = 0x04, */
2002 /* ALPHA_DESTBLEND_mask = 0x1f << 24, */
2003 /* ALPHA_DESTBLEND_shift = 24, */
2004 /* BLEND_ZERO = 0x00, */
2005 /* BLEND_ONE = 0x01, */
2006 /* BLEND_SRC_COLOR = 0x02, */
2007 /* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */
2008 /* BLEND_SRC_ALPHA = 0x04, */
2009 /* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */
2010 /* BLEND_DST_ALPHA = 0x06, */
2011 /* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */
2012 /* BLEND_DST_COLOR = 0x08, */
2013 /* BLEND_ONE_MINUS_DST_COLOR = 0x09, */
2014 /* BLEND_SRC_ALPHA_SATURATE = 0x0a, */
2015 /* BLEND_BOTH_SRC_ALPHA = 0x0b, */
2016 /* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */
2017 /* BLEND_CONSTANT_COLOR = 0x0d, */
2018 /* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */
2019 /* BLEND_SRC1_COLOR = 0x0f, */
2020 /* BLEND_INV_SRC1_COLOR = 0x10, */
2021 /* BLEND_SRC1_ALPHA = 0x11, */
2022 /* BLEND_INV_SRC1_ALPHA = 0x12, */
2023 /* BLEND_CONSTANT_ALPHA = 0x13, */
2024 /* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */
2025 /* SEPARATE_ALPHA_BLEND_bit = 1 << 29, */
2026 CB_COLOR_CONTROL = 0x00028808,
2027 FOG_ENABLE_bit = 1 << 0,
2028 MULTIWRITE_ENABLE_bit = 1 << 1,
2029 DITHER_ENABLE_bit = 1 << 2,
2030 DEGAMMA_ENABLE_bit = 1 << 3,
2031 SPECIAL_OP_mask = 0x07 << 4,
2032 SPECIAL_OP_shift = 4,
2033 SPECIAL_NORMAL = 0x00,
2034 SPECIAL_DISABLE = 0x01,
2035 SPECIAL_FAST_CLEAR = 0x02,
2036 SPECIAL_FORCE_CLEAR = 0x03,
2037 SPECIAL_EXPAND_COLOR = 0x04,
2038 SPECIAL_EXPAND_TEXTURE = 0x05,
2039 SPECIAL_EXPAND_SAMPLES = 0x06,
2040 SPECIAL_RESOLVE_BOX = 0x07,
2041 PER_MRT_BLEND_bit = 1 << 7,
2042 TARGET_BLEND_ENABLE_mask = 0xff << 8,
2043 TARGET_BLEND_ENABLE_shift = 8,
2044 ROP3_mask = 0xff << 16,
2045 ROP3_shift = 16,
2046 DB_SHADER_CONTROL = 0x0002880c,
2047 Z_EXPORT_ENABLE_bit = 1 << 0,
2048 STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1,
2049 Z_ORDER_mask = 0x03 << 4,
2050 Z_ORDER_shift = 4,
2051 LATE_Z = 0x00,
2052 EARLY_Z_THEN_LATE_Z = 0x01,
2053 RE_Z = 0x02,
2054 EARLY_Z_THEN_RE_Z = 0x03,
2055 KILL_ENABLE_bit = 1 << 6,
2056 COVERAGE_TO_MASK_ENABLE_bit = 1 << 7,
2057 MASK_EXPORT_ENABLE_bit = 1 << 8,
2058 DUAL_EXPORT_ENABLE_bit = 1 << 9,
2059 EXEC_ON_HIER_FAIL_bit = 1 << 10,
2060 EXEC_ON_NOOP_bit = 1 << 11,
2061 PA_CL_CLIP_CNTL = 0x00028810,
2062 UCP_ENA_0_bit = 1 << 0,
2063 UCP_ENA_1_bit = 1 << 1,
2064 UCP_ENA_2_bit = 1 << 2,
2065 UCP_ENA_3_bit = 1 << 3,
2066 UCP_ENA_4_bit = 1 << 4,
2067 UCP_ENA_5_bit = 1 << 5,
2068 PS_UCP_Y_SCALE_NEG_bit = 1 << 13,
2069 PS_UCP_MODE_mask = 0x03 << 14,
2070 PS_UCP_MODE_shift = 14,
2071 CLIP_DISABLE_bit = 1 << 16,
2072 UCP_CULL_ONLY_ENA_bit = 1 << 17,
2073 BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18,
2074 DX_CLIP_SPACE_DEF_bit = 1 << 19,
2075 DIS_CLIP_ERR_DETECT_bit = 1 << 20,
2076 VTX_KILL_OR_bit = 1 << 21,
2077 DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24,
2078 VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25,
2079 ZCLIP_NEAR_DISABLE_bit = 1 << 26,
2080 ZCLIP_FAR_DISABLE_bit = 1 << 27,
2081 PA_SU_SC_MODE_CNTL = 0x00028814,
2082 CULL_FRONT_bit = 1 << 0,
2083 CULL_BACK_bit = 1 << 1,
2084 FACE_bit = 1 << 2,
2085 POLY_MODE_mask = 0x03 << 3,
2086 POLY_MODE_shift = 3,
2087 X_DISABLE_POLY_MODE = 0x00,
2088 X_DUAL_MODE = 0x01,
2089 POLYMODE_FRONT_PTYPE_mask = 0x07 << 5,
2090 POLYMODE_FRONT_PTYPE_shift = 5,
2091 X_DRAW_POINTS = 0x00,
2092 X_DRAW_LINES = 0x01,
2093 X_DRAW_TRIANGLES = 0x02,
2094 POLYMODE_BACK_PTYPE_mask = 0x07 << 8,
2095 POLYMODE_BACK_PTYPE_shift = 8,
2096 /* X_DRAW_POINTS = 0x00, */
2097 /* X_DRAW_LINES = 0x01, */
2098 /* X_DRAW_TRIANGLES = 0x02, */
2099 POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11,
2100 POLY_OFFSET_BACK_ENABLE_bit = 1 << 12,
2101 POLY_OFFSET_PARA_ENABLE_bit = 1 << 13,
2102 VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16,
2103 PROVOKING_VTX_LAST_bit = 1 << 19,
2104 PERSP_CORR_DIS_bit = 1 << 20,
2105 MULTI_PRIM_IB_ENA_bit = 1 << 21,
2106 PA_CL_VTE_CNTL = 0x00028818,
2107 VPORT_X_SCALE_ENA_bit = 1 << 0,
2108 VPORT_X_OFFSET_ENA_bit = 1 << 1,
2109 VPORT_Y_SCALE_ENA_bit = 1 << 2,
2110 VPORT_Y_OFFSET_ENA_bit = 1 << 3,
2111 VPORT_Z_SCALE_ENA_bit = 1 << 4,
2112 VPORT_Z_OFFSET_ENA_bit = 1 << 5,
2113 VTX_XY_FMT_bit = 1 << 8,
2114 VTX_Z_FMT_bit = 1 << 9,
2115 VTX_W0_FMT_bit = 1 << 10,
2116 PERFCOUNTER_REF_bit = 1 << 11,
2117 PA_CL_VS_OUT_CNTL = 0x0002881c,
2118 CLIP_DIST_ENA_0_bit = 1 << 0,
2119 CLIP_DIST_ENA_1_bit = 1 << 1,
2120 CLIP_DIST_ENA_2_bit = 1 << 2,
2121 CLIP_DIST_ENA_3_bit = 1 << 3,
2122 CLIP_DIST_ENA_4_bit = 1 << 4,
2123 CLIP_DIST_ENA_5_bit = 1 << 5,
2124 CLIP_DIST_ENA_6_bit = 1 << 6,
2125 CLIP_DIST_ENA_7_bit = 1 << 7,
2126 CULL_DIST_ENA_0_bit = 1 << 8,
2127 CULL_DIST_ENA_1_bit = 1 << 9,
2128 CULL_DIST_ENA_2_bit = 1 << 10,
2129 CULL_DIST_ENA_3_bit = 1 << 11,
2130 CULL_DIST_ENA_4_bit = 1 << 12,
2131 CULL_DIST_ENA_5_bit = 1 << 13,
2132 CULL_DIST_ENA_6_bit = 1 << 14,
2133 CULL_DIST_ENA_7_bit = 1 << 15,
2134 USE_VTX_POINT_SIZE_bit = 1 << 16,
2135 USE_VTX_EDGE_FLAG_bit = 1 << 17,
2136 USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18,
2137 USE_VTX_VIEWPORT_INDX_bit = 1 << 19,
2138 USE_VTX_KILL_FLAG_bit = 1 << 20,
2139 VS_OUT_MISC_VEC_ENA_bit = 1 << 21,
2140 VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22,
2141 VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23,
2142 PA_CL_NANINF_CNTL = 0x00028820,
2143 VTE_XY_INF_DISCARD_bit = 1 << 0,
2144 VTE_Z_INF_DISCARD_bit = 1 << 1,
2145 VTE_W_INF_DISCARD_bit = 1 << 2,
2146 VTE_0XNANINF_IS_0_bit = 1 << 3,
2147 VTE_XY_NAN_RETAIN_bit = 1 << 4,
2148 VTE_Z_NAN_RETAIN_bit = 1 << 5,
2149 VTE_W_NAN_RETAIN_bit = 1 << 6,
2150 VTE_W_RECIP_NAN_IS_0_bit = 1 << 7,
2151 VS_XY_NAN_TO_INF_bit = 1 << 8,
2152 VS_XY_INF_RETAIN_bit = 1 << 9,
2153 VS_Z_NAN_TO_INF_bit = 1 << 10,
2154 VS_Z_INF_RETAIN_bit = 1 << 11,
2155 VS_W_NAN_TO_INF_bit = 1 << 12,
2156 VS_W_INF_RETAIN_bit = 1 << 13,
2157 VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14,
2158 VTE_NO_OUTPUT_NEG_0_bit = 1 << 20,
2159 SQ_PGM_START_PS = 0x00028840,
2160 SQ_PGM_RESOURCES_PS = 0x00028850,
2161 NUM_GPRS_mask = 0xff << 0,
2162 NUM_GPRS_shift = 0,
2163 STACK_SIZE_mask = 0xff << 8,
2164 STACK_SIZE_shift = 8,
2165 SQ_PGM_RESOURCES_PS__DX10_CLAMP_bit = 1 << 21,
2166 FETCH_CACHE_LINES_mask = 0x07 << 24,
2167 FETCH_CACHE_LINES_shift = 24,
2168 UNCACHED_FIRST_INST_bit = 1 << 28,
2169 CLAMP_CONSTS_bit = 1 << 31,
2170 SQ_PGM_EXPORTS_PS = 0x00028854,
2171 EXPORT_MODE_mask = 0x1f << 0,
2172 EXPORT_MODE_shift = 0,
2173 SQ_PGM_START_VS = 0x00028858,
2174 SQ_PGM_RESOURCES_VS = 0x00028868,
2175 /* NUM_GPRS_mask = 0xff << 0, */
2176 /* NUM_GPRS_shift = 0, */
2177 /* STACK_SIZE_mask = 0xff << 8, */
2178 /* STACK_SIZE_shift = 8, */
2179 SQ_PGM_RESOURCES_VS__DX10_CLAMP_bit = 1 << 21,
2180 /* FETCH_CACHE_LINES_mask = 0x07 << 24, */
2181 /* FETCH_CACHE_LINES_shift = 24, */
2182 /* UNCACHED_FIRST_INST_bit = 1 << 28, */
2183 SQ_PGM_START_GS = 0x0002886c,
2184 SQ_PGM_RESOURCES_GS = 0x0002887c,
2185 /* NUM_GPRS_mask = 0xff << 0, */
2186 /* NUM_GPRS_shift = 0, */
2187 /* STACK_SIZE_mask = 0xff << 8, */
2188 /* STACK_SIZE_shift = 8, */
2189 SQ_PGM_RESOURCES_GS__DX10_CLAMP_bit = 1 << 21,
2190 /* FETCH_CACHE_LINES_mask = 0x07 << 24, */
2191 /* FETCH_CACHE_LINES_shift = 24, */
2192 /* UNCACHED_FIRST_INST_bit = 1 << 28, */
2193 SQ_PGM_START_ES = 0x00028880,
2194 SQ_PGM_RESOURCES_ES = 0x00028890,
2195 /* NUM_GPRS_mask = 0xff << 0, */
2196 /* NUM_GPRS_shift = 0, */
2197 /* STACK_SIZE_mask = 0xff << 8, */
2198 /* STACK_SIZE_shift = 8, */
2199 SQ_PGM_RESOURCES_ES__DX10_CLAMP_bit = 1 << 21,
2200 /* FETCH_CACHE_LINES_mask = 0x07 << 24, */
2201 /* FETCH_CACHE_LINES_shift = 24, */
2202 /* UNCACHED_FIRST_INST_bit = 1 << 28, */
2203 SQ_PGM_START_FS = 0x00028894,
2204 SQ_PGM_RESOURCES_FS = 0x000288a4,
2205 /* NUM_GPRS_mask = 0xff << 0, */
2206 /* NUM_GPRS_shift = 0, */
2207 /* STACK_SIZE_mask = 0xff << 8, */
2208 /* STACK_SIZE_shift = 8, */
2209 SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit = 1 << 21,
2210 SQ_ESGS_RING_ITEMSIZE = 0x000288a8,
2211 ITEMSIZE_mask = 0x7fff << 0,
2212 ITEMSIZE_shift = 0,
2213 SQ_GSVS_RING_ITEMSIZE = 0x000288ac,
2214 /* ITEMSIZE_mask = 0x7fff << 0, */
2215 /* ITEMSIZE_shift = 0, */
2216 SQ_ESTMP_RING_ITEMSIZE = 0x000288b0,
2217 /* ITEMSIZE_mask = 0x7fff << 0, */
2218 /* ITEMSIZE_shift = 0, */
2219 SQ_GSTMP_RING_ITEMSIZE = 0x000288b4,
2220 /* ITEMSIZE_mask = 0x7fff << 0, */
2221 /* ITEMSIZE_shift = 0, */
2222 SQ_VSTMP_RING_ITEMSIZE = 0x000288b8,
2223 /* ITEMSIZE_mask = 0x7fff << 0, */
2224 /* ITEMSIZE_shift = 0, */
2225 SQ_PSTMP_RING_ITEMSIZE = 0x000288bc,
2226 /* ITEMSIZE_mask = 0x7fff << 0, */
2227 /* ITEMSIZE_shift = 0, */
2228 SQ_FBUF_RING_ITEMSIZE = 0x000288c0,
2229 /* ITEMSIZE_mask = 0x7fff << 0, */
2230 /* ITEMSIZE_shift = 0, */
2231 SQ_REDUC_RING_ITEMSIZE = 0x000288c4,
2232 /* ITEMSIZE_mask = 0x7fff << 0, */
2233 /* ITEMSIZE_shift = 0, */
2234 SQ_GS_VERT_ITEMSIZE = 0x000288c8,
2235 /* ITEMSIZE_mask = 0x7fff << 0, */
2236 /* ITEMSIZE_shift = 0, */
2237 SQ_PGM_CF_OFFSET_PS = 0x000288cc,
2238 PGM_CF_OFFSET_mask = 0xfffff << 0,
2239 PGM_CF_OFFSET_shift = 0,
2240 SQ_PGM_CF_OFFSET_VS = 0x000288d0,
2241 /* PGM_CF_OFFSET_mask = 0xfffff << 0, */
2242 /* PGM_CF_OFFSET_shift = 0, */
2243 SQ_PGM_CF_OFFSET_GS = 0x000288d4,
2244 /* PGM_CF_OFFSET_mask = 0xfffff << 0, */
2245 /* PGM_CF_OFFSET_shift = 0, */
2246 SQ_PGM_CF_OFFSET_ES = 0x000288d8,
2247 /* PGM_CF_OFFSET_mask = 0xfffff << 0, */
2248 /* PGM_CF_OFFSET_shift = 0, */
2249 SQ_PGM_CF_OFFSET_FS = 0x000288dc,
2250 /* PGM_CF_OFFSET_mask = 0xfffff << 0, */
2251 /* PGM_CF_OFFSET_shift = 0, */
2252 SQ_VTX_SEMANTIC_CLEAR = 0x000288e0,
2253 SQ_ALU_CONST_CACHE_PS_0 = 0x00028940,
2254 SQ_ALU_CONST_CACHE_PS_0_num = 16,
2255 SQ_ALU_CONST_CACHE_VS_0 = 0x00028980,
2256 SQ_ALU_CONST_CACHE_VS_0_num = 16,
2257 SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0,
2258 SQ_ALU_CONST_CACHE_GS_0_num = 16,
2259 PA_SU_POINT_SIZE = 0x00028a00,
2260 PA_SU_POINT_SIZE__HEIGHT_mask = 0xffff << 0,
2261 PA_SU_POINT_SIZE__HEIGHT_shift = 0,
2262 PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16,
2263 PA_SU_POINT_SIZE__WIDTH_shift = 16,
2264 PA_SU_POINT_MINMAX = 0x00028a04,
2265 MIN_SIZE_mask = 0xffff << 0,
2266 MIN_SIZE_shift = 0,
2267 MAX_SIZE_mask = 0xffff << 16,
2268 MAX_SIZE_shift = 16,
2269 PA_SU_LINE_CNTL = 0x00028a08,
2270 PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0,
2271 PA_SU_LINE_CNTL__WIDTH_shift = 0,
2272 PA_SC_LINE_STIPPLE = 0x00028a0c,
2273 LINE_PATTERN_mask = 0xffff << 0,
2274 LINE_PATTERN_shift = 0,
2275 REPEAT_COUNT_mask = 0xff << 16,
2276 REPEAT_COUNT_shift = 16,
2277 PATTERN_BIT_ORDER_bit = 1 << 28,
2278 AUTO_RESET_CNTL_mask = 0x03 << 29,
2279 AUTO_RESET_CNTL_shift = 29,
2280 VGT_OUTPUT_PATH_CNTL = 0x00028a10,
2281 PATH_SELECT_mask = 0x03 << 0,
2282 PATH_SELECT_shift = 0,
2283 VGT_OUTPATH_VTX_REUSE = 0x00,
2284 VGT_OUTPATH_TESS_EN = 0x01,
2285 VGT_OUTPATH_PASSTHRU = 0x02,
2286 VGT_OUTPATH_GS_BLOCK = 0x03,
2287 VGT_HOS_CNTL = 0x00028a14,
2288 TESS_MODE_mask = 0x03 << 0,
2289 TESS_MODE_shift = 0,
2290 VGT_HOS_MAX_TESS_LEVEL = 0x00028a18,
2291 VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c,
2292 VGT_HOS_REUSE_DEPTH = 0x00028a20,
2293 REUSE_DEPTH_mask = 0xff << 0,
2294 REUSE_DEPTH_shift = 0,
2295 VGT_GROUP_PRIM_TYPE = 0x00028a24,
2296 VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0,
2297 VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0,
2298 VGT_GRP_3D_POINT = 0x00,
2299 VGT_GRP_3D_LINE = 0x01,
2300 VGT_GRP_3D_TRI = 0x02,
2301 VGT_GRP_3D_RECT = 0x03,
2302 VGT_GRP_3D_QUAD = 0x04,
2303 VGT_GRP_2D_COPY_RECT_V0 = 0x05,
2304 VGT_GRP_2D_COPY_RECT_V1 = 0x06,
2305 VGT_GRP_2D_COPY_RECT_V2 = 0x07,
2306 VGT_GRP_2D_COPY_RECT_V3 = 0x08,
2307 VGT_GRP_2D_FILL_RECT = 0x09,
2308 VGT_GRP_2D_LINE = 0x0a,
2309 VGT_GRP_2D_TRI = 0x0b,
2310 VGT_GRP_PRIM_INDEX_LINE = 0x0c,
2311 VGT_GRP_PRIM_INDEX_TRI = 0x0d,
2312 VGT_GRP_PRIM_INDEX_QUAD = 0x0e,
2313 VGT_GRP_3D_LINE_ADJ = 0x0f,
2314 VGT_GRP_3D_TRI_ADJ = 0x10,
2315 RETAIN_ORDER_bit = 1 << 14,
2316 RETAIN_QUADS_bit = 1 << 15,
2317 PRIM_ORDER_mask = 0x07 << 16,
2318 PRIM_ORDER_shift = 16,
2319 VGT_GRP_LIST = 0x00,
2320 VGT_GRP_STRIP = 0x01,
2321 VGT_GRP_FAN = 0x02,
2322 VGT_GRP_LOOP = 0x03,
2323 VGT_GRP_POLYGON = 0x04,
2324 VGT_GROUP_FIRST_DECR = 0x00028a28,
2325 FIRST_DECR_mask = 0x0f << 0,
2326 FIRST_DECR_shift = 0,
2327 VGT_GROUP_DECR = 0x00028a2c,
2328 DECR_mask = 0x0f << 0,
2329 DECR_shift = 0,
2330 VGT_GROUP_VECT_0_CNTL = 0x00028a30,
2331 COMP_X_EN_bit = 1 << 0,
2332 COMP_Y_EN_bit = 1 << 1,
2333 COMP_Z_EN_bit = 1 << 2,
2334 COMP_W_EN_bit = 1 << 3,
2335 VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8,
2336 VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8,
2337 SHIFT_mask = 0xff << 16,
2338 SHIFT_shift = 16,
2339 VGT_GROUP_VECT_1_CNTL = 0x00028a34,
2340 /* COMP_X_EN_bit = 1 << 0, */
2341 /* COMP_Y_EN_bit = 1 << 1, */
2342 /* COMP_Z_EN_bit = 1 << 2, */
2343 /* COMP_W_EN_bit = 1 << 3, */
2344 VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8,
2345 VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8,
2346 /* SHIFT_mask = 0xff << 16, */
2347 /* SHIFT_shift = 16, */
2348 VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38,
2349 X_CONV_mask = 0x0f << 0,
2350 X_CONV_shift = 0,
2351 VGT_GRP_INDEX_16 = 0x00,
2352 VGT_GRP_INDEX_32 = 0x01,
2353 VGT_GRP_UINT_16 = 0x02,
2354 VGT_GRP_UINT_32 = 0x03,
2355 VGT_GRP_SINT_16 = 0x04,
2356 VGT_GRP_SINT_32 = 0x05,
2357 VGT_GRP_FLOAT_32 = 0x06,
2358 VGT_GRP_AUTO_PRIM = 0x07,
2359 VGT_GRP_FIX_1_23_TO_FLOAT = 0x08,
2360 X_OFFSET_mask = 0x0f << 4,
2361 X_OFFSET_shift = 4,
2362 Y_CONV_mask = 0x0f << 8,
2363 Y_CONV_shift = 8,
2364 /* VGT_GRP_INDEX_16 = 0x00, */
2365 /* VGT_GRP_INDEX_32 = 0x01, */
2366 /* VGT_GRP_UINT_16 = 0x02, */
2367 /* VGT_GRP_UINT_32 = 0x03, */
2368 /* VGT_GRP_SINT_16 = 0x04, */
2369 /* VGT_GRP_SINT_32 = 0x05, */
2370 /* VGT_GRP_FLOAT_32 = 0x06, */
2371 /* VGT_GRP_AUTO_PRIM = 0x07, */
2372 /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
2373 Y_OFFSET_mask = 0x0f << 12,
2374 Y_OFFSET_shift = 12,
2375 Z_CONV_mask = 0x0f << 16,
2376 Z_CONV_shift = 16,
2377 /* VGT_GRP_INDEX_16 = 0x00, */
2378 /* VGT_GRP_INDEX_32 = 0x01, */
2379 /* VGT_GRP_UINT_16 = 0x02, */
2380 /* VGT_GRP_UINT_32 = 0x03, */
2381 /* VGT_GRP_SINT_16 = 0x04, */
2382 /* VGT_GRP_SINT_32 = 0x05, */
2383 /* VGT_GRP_FLOAT_32 = 0x06, */
2384 /* VGT_GRP_AUTO_PRIM = 0x07, */
2385 /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
2386 Z_OFFSET_mask = 0x0f << 20,
2387 Z_OFFSET_shift = 20,
2388 W_CONV_mask = 0x0f << 24,
2389 W_CONV_shift = 24,
2390 /* VGT_GRP_INDEX_16 = 0x00, */
2391 /* VGT_GRP_INDEX_32 = 0x01, */
2392 /* VGT_GRP_UINT_16 = 0x02, */
2393 /* VGT_GRP_UINT_32 = 0x03, */
2394 /* VGT_GRP_SINT_16 = 0x04, */
2395 /* VGT_GRP_SINT_32 = 0x05, */
2396 /* VGT_GRP_FLOAT_32 = 0x06, */
2397 /* VGT_GRP_AUTO_PRIM = 0x07, */
2398 /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
2399 W_OFFSET_mask = 0x0f << 28,
2400 W_OFFSET_shift = 28,
2401 VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c,
2402 /* X_CONV_mask = 0x0f << 0, */
2403 /* X_CONV_shift = 0, */
2404 /* VGT_GRP_INDEX_16 = 0x00, */
2405 /* VGT_GRP_INDEX_32 = 0x01, */
2406 /* VGT_GRP_UINT_16 = 0x02, */
2407 /* VGT_GRP_UINT_32 = 0x03, */
2408 /* VGT_GRP_SINT_16 = 0x04, */
2409 /* VGT_GRP_SINT_32 = 0x05, */
2410 /* VGT_GRP_FLOAT_32 = 0x06, */
2411 /* VGT_GRP_AUTO_PRIM = 0x07, */
2412 /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
2413 /* X_OFFSET_mask = 0x0f << 4, */
2414 /* X_OFFSET_shift = 4, */
2415 /* Y_CONV_mask = 0x0f << 8, */
2416 /* Y_CONV_shift = 8, */
2417 /* VGT_GRP_INDEX_16 = 0x00, */
2418 /* VGT_GRP_INDEX_32 = 0x01, */
2419 /* VGT_GRP_UINT_16 = 0x02, */
2420 /* VGT_GRP_UINT_32 = 0x03, */
2421 /* VGT_GRP_SINT_16 = 0x04, */
2422 /* VGT_GRP_SINT_32 = 0x05, */
2423 /* VGT_GRP_FLOAT_32 = 0x06, */
2424 /* VGT_GRP_AUTO_PRIM = 0x07, */
2425 /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
2426 /* Y_OFFSET_mask = 0x0f << 12, */
2427 /* Y_OFFSET_shift = 12, */
2428 /* Z_CONV_mask = 0x0f << 16, */
2429 /* Z_CONV_shift = 16, */
2430 /* VGT_GRP_INDEX_16 = 0x00, */
2431 /* VGT_GRP_INDEX_32 = 0x01, */
2432 /* VGT_GRP_UINT_16 = 0x02, */
2433 /* VGT_GRP_UINT_32 = 0x03, */
2434 /* VGT_GRP_SINT_16 = 0x04, */
2435 /* VGT_GRP_SINT_32 = 0x05, */
2436 /* VGT_GRP_FLOAT_32 = 0x06, */
2437 /* VGT_GRP_AUTO_PRIM = 0x07, */
2438 /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
2439 /* Z_OFFSET_mask = 0x0f << 20, */
2440 /* Z_OFFSET_shift = 20, */
2441 /* W_CONV_mask = 0x0f << 24, */
2442 /* W_CONV_shift = 24, */
2443 /* VGT_GRP_INDEX_16 = 0x00, */
2444 /* VGT_GRP_INDEX_32 = 0x01, */
2445 /* VGT_GRP_UINT_16 = 0x02, */
2446 /* VGT_GRP_UINT_32 = 0x03, */
2447 /* VGT_GRP_SINT_16 = 0x04, */
2448 /* VGT_GRP_SINT_32 = 0x05, */
2449 /* VGT_GRP_FLOAT_32 = 0x06, */
2450 /* VGT_GRP_AUTO_PRIM = 0x07, */
2451 /* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */
2452 /* W_OFFSET_mask = 0x0f << 28, */
2453 /* W_OFFSET_shift = 28, */
2454 VGT_GS_MODE = 0x00028a40,
2455 MODE_mask = 0x03 << 0,
2456 MODE_shift = 0,
2457 GS_OFF = 0x00,
2458 GS_SCENARIO_A = 0x01,
2459 GS_SCENARIO_B = 0x02,
2460 GS_SCENARIO_G = 0x03,
2461 ES_PASSTHRU_bit = 1 << 2,
2462 CUT_MODE_mask = 0x03 << 3,
2463 CUT_MODE_shift = 3,
2464 GS_CUT_1024 = 0x00,
2465 GS_CUT_512 = 0x01,
2466 GS_CUT_256 = 0x02,
2467 GS_CUT_128 = 0x03,
2468 PA_SC_MPASS_PS_CNTL = 0x00028a48,
2469 MPASS_PIX_VEC_PER_PASS_mask = 0xfffff << 0,
2470 MPASS_PIX_VEC_PER_PASS_shift = 0,
2471 MPASS_PS_ENA_bit = 1 << 31,
2472 PA_SC_MODE_CNTL = 0x00028a4c,
2473 MSAA_ENABLE_bit = 1 << 0,
2474 CLIPRECT_ENABLE_bit = 1 << 1,
2475 LINE_STIPPLE_ENABLE_bit = 1 << 2,
2476 MULTI_CHIP_PRIM_DISCARD_ENAB_bit = 1 << 3,
2477 WALK_ORDER_ENABLE_bit = 1 << 4,
2478 HALVE_DETAIL_SAMPLE_PERF_bit = 1 << 5,
2479 WALK_SIZE_bit = 1 << 6,
2480 WALK_ALIGNMENT_bit = 1 << 7,
2481 WALK_ALIGN8_PRIM_FITS_ST_bit = 1 << 8,
2482 TILE_COVER_NO_SCISSOR_bit = 1 << 9,
2483 KILL_PIX_POST_HI_Z_bit = 1 << 10,
2484 KILL_PIX_POST_DETAIL_MASK_bit = 1 << 11,
2485 MULTI_CHIP_SUPERTILE_ENABLE_bit = 1 << 12,
2486 TILE_COVER_DISABLE_bit = 1 << 13,
2487 FORCE_EOV_CNTDWN_ENABLE_bit = 1 << 14,
2488 FORCE_EOV_TILE_ENABLE_bit = 1 << 15,
2489 FORCE_EOV_REZ_ENABLE_bit = 1 << 16,
2490 PS_ITER_SAMPLE_bit = 1 << 17,
2491 VGT_ENHANCE = 0x00028a50,
2492 VGT_ENHANCE__MI_TIMESTAMP_RES_mask = 0x03 << 0,
2493 VGT_ENHANCE__MI_TIMESTAMP_RES_shift = 0,
2494 X_0_992_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_32 = 0x00,
2495 X_0_496_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_16 = 0x01,
2496 X_0_248_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_8 = 0x02,
2497 X_0_124_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_4 = 0x03,
2498 MISC_mask = 0x3fffffff << 2,
2499 MISC_shift = 2,
2500 VGT_GS_OUT_PRIM_TYPE = 0x00028a6c,
2501 OUTPRIM_TYPE_mask = 0x3f << 0,
2502 OUTPRIM_TYPE_shift = 0,
2503 POINTLIST = 0x00,
2504 LINESTRIP = 0x01,
2505 TRISTRIP = 0x02,
2506 VGT_DMA_SIZE = 0x00028a74,
2507 VGT_DMA_INDEX_TYPE = 0x00028a7c,
2508 /* INDEX_TYPE_mask = 0x03 << 0, */
2509 /* INDEX_TYPE_shift = 0, */
2510 VGT_INDEX_16 = 0x00,
2511 VGT_INDEX_32 = 0x01,
2512 SWAP_MODE_mask = 0x03 << 2,
2513 SWAP_MODE_shift = 2,
2514 VGT_DMA_SWAP_NONE = 0x00,
2515 VGT_DMA_SWAP_16_BIT = 0x01,
2516 VGT_DMA_SWAP_32_BIT = 0x02,
2517 VGT_DMA_SWAP_WORD = 0x03,
2518 VGT_PRIMITIVEID_EN = 0x00028a84,
2519 PRIMITIVEID_EN_bit = 1 << 0,
2520 VGT_DMA_NUM_INSTANCES = 0x00028a88,
2521 VGT_EVENT_INITIATOR = 0x00028a90,
2522 EVENT_TYPE_mask = 0x3f << 0,
2523 EVENT_TYPE_shift = 0,
2524 CACHE_FLUSH_TS = 0x04,
2525 CONTEXT_DONE = 0x05,
2526 CACHE_FLUSH = 0x06,
2527 VIZQUERY_START = 0x07,
2528 VIZQUERY_END = 0x08,
2529 SC_WAIT_WC = 0x09,
2530 MPASS_PS_CP_REFETCH = 0x0a,
2531 MPASS_PS_RST_START = 0x0b,
2532 MPASS_PS_INCR_START = 0x0c,
2533 RST_PIX_CNT = 0x0d,
2534 RST_VTX_CNT = 0x0e,
2535 VS_PARTIAL_FLUSH = 0x0f,
2536 PS_PARTIAL_FLUSH = 0x10,
2537 CACHE_FLUSH_AND_INV_TS_EVENT = 0x14,
2538 ZPASS_DONE = 0x15,
2539 CACHE_FLUSH_AND_INV_EVENT = 0x16,
2540 PERFCOUNTER_START = 0x17,
2541 PERFCOUNTER_STOP = 0x18,
2542 PIPELINESTAT_START = 0x19,
2543 PIPELINESTAT_STOP = 0x1a,
2544 PERFCOUNTER_SAMPLE = 0x1b,
2545 FLUSH_ES_OUTPUT = 0x1c,
2546 FLUSH_GS_OUTPUT = 0x1d,
2547 SAMPLE_PIPELINESTAT = 0x1e,
2548 SO_VGTSTREAMOUT_FLUSH = 0x1f,
2549 SAMPLE_STREAMOUTSTATS = 0x20,
2550 RESET_VTX_CNT = 0x21,
2551 BLOCK_CONTEXT_DONE = 0x22,
2552 CR_CONTEXT_DONE = 0x23,
2553 VGT_FLUSH = 0x24,
2554 CR_DONE_TS = 0x25,
2555 SQ_NON_EVENT = 0x26,
2556 SC_SEND_DB_VPZ = 0x27,
2557 BOTTOM_OF_PIPE_TS = 0x28,
2558 DB_CACHE_FLUSH_AND_INV = 0x2a,
2559 ADDRESS_HI_mask = 0xff << 19,
2560 ADDRESS_HI_shift = 19,
2561 EXTENDED_EVENT_bit = 1 << 27,
2562 VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94,
2563 RESET_EN_bit = 1 << 0,
2564 VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0,
2565 VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4,
2566 VGT_STRMOUT_EN = 0x00028ab0,
2567 STREAMOUT_bit = 1 << 0,
2568 VGT_REUSE_OFF = 0x00028ab4,
2569 REUSE_OFF_bit = 1 << 0,
2570 VGT_VTX_CNT_EN = 0x00028ab8,
2571 VTX_CNT_EN_bit = 1 << 0,
2572 VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0,
2573 VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4,
2574 VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0,
2575 VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0,
2576 VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8,
2577 VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc,
2578 VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0,
2579 VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4,
2580 VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0,
2581 VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0,
2582 VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8,
2583 VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec,
2584 VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0,
2585 VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4,
2586 VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0,
2587 VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0,
2588 VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8,
2589 VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc,
2590 VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00,
2591 VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04,
2592 VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0,
2593 VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0,
2594 VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08,
2595 VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c,
2596 VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10,
2597 VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14,
2598 VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18,
2599 VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c,
2600 VGT_STRMOUT_BUFFER_EN = 0x00028b20,
2601 BUFFER_0_EN_bit = 1 << 0,
2602 BUFFER_1_EN_bit = 1 << 1,
2603 BUFFER_2_EN_bit = 1 << 2,
2604 BUFFER_3_EN_bit = 1 << 3,
2605 VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28,
2606 VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c,
2607 VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30,
2608 VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44,
2609 VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0,
2610 VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0,
2611 VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48,
2612 VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0,
2613 VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0,
2614 VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c,
2615 VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0,
2616 VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0,
2617 VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50,
2618 VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0,
2619 VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0,
2620 PA_SC_LINE_CNTL = 0x00028c00,
2621 BRES_CNTL_mask = 0xff << 0,
2622 BRES_CNTL_shift = 0,
2623 USE_BRES_CNTL_bit = 1 << 8,
2624 EXPAND_LINE_WIDTH_bit = 1 << 9,
2625 LAST_PIXEL_bit = 1 << 10,
2626 PA_SC_AA_CONFIG = 0x00028c04,
2627 MSAA_NUM_SAMPLES_mask = 0x03 << 0,
2628 MSAA_NUM_SAMPLES_shift = 0,
2629 AA_MASK_CENTROID_DTMN_bit = 1 << 4,
2630 MAX_SAMPLE_DIST_mask = 0x0f << 13,
2631 MAX_SAMPLE_DIST_shift = 13,
2632 PA_SU_VTX_CNTL = 0x00028c08,
2633 PIX_CENTER_bit = 1 << 0,
2634 PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1,
2635 PA_SU_VTX_CNTL__ROUND_MODE_shift = 1,
2636 X_TRUNCATE = 0x00,
2637 X_ROUND = 0x01,
2638 X_ROUND_TO_EVEN = 0x02,
2639 X_ROUND_TO_ODD = 0x03,
2640 QUANT_MODE_mask = 0x07 << 3,
2641 QUANT_MODE_shift = 3,
2642 X_1_16TH = 0x00,
2643 X_1_8TH = 0x01,
2644 X_1_4TH = 0x02,
2645 X_1_2 = 0x03,
2646 X_1 = 0x04,
2647 X_1_256TH = 0x05,
2648 PA_CL_GB_VERT_CLIP_ADJ = 0x00028c0c,
2649 PA_CL_GB_VERT_DISC_ADJ = 0x00028c10,
2650 PA_CL_GB_HORZ_CLIP_ADJ = 0x00028c14,
2651 PA_CL_GB_HORZ_DISC_ADJ = 0x00028c18,
2652 PA_SC_AA_SAMPLE_LOCS_MCTX = 0x00028c1c,
2653 /* S0_X_mask = 0x0f << 0, */
2654 /* S0_X_shift = 0, */
2655 /* S0_Y_mask = 0x0f << 4, */
2656 /* S0_Y_shift = 4, */
2657 /* S1_X_mask = 0x0f << 8, */
2658 /* S1_X_shift = 8, */
2659 /* S1_Y_mask = 0x0f << 12, */
2660 /* S1_Y_shift = 12, */
2661 /* S2_X_mask = 0x0f << 16, */
2662 /* S2_X_shift = 16, */
2663 /* S2_Y_mask = 0x0f << 20, */
2664 /* S2_Y_shift = 20, */
2665 /* S3_X_mask = 0x0f << 24, */
2666 /* S3_X_shift = 24, */
2667 /* S3_Y_mask = 0x0f << 28, */
2668 /* S3_Y_shift = 28, */
2669 PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX = 0x00028c20,
2670 /* S4_X_mask = 0x0f << 0, */
2671 /* S4_X_shift = 0, */
2672 /* S4_Y_mask = 0x0f << 4, */
2673 /* S4_Y_shift = 4, */
2674 /* S5_X_mask = 0x0f << 8, */
2675 /* S5_X_shift = 8, */
2676 /* S5_Y_mask = 0x0f << 12, */
2677 /* S5_Y_shift = 12, */
2678 /* S6_X_mask = 0x0f << 16, */
2679 /* S6_X_shift = 16, */
2680 /* S6_Y_mask = 0x0f << 20, */
2681 /* S6_Y_shift = 20, */
2682 /* S7_X_mask = 0x0f << 24, */
2683 /* S7_X_shift = 24, */
2684 /* S7_Y_mask = 0x0f << 28, */
2685 /* S7_Y_shift = 28, */
2686 CB_CLRCMP_CONTROL = 0x00028c30,
2687 CLRCMP_FCN_SRC_mask = 0x07 << 0,
2688 CLRCMP_FCN_SRC_shift = 0,
2689 CLRCMP_DRAW_ALWAYS = 0x00,
2690 CLRCMP_DRAW_NEVER = 0x01,
2691 CLRCMP_DRAW_ON_NEQ = 0x04,
2692 CLRCMP_DRAW_ON_EQ = 0x05,
2693 CLRCMP_FCN_DST_mask = 0x07 << 8,
2694 CLRCMP_FCN_DST_shift = 8,
2695 /* CLRCMP_DRAW_ALWAYS = 0x00, */
2696 /* CLRCMP_DRAW_NEVER = 0x01, */
2697 /* CLRCMP_DRAW_ON_NEQ = 0x04, */
2698 /* CLRCMP_DRAW_ON_EQ = 0x05, */
2699 CLRCMP_FCN_SEL_mask = 0x03 << 24,
2700 CLRCMP_FCN_SEL_shift = 24,
2701 CLRCMP_SEL_DST = 0x00,
2702 CLRCMP_SEL_SRC = 0x01,
2703 CLRCMP_SEL_AND = 0x02,
2704 CB_CLRCMP_SRC = 0x00028c34,
2705 CB_CLRCMP_DST = 0x00028c38,
2706 CB_CLRCMP_MSK = 0x00028c3c,
2707 PA_SC_AA_MASK = 0x00028c48,
2708 VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58,
2709 VTX_REUSE_DEPTH_mask = 0xff << 0,
2710 VTX_REUSE_DEPTH_shift = 0,
2711 VGT_OUT_DEALLOC_CNTL = 0x00028c5c,
2712 DEALLOC_DIST_mask = 0x7f << 0,
2713 DEALLOC_DIST_shift = 0,
2714 DB_RENDER_CONTROL = 0x00028d0c,
2715 DEPTH_CLEAR_ENABLE_bit = 1 << 0,
2716 STENCIL_CLEAR_ENABLE_bit = 1 << 1,
2717 DEPTH_COPY_bit = 1 << 2,
2718 STENCIL_COPY_bit = 1 << 3,
2719 RESUMMARIZE_ENABLE_bit = 1 << 4,
2720 STENCIL_COMPRESS_DISABLE_bit = 1 << 5,
2721 DEPTH_COMPRESS_DISABLE_bit = 1 << 6,
2722 COPY_CENTROID_bit = 1 << 7,
2723 COPY_SAMPLE_mask = 0x07 << 8,
2724 COPY_SAMPLE_shift = 8,
2725 ZPASS_INCREMENT_DISABLE_bit = 1 << 11,
2726 DB_RENDER_OVERRIDE = 0x00028d10,
2727 FORCE_HIZ_ENABLE_mask = 0x03 << 0,
2728 FORCE_HIZ_ENABLE_shift = 0,
2729 FORCE_OFF = 0x00,
2730 FORCE_ENABLE = 0x01,
2731 FORCE_DISABLE = 0x02,
2732 FORCE_RESERVED = 0x03,
2733 FORCE_HIS_ENABLE0_mask = 0x03 << 2,
2734 FORCE_HIS_ENABLE0_shift = 2,
2735 /* FORCE_OFF = 0x00, */
2736 /* FORCE_ENABLE = 0x01, */
2737 /* FORCE_DISABLE = 0x02, */
2738 /* FORCE_RESERVED = 0x03, */
2739 FORCE_HIS_ENABLE1_mask = 0x03 << 4,
2740 FORCE_HIS_ENABLE1_shift = 4,
2741 /* FORCE_OFF = 0x00, */
2742 /* FORCE_ENABLE = 0x01, */
2743 /* FORCE_DISABLE = 0x02, */
2744 /* FORCE_RESERVED = 0x03, */
2745 FORCE_SHADER_Z_ORDER_bit = 1 << 6,
2746 FAST_Z_DISABLE_bit = 1 << 7,
2747 FAST_STENCIL_DISABLE_bit = 1 << 8,
2748 NOOP_CULL_DISABLE_bit = 1 << 9,
2749 FORCE_COLOR_KILL_bit = 1 << 10,
2750 FORCE_Z_READ_bit = 1 << 11,
2751 FORCE_STENCIL_READ_bit = 1 << 12,
2752 FORCE_FULL_Z_RANGE_mask = 0x03 << 13,
2753 FORCE_FULL_Z_RANGE_shift = 13,
2754 /* FORCE_OFF = 0x00, */
2755 /* FORCE_ENABLE = 0x01, */
2756 /* FORCE_DISABLE = 0x02, */
2757 /* FORCE_RESERVED = 0x03, */
2758 FORCE_QC_SMASK_CONFLICT_bit = 1 << 15,
2759 DISABLE_VIEWPORT_CLAMP_bit = 1 << 16,
2760 IGNORE_SC_ZRANGE_bit = 1 << 17,
2761 DB_HTILE_SURFACE = 0x00028d24,
2762 HTILE_WIDTH_bit = 1 << 0,
2763 HTILE_HEIGHT_bit = 1 << 1,
2764 LINEAR_bit = 1 << 2,
2765 FULL_CACHE_bit = 1 << 3,
2766 HTILE_USES_PRELOAD_WIN_bit = 1 << 4,
2767 PRELOAD_bit = 1 << 5,
2768 PREFETCH_WIDTH_mask = 0x3f << 6,
2769 PREFETCH_WIDTH_shift = 6,
2770 PREFETCH_HEIGHT_mask = 0x3f << 12,
2771 PREFETCH_HEIGHT_shift = 12,
2772 DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c,
2773 COMPAREFUNC1_mask = 0x07 << 0,
2774 COMPAREFUNC1_shift = 0,
2775 /* REF_NEVER = 0x00, */
2776 /* REF_LESS = 0x01, */
2777 /* REF_EQUAL = 0x02, */
2778 /* REF_LEQUAL = 0x03, */
2779 /* REF_GREATER = 0x04, */
2780 /* REF_NOTEQUAL = 0x05, */
2781 /* REF_GEQUAL = 0x06, */
2782 /* REF_ALWAYS = 0x07, */
2783 COMPAREVALUE1_mask = 0xff << 4,
2784 COMPAREVALUE1_shift = 4,
2785 COMPAREMASK1_mask = 0xff << 12,
2786 COMPAREMASK1_shift = 12,
2787 ENABLE1_bit = 1 << 24,
2788 DB_PRELOAD_CONTROL = 0x00028d30,
2789 START_X_mask = 0xff << 0,
2790 START_X_shift = 0,
2791 START_Y_mask = 0xff << 8,
2792 START_Y_shift = 8,
2793 MAX_X_mask = 0xff << 16,
2794 MAX_X_shift = 16,
2795 MAX_Y_mask = 0xff << 24,
2796 MAX_Y_shift = 24,
2797 DB_PREFETCH_LIMIT = 0x00028d34,
2798 DEPTH_HEIGHT_TILE_MAX_mask = 0x3ff << 0,
2799 DEPTH_HEIGHT_TILE_MAX_shift = 0,
2800 PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028df8,
2801 POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0,
2802 POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0,
2803 POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8,
2804 PA_SU_POLY_OFFSET_CLAMP = 0x00028dfc,
2805 PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028e00,
2806 PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028e04,
2807 PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028e08,
2808 PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028e0c,
2809 PA_CL_POINT_X_RAD = 0x00028e10,
2810 PA_CL_POINT_Y_RAD = 0x00028e14,
2811 PA_CL_POINT_SIZE = 0x00028e18,
2812 PA_CL_POINT_CULL_RAD = 0x00028e1c,
2813 PA_CL_UCP_0_X = 0x00028e20,
2814 PA_CL_UCP_0_X_num = 6,
2815 PA_CL_UCP_0_X_offset = 16,
2816 PA_CL_UCP_0_Y = 0x00028e24,
2817 PA_CL_UCP_0_Y_num = 6,
2818 PA_CL_UCP_0_Y_offset = 16,
2819 PA_CL_UCP_0_Z = 0x00028e28,
2820 PA_CL_UCP_0_Z_num = 6,
2821 PA_CL_UCP_0_Z_offset = 16,
2822 SQ_ALU_CONSTANT0_0 = 0x00030000,
2823 SQ_ALU_CONSTANT1_0 = 0x00030004,
2824 SQ_ALU_CONSTANT2_0 = 0x00030008,
2825 SQ_ALU_CONSTANT3_0 = 0x0003000c,
2826 SQ_VTX_CONSTANT_WORD0_0 = 0x00038000,
2827 SQ_TEX_RESOURCE_WORD0_0 = 0x00038000,
2828 DIM_mask = 0x07 << 0,
2829 DIM_shift = 0,
2830 SQ_TEX_DIM_1D = 0x00,
2831 SQ_TEX_DIM_2D = 0x01,
2832 SQ_TEX_DIM_3D = 0x02,
2833 SQ_TEX_DIM_CUBEMAP = 0x03,
2834 SQ_TEX_DIM_1D_ARRAY = 0x04,
2835 SQ_TEX_DIM_2D_ARRAY = 0x05,
2836 SQ_TEX_DIM_2D_MSAA = 0x06,
2837 SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07,
2838 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask = 0x0f << 3,
2839 SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift = 3,
2840 TILE_TYPE_bit = 1 << 7,
2841 PITCH_mask = 0x7ff << 8,
2842 PITCH_shift = 8,
2843 TEX_WIDTH_mask = 0x1fff << 19,
2844 TEX_WIDTH_shift = 19,
2845 SQ_VTX_CONSTANT_WORD1_0 = 0x00038004,
2846 SQ_TEX_RESOURCE_WORD1_0 = 0x00038004,
2847 TEX_HEIGHT_mask = 0x1fff << 0,
2848 TEX_HEIGHT_shift = 0,
2849 TEX_DEPTH_mask = 0x1fff << 13,
2850 TEX_DEPTH_shift = 13,
2851 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask = 0x3f << 26,
2852 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift = 26,
2853 SQ_VTX_CONSTANT_WORD2_0 = 0x00038008,
2854 BASE_ADDRESS_HI_mask = 0xff << 0,
2855 BASE_ADDRESS_HI_shift = 0,
2856 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0x7ff << 8,
2857 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8,
2858 SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit = 1 << 19,
2859 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20,
2860 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20,
2861 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26,
2862 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26,
2863 /* SQ_NUM_FORMAT_NORM = 0x00, */
2864 /* SQ_NUM_FORMAT_INT = 0x01, */
2865 /* SQ_NUM_FORMAT_SCALED = 0x02, */
2866 SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28,
2867 SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29,
2868 SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30,
2869 SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30,
2870 /* SQ_ENDIAN_NONE = 0x00, */
2871 /* SQ_ENDIAN_8IN16 = 0x01, */
2872 /* SQ_ENDIAN_8IN32 = 0x02, */
2873 SQ_TEX_RESOURCE_WORD2_0 = 0x00038008,
2874 SQ_VTX_CONSTANT_WORD3_0 = 0x0003800c,
2875 MEM_REQUEST_SIZE_mask = 0x03 << 0,
2876 MEM_REQUEST_SIZE_shift = 0,
2877 SQ_TEX_RESOURCE_WORD3_0 = 0x0003800c,
2878 SQ_TEX_RESOURCE_WORD4_0 = 0x00038010,
2879 FORMAT_COMP_X_mask = 0x03 << 0,
2880 FORMAT_COMP_X_shift = 0,
2881 SQ_FORMAT_COMP_UNSIGNED = 0x00,
2882 SQ_FORMAT_COMP_SIGNED = 0x01,
2883 SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02,
2884 FORMAT_COMP_Y_mask = 0x03 << 2,
2885 FORMAT_COMP_Y_shift = 2,
2886 /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
2887 /* SQ_FORMAT_COMP_SIGNED = 0x01, */
2888 /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
2889 FORMAT_COMP_Z_mask = 0x03 << 4,
2890 FORMAT_COMP_Z_shift = 4,
2891 /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
2892 /* SQ_FORMAT_COMP_SIGNED = 0x01, */
2893 /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
2894 FORMAT_COMP_W_mask = 0x03 << 6,
2895 FORMAT_COMP_W_shift = 6,
2896 /* SQ_FORMAT_COMP_UNSIGNED = 0x00, */
2897 /* SQ_FORMAT_COMP_SIGNED = 0x01, */
2898 /* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */
2899 SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8,
2900 SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8,
2901 /* SQ_NUM_FORMAT_NORM = 0x00, */
2902 /* SQ_NUM_FORMAT_INT = 0x01, */
2903 /* SQ_NUM_FORMAT_SCALED = 0x02, */
2904 SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10,
2905 SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11,
2906 SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12,
2907 SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12,
2908 /* SQ_ENDIAN_NONE = 0x00, */
2909 /* SQ_ENDIAN_8IN16 = 0x01, */
2910 /* SQ_ENDIAN_8IN32 = 0x02, */
2911 REQUEST_SIZE_mask = 0x03 << 14,
2912 REQUEST_SIZE_shift = 14,
2913 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16,
2914 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16,
2915 /* SQ_SEL_X = 0x00, */
2916 /* SQ_SEL_Y = 0x01, */
2917 /* SQ_SEL_Z = 0x02, */
2918 /* SQ_SEL_W = 0x03, */
2919 /* SQ_SEL_0 = 0x04, */
2920 /* SQ_SEL_1 = 0x05, */
2921 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19,
2922 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19,
2923 /* SQ_SEL_X = 0x00, */
2924 /* SQ_SEL_Y = 0x01, */
2925 /* SQ_SEL_Z = 0x02, */
2926 /* SQ_SEL_W = 0x03, */
2927 /* SQ_SEL_0 = 0x04, */
2928 /* SQ_SEL_1 = 0x05, */
2929 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22,
2930 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22,
2931 /* SQ_SEL_X = 0x00, */
2932 /* SQ_SEL_Y = 0x01, */
2933 /* SQ_SEL_Z = 0x02, */
2934 /* SQ_SEL_W = 0x03, */
2935 /* SQ_SEL_0 = 0x04, */
2936 /* SQ_SEL_1 = 0x05, */
2937 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25,
2938 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25,
2939 /* SQ_SEL_X = 0x00, */
2940 /* SQ_SEL_Y = 0x01, */
2941 /* SQ_SEL_Z = 0x02, */
2942 /* SQ_SEL_W = 0x03, */
2943 /* SQ_SEL_0 = 0x04, */
2944 /* SQ_SEL_1 = 0x05, */
2945 BASE_LEVEL_mask = 0x0f << 28,
2946 BASE_LEVEL_shift = 28,
2947 SQ_TEX_RESOURCE_WORD5_0 = 0x00038014,
2948 LAST_LEVEL_mask = 0x0f << 0,
2949 LAST_LEVEL_shift = 0,
2950 BASE_ARRAY_mask = 0x1fff << 4,
2951 BASE_ARRAY_shift = 4,
2952 LAST_ARRAY_mask = 0x1fff << 17,
2953 LAST_ARRAY_shift = 17,
2954 SQ_TEX_RESOURCE_WORD6_0 = 0x00038018,
2955 MPEG_CLAMP_mask = 0x03 << 0,
2956 MPEG_CLAMP_shift = 0,
2957 SQ_TEX_MPEG_CLAMP_OFF = 0x00,
2958 SQ_TEX_MPEG_9 = 0x01,
2959 SQ_TEX_MPEG_10 = 0x02,
2960 PERF_MODULATION_mask = 0x07 << 5,
2961 PERF_MODULATION_shift = 5,
2962 INTERLACED_bit = 1 << 8,
2963 SQ_TEX_RESOURCE_WORD6_0__TYPE_mask = 0x03 << 30,
2964 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift = 30,
2965 SQ_TEX_VTX_INVALID_TEXTURE = 0x00,
2966 SQ_TEX_VTX_INVALID_BUFFER = 0x01,
2967 SQ_TEX_VTX_VALID_TEXTURE = 0x02,
2968 SQ_TEX_VTX_VALID_BUFFER = 0x03,
2969 SQ_VTX_CONSTANT_WORD6_0 = 0x00038018,
2970 SQ_VTX_CONSTANT_WORD6_0__TYPE_mask = 0x03 << 30,
2971 SQ_VTX_CONSTANT_WORD6_0__TYPE_shift = 30,
2972 /* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */
2973 /* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */
2974 /* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */
2975 /* SQ_TEX_VTX_VALID_BUFFER = 0x03, */
2976 SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000,
2977 SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x07 << 0,
2978 SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0,
2979 SQ_TEX_WRAP = 0x00,
2980 SQ_TEX_MIRROR = 0x01,
2981 SQ_TEX_CLAMP_LAST_TEXEL = 0x02,
2982 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03,
2983 SQ_TEX_CLAMP_HALF_BORDER = 0x04,
2984 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05,
2985 SQ_TEX_CLAMP_BORDER = 0x06,
2986 SQ_TEX_MIRROR_ONCE_BORDER = 0x07,
2987 CLAMP_Y_mask = 0x07 << 3,
2988 CLAMP_Y_shift = 3,
2989 /* SQ_TEX_WRAP = 0x00, */
2990 /* SQ_TEX_MIRROR = 0x01, */
2991 /* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */
2992 /* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */
2993 /* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */
2994 /* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */
2995 /* SQ_TEX_CLAMP_BORDER = 0x06, */
2996 /* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */
2997 CLAMP_Z_mask = 0x07 << 6,
2998 CLAMP_Z_shift = 6,
2999 /* SQ_TEX_WRAP = 0x00, */
3000 /* SQ_TEX_MIRROR = 0x01, */
3001 /* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */
3002 /* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */
3003 /* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */
3004 /* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */
3005 /* SQ_TEX_CLAMP_BORDER = 0x06, */
3006 /* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */
3007 XY_MAG_FILTER_mask = 0x07 << 9,
3008 XY_MAG_FILTER_shift = 9,
3009 SQ_TEX_XY_FILTER_POINT = 0x00,
3010 SQ_TEX_XY_FILTER_BILINEAR = 0x01,
3011 SQ_TEX_XY_FILTER_BICUBIC = 0x02,
3012 XY_MIN_FILTER_mask = 0x07 << 12,
3013 XY_MIN_FILTER_shift = 12,
3014 /* SQ_TEX_XY_FILTER_POINT = 0x00, */
3015 /* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */
3016 /* SQ_TEX_XY_FILTER_BICUBIC = 0x02, */
3017 Z_FILTER_mask = 0x03 << 15,
3018 Z_FILTER_shift = 15,
3019 SQ_TEX_Z_FILTER_NONE = 0x00,
3020 SQ_TEX_Z_FILTER_POINT = 0x01,
3021 SQ_TEX_Z_FILTER_LINEAR = 0x02,
3022 MIP_FILTER_mask = 0x03 << 17,
3023 MIP_FILTER_shift = 17,
3024 /* SQ_TEX_Z_FILTER_NONE = 0x00, */
3025 /* SQ_TEX_Z_FILTER_POINT = 0x01, */
3026 /* SQ_TEX_Z_FILTER_LINEAR = 0x02, */
3027 BORDER_COLOR_TYPE_mask = 0x03 << 22,
3028 BORDER_COLOR_TYPE_shift = 22,
3029 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00,
3030 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01,
3031 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02,
3032 SQ_TEX_BORDER_COLOR_REGISTER = 0x03,
3033 POINT_SAMPLING_CLAMP_bit = 1 << 24,
3034 TEX_ARRAY_OVERRIDE_bit = 1 << 25,
3035 DEPTH_COMPARE_FUNCTION_mask = 0x07 << 26,
3036 DEPTH_COMPARE_FUNCTION_shift = 26,
3037 SQ_TEX_DEPTH_COMPARE_NEVER = 0x00,
3038 SQ_TEX_DEPTH_COMPARE_LESS = 0x01,
3039 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02,
3040 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03,
3041 SQ_TEX_DEPTH_COMPARE_GREATER = 0x04,
3042 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05,
3043 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06,
3044 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07,
3045 CHROMA_KEY_mask = 0x03 << 29,
3046 CHROMA_KEY_shift = 29,
3047 SQ_TEX_CHROMA_KEY_DISABLED = 0x00,
3048 SQ_TEX_CHROMA_KEY_KILL = 0x01,
3049 SQ_TEX_CHROMA_KEY_BLEND = 0x02,
3050 LOD_USES_MINOR_AXIS_bit = 1 << 31,
3051 SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004,
3052 MIN_LOD_mask = 0x3ff << 0,
3053 MIN_LOD_shift = 0,
3054 MAX_LOD_mask = 0x3ff << 10,
3055 MAX_LOD_shift = 10,
3056 SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_mask = 0xfff << 20,
3057 SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS_shift = 20,
3058 SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008,
3059 LOD_BIAS_SEC_mask = 0xfff << 0,
3060 LOD_BIAS_SEC_shift = 0,
3061 MC_COORD_TRUNCATE_bit = 1 << 12,
3062 SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 13,
3063 HIGH_PRECISION_FILTER_bit = 1 << 14,
3064 PERF_MIP_mask = 0x07 << 15,
3065 PERF_MIP_shift = 15,
3066 PERF_Z_mask = 0x03 << 18,
3067 PERF_Z_shift = 18,
3068 FETCH_4_bit = 1 << 26,
3069 SAMPLE_IS_PCF_bit = 1 << 27,
3070 SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31,
3071 SQ_VTX_BASE_VTX_LOC = 0x0003cff0,
3072 SQ_VTX_START_INST_LOC = 0x0003cff4,
3073 SQ_LOOP_CONST_DX10_0 = 0x0003e200,
3074 SQ_LOOP_CONST_0 = 0x0003e200,
3075 SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0,
3076 SQ_LOOP_CONST_0__COUNT_shift = 0,
3077 INIT_mask = 0xfff << 12,
3078 INIT_shift = 12,
3079 INC_mask = 0xff << 24,
3080 INC_shift = 24,
3081 SQ_BOOL_CONST_0 = 0x0003e380,
3082 SQ_BOOL_CONST_0_num = 3,
3083
3084 } ;
3085
3086 #endif /* _AUTOREGS */
3087