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Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
[mesa.git] / src / mesa / drivers / dri / r600 / r600_reg_r7xx.h
1 /*
2 * RadeonHD R6xx, R7xx Register documentation
3 *
4 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008-2009 Matthias Hopf
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef _R600_REG_R7xx_H_
26 #define _R600_REG_R7xx_H_
27
28 /*
29 * Register update for R7xx chips
30 */
31
32 enum {
33
34 R7XX_MC_VM_FB_LOCATION = 0x00002024,
35
36 // GRBM_STATUS = 0x00008010,
37 R7XX_TA_BUSY_bit = 1 << 14,
38
39 R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c,
40 RING0_OFFSET_mask = 0xff << 0,
41 RING0_OFFSET_shift = 0,
42 ISOLATE_ES_ENABLE_bit = 1 << 12,
43 ISOLATE_GS_ENABLE_bit = 1 << 13,
44 VS_PC_LIMIT_ENABLE_bit = 1 << 14,
45
46 // SQ_ALU_WORD0 = 0x00008dfc,
47 // SRC0_SEL_mask = 0x1ff << 0,
48 // SRC1_SEL_mask = 0x1ff << 13,
49 R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
50 R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
51 R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
52 R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
53 // INDEX_MODE_mask = 0x07 << 26,
54 R7xx_SQ_INDEX_GLOBAL = 0x05,
55 R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06,
56 R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc,
57 R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
58 R6xx_FOG_MERGE_bit = 1 << 5,
59 R6xx_OMOD_mask = 0x03 << 6,
60 R7xx_OMOD_mask = 0x03 << 5,
61 R6xx_OMOD_shift = 6,
62 R7xx_OMOD_shift = 5,
63 R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
64 R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
65 R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
66 R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
67 R7xx_SQ_OP2_INST_FREXP_64 = 0x07,
68 R7xx_SQ_OP2_INST_ADD_64 = 0x17,
69 R7xx_SQ_OP2_INST_MUL_64 = 0x1b,
70 R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c,
71 R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d,
72 R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a,
73 R7xx_SQ_OP2_INST_FRACT_64 = 0x7b,
74 R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c,
75 R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d,
76 R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e,
77 // SQ_ALU_WORD1_OP3 = 0x00008dfc,
78 // SRC2_SEL_mask = 0x1ff << 0,
79 // R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
80 // R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
81 // R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
82 // R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
83 // SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13,
84 R7xx_SQ_OP3_INST_MULADD_64 = 0x08,
85 R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09,
86 R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a,
87 R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b,
88 // SQ_CF_ALU_WORD1 = 0x00008dfc,
89 R6xx_USES_WATERFALL_bit = 1 << 25,
90 R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
91 // SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc,
92 // ARRAY_BASE_mask = 0x1fff << 0,
93 // TYPE_mask = 0x03 << 13,
94 // SQ_EXPORT_PARAM = 0x02,
95 // X_UNUSED_FOR_SX_EXPORTS = 0x03,
96 // ELEM_SIZE_mask = 0x03 << 30,
97 // SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc,
98 // SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23,
99 R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a,
100 // SQ_CF_WORD1 = 0x00008dfc,
101 // SQ_CF_WORD1__COUNT_mask = 0x07 << 10,
102 R7xx_COUNT_3_bit = 1 << 19,
103 // SQ_CF_WORD1__CF_INST_mask = 0x7f << 23,
104 R7xx_SQ_CF_INST_END_PROGRAM = 0x19,
105 R7xx_SQ_CF_INST_WAIT_ACK = 0x1a,
106 R7xx_SQ_CF_INST_TEX_ACK = 0x1b,
107 R7xx_SQ_CF_INST_VTX_ACK = 0x1c,
108 R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d,
109 // SQ_VTX_WORD0 = 0x00008dfc,
110 // VTX_INST_mask = 0x1f << 0,
111 R7xx_SQ_VTX_INST_MEM = 0x02,
112 // SQ_VTX_WORD2 = 0x00008dfc,
113 R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
114
115 // SQ_TEX_WORD0 = 0x00008dfc,
116 // TEX_INST_mask = 0x1f << 0,
117 R7xx_X_MEMORY_READ = 0x02,
118 R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a,
119 R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f,
120 R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
121
122 R7xx_PA_SC_EDGERULE = 0x00028230,
123 R7xx_SPI_THREAD_GROUPING = 0x000286c8,
124 PS_GROUPING_mask = 0x1f << 0,
125 PS_GROUPING_shift = 0,
126 VS_GROUPING_mask = 0x1f << 8,
127 VS_GROUPING_shift = 8,
128 GS_GROUPING_mask = 0x1f << 16,
129 GS_GROUPING_shift = 16,
130 ES_GROUPING_mask = 0x1f << 24,
131 ES_GROUPING_shift = 24,
132 R7xx_CB_SHADER_CONTROL = 0x000287a0,
133 RT0_ENABLE_bit = 1 << 0,
134 RT1_ENABLE_bit = 1 << 1,
135 RT2_ENABLE_bit = 1 << 2,
136 RT3_ENABLE_bit = 1 << 3,
137 RT4_ENABLE_bit = 1 << 4,
138 RT5_ENABLE_bit = 1 << 5,
139 RT6_ENABLE_bit = 1 << 6,
140 RT7_ENABLE_bit = 1 << 7,
141 // DB_ALPHA_TO_MASK = 0x00028d44,
142 R7xx_OFFSET_ROUND_bit = 1 << 16,
143 // SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c,
144 R7xx_TRUNCATE_COORD_bit = 1 << 9,
145 R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10,
146
147 } ;
148
149 #endif /* _R600_REG_R7xx_H_ */