src/mesa/drivers/dri/r600/r600_tex.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 */
  28
  29 /**
  30  * \file
  31  *
  32  * \author Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/imports.h"
  37 #include "main/colormac.h"
  38 #include "main/context.h"
  39 #include "main/enums.h"
  40 #include "main/image.h"
  41 #include "main/mipmap.h"
  42 #include "main/simple_list.h"
  43 #include "main/texformat.h"
  44 #include "main/texstore.h"
  45 #include "main/teximage.h"
  46 #include "main/texobj.h"
  47
  48 #include "texmem.h"
  49
  50 #include "r600_context.h"
  51 #include "r700_state.h"
  52 #include "radeon_mipmap_tree.h"
  53 #include "r600_tex.h"
  54
  55 #include "xmlpool.h"
  56
  57
  58 static unsigned int translate_wrap_mode(GLenum wrapmode)
  59 {
  60         switch(wrapmode) {
  61         case GL_REPEAT: return SQ_TEX_WRAP;
  62         case GL_CLAMP: return SQ_TEX_CLAMP_HALF_BORDER;
  63         case GL_CLAMP_TO_EDGE: return SQ_TEX_CLAMP_LAST_TEXEL;
  64         case GL_CLAMP_TO_BORDER: return SQ_TEX_CLAMP_BORDER;
  65         case GL_MIRRORED_REPEAT: return SQ_TEX_MIRROR_ONCE_HALF_BORDER;
  66         case GL_MIRROR_CLAMP_EXT: return SQ_TEX_MIRROR;
  67         case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_BORDER;
  68         case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
  69         default:
  70                 _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__);
  71                 return 0;
  72         }
  73 }
  74
  75
  76 /**
  77  * Update the cached hardware registers based on the current texture wrap modes.
  78  *
  79  * \param t Texture object whose wrap modes are to be set
  80  */
  81 static void r600UpdateTexWrap(radeonTexObjPtr t)
  82 {
  83         struct gl_texture_object *tObj = &t->base;
  84
  85         SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapS),
  86                  SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
  87
  88         if (tObj->Target != GL_TEXTURE_1D) {
  89                 SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapT),
  90                          CLAMP_Y_shift, CLAMP_Y_mask);
  91
  92                 if (tObj->Target == GL_TEXTURE_3D)
  93                         SETfield(t->SQ_TEX_SAMPLER0, translate_wrap_mode(tObj->WrapR),
  94                                  CLAMP_Z_shift, CLAMP_Z_mask);
  95         }
  96 }
  97
  98 static void r600SetTexDefaultState(radeonTexObjPtr t)
  99 {
 100         /* Init text object to default states. */
 101         t->SQ_TEX_RESOURCE0              = 0;
 102         SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
 103         SETfield(t->SQ_TEX_RESOURCE0, ARRAY_LINEAR_GENERAL,
 104                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift, SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 105         CLEARbit(t->SQ_TEX_RESOURCE0, TILE_TYPE_bit);
 106
 107         t->SQ_TEX_RESOURCE1                = 0;
 108         SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 109                  SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 110
 111         t->SQ_TEX_RESOURCE2                = 0;
 112         t->SQ_TEX_RESOURCE3                = 0;
 113
 114         t->SQ_TEX_RESOURCE4                   = 0;
 115         SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
 116                  FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 117         SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
 118                  FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 119         SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
 120                  FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 121         SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
 122                  FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 123         SETfield(t->SQ_TEX_RESOURCE4, SQ_NUM_FORMAT_NORM,
 124                  SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift, SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask);
 125         CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit);
 126         CLEARbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
 127         SETfield(t->SQ_TEX_RESOURCE4, SQ_ENDIAN_NONE,
 128                  SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask);
 129         SETfield(t->SQ_TEX_RESOURCE4, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask);
 130         t->SQ_TEX_RESOURCE4 |= SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
 131                               |SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
 132                               |SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
 133                               |SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift;
 134         SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */
 135
 136         t->SQ_TEX_RESOURCE5 = 0;
 137         t->SQ_TEX_RESOURCE6 = 0;
 138
 139         SETfield(t->SQ_TEX_RESOURCE6, SQ_TEX_VTX_VALID_TEXTURE,
 140                  SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
 141
 142         /* Initialize sampler registers */
 143         t->SQ_TEX_SAMPLER0                           = 0;
 144         t->SQ_TEX_SAMPLER0 |=
 145                          SQ_TEX_WRAP << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift
 146                         |SQ_TEX_WRAP << CLAMP_Y_shift
 147                         |SQ_TEX_WRAP << CLAMP_Z_shift
 148                         |SQ_TEX_XY_FILTER_POINT << XY_MAG_FILTER_shift
 149                         |SQ_TEX_XY_FILTER_POINT << XY_MIN_FILTER_shift
 150                         |SQ_TEX_Z_FILTER_NONE << Z_FILTER_shift
 151                         |SQ_TEX_Z_FILTER_NONE << MIP_FILTER_shift
 152                         |SQ_TEX_BORDER_COLOR_TRANS_BLACK << BORDER_COLOR_TYPE_shift;
 153
 154         t->SQ_TEX_SAMPLER1 = 0x7FF << MAX_LOD_shift;
 155
 156         t->SQ_TEX_SAMPLER2                          = 0;
 157         SETbit(t->SQ_TEX_SAMPLER2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
 158 }
 159
 160
 161 static GLuint aniso_filter(GLfloat anisotropy)
 162 {
 163 #if 0
 164         if (anisotropy >= 16.0) {
 165                 return R300_TX_MAX_ANISO_16_TO_1;
 166         } else if (anisotropy >= 8.0) {
 167                 return R300_TX_MAX_ANISO_8_TO_1;
 168         } else if (anisotropy >= 4.0) {
 169                 return R300_TX_MAX_ANISO_4_TO_1;
 170         } else if (anisotropy >= 2.0) {
 171                 return R300_TX_MAX_ANISO_2_TO_1;
 172         } else {
 173                 return R300_TX_MAX_ANISO_1_TO_1;
 174         }
 175 #endif
 176         return 0;
 177 }
 178
 179 /**
 180  * Set the texture magnification and minification modes.
 181  *
 182  * \param t Texture whose filter modes are to be set
 183  * \param minf Texture minification mode
 184  * \param magf Texture magnification mode
 185  * \param anisotropy Maximum anisotropy level
 186  */
 187 static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
 188 {
 189         /* Force revalidation to account for switches from/to mipmapping. */
 190         t->validated = GL_FALSE;
 191
 192         /* Note that EXT_texture_filter_anisotropic is extremely vague about
 193          * how anisotropic filtering interacts with the "normal" filter modes.
 194          * When anisotropic filtering is enabled, we override min and mag
 195          * filter settings completely. This includes driconf's settings.
 196          */
 197         if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) {
 198                 /*t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO
 199                         | R300_TX_MIN_FILTER_ANISO
 200                         | R300_TX_MIN_FILTER_MIP_LINEAR
 201                         | aniso_filter(anisotropy);*/
 202                 if (RADEON_DEBUG & DEBUG_TEXTURE)
 203                         fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy);
 204                 return;
 205         }
 206
 207         switch (minf) {
 208         case GL_NEAREST:
 209                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
 210                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 211                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None,
 212                          MIP_FILTER_shift, MIP_FILTER_mask);
 213                 break;
 214         case GL_LINEAR:
 215                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
 216                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 217                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_None,
 218                          MIP_FILTER_shift, MIP_FILTER_mask);
 219                 break;
 220         case GL_NEAREST_MIPMAP_NEAREST:
 221                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
 222                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 223                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point,
 224                          MIP_FILTER_shift, MIP_FILTER_mask);
 225                 break;
 226         case GL_NEAREST_MIPMAP_LINEAR:
 227                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
 228                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 229                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear,
 230                          MIP_FILTER_shift, MIP_FILTER_mask);
 231                 break;
 232         case GL_LINEAR_MIPMAP_NEAREST:
 233                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
 234                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 235                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Point,
 236                          MIP_FILTER_shift, MIP_FILTER_mask);
 237                 break;
 238         case GL_LINEAR_MIPMAP_LINEAR:
 239                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
 240                          XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
 241                 SETfield(t->SQ_TEX_SAMPLER0, TEX_MipFilter_Linear,
 242                          MIP_FILTER_shift, MIP_FILTER_mask);
 243                 break;
 244         }
 245
 246         /* Note we don't have 3D mipmaps so only use the mag filter setting
 247          * to set the 3D texture filter mode.
 248          */
 249         switch (magf) {
 250         case GL_NEAREST:
 251                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Point,
 252                          XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
 253                 break;
 254         case GL_LINEAR:
 255                 SETfield(t->SQ_TEX_SAMPLER0, TEX_XYFilter_Linear,
 256                          XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
 257                 break;
 258         }
 259 }
 260
 261 static void r600SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4])
 262 {
 263 #if 0
 264         GLubyte c[4];
 265         CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
 266         CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
 267         CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
 268         CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
 269         t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]);
 270 #endif
 271 }
 272
 273 /**
 274  * Changes variables and flags for a state update, which will happen at the
 275  * next UpdateTextureState
 276  */
 277
 278 static void r600TexParameter(GLcontext * ctx, GLenum target,
 279                              struct gl_texture_object *texObj,
 280                              GLenum pname, const GLfloat * params)
 281 {
 282         radeonTexObj* t = radeon_tex_obj(texObj);
 283
 284         if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) {
 285                 fprintf(stderr, "%s( %s )\n", __FUNCTION__,
 286                         _mesa_lookup_enum_by_nr(pname));
 287         }
 288
 289         switch (pname) {
 290         case GL_TEXTURE_MIN_FILTER:
 291         case GL_TEXTURE_MAG_FILTER:
 292         case GL_TEXTURE_MAX_ANISOTROPY_EXT:
 293                 r600SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
 294                 break;
 295
 296         case GL_TEXTURE_WRAP_S:
 297         case GL_TEXTURE_WRAP_T:
 298         case GL_TEXTURE_WRAP_R:
 299                 r600UpdateTexWrap(t);
 300                 break;
 301
 302         case GL_TEXTURE_BORDER_COLOR:
 303                 r600SetTexBorderColor(t, texObj->BorderColor);
 304                 break;
 305
 306         case GL_TEXTURE_BASE_LEVEL:
 307         case GL_TEXTURE_MAX_LEVEL:
 308         case GL_TEXTURE_MIN_LOD:
 309         case GL_TEXTURE_MAX_LOD:
 310                 /* This isn't the most efficient solution but there doesn't appear to
 311                  * be a nice alternative.  Since there's no LOD clamping,
 312                  * we just have to rely on loading the right subset of mipmap levels
 313                  * to simulate a clamped LOD.
 314                  */
 315                 if (t->mt) {
 316                         radeon_miptree_unreference(t->mt);
 317                         t->mt = 0;
 318                         t->validated = GL_FALSE;
 319                 }
 320                 break;
 321
 322         case GL_DEPTH_TEXTURE_MODE:
 323                 if (!texObj->Image[0][texObj->BaseLevel])
 324                         return;
 325                 if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat
 326                     == GL_DEPTH_COMPONENT) {
 327                         r600SetDepthTexMode(texObj);
 328                         break;
 329                 } else {
 330                         /* If the texture isn't a depth texture, changing this
 331                          * state won't cause any changes to the hardware.
 332                          * Don't force a flush of texture state.
 333                          */
 334                         return;
 335                 }
 336
 337         default:
 338                 return;
 339         }
 340 }
 341
 342 static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
 343 {
 344         context_t* rmesa = R700_CONTEXT(ctx);
 345         radeonTexObj* t = radeon_tex_obj(texObj);
 346
 347         if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) {
 348                 fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__,
 349                         (void *)texObj,
 350                         _mesa_lookup_enum_by_nr(texObj->Target));
 351         }
 352
 353         if (rmesa) {
 354                 int i;
 355                 radeon_firevertices(&rmesa->radeon);
 356
 357                 for(i = 0; i < R700_MAX_TEXTURE_UNITS; ++i)
 358                         if (rmesa->hw.textures[i] == t)
 359                                 rmesa->hw.textures[i] = 0;
 360         }
 361
 362         if (t->bo) {
 363                 radeon_bo_unref(t->bo);
 364                 t->bo = NULL;
 365         }
 366
 367         if (t->mt) {
 368                 radeon_miptree_unreference(t->mt);
 369                 t->mt = 0;
 370         }
 371         _mesa_delete_texture_object(ctx, texObj);
 372 }
 373
 374 /**
 375  * Allocate a new texture object.
 376  * Called via ctx->Driver.NewTextureObject.
 377  * Note: this function will be called during context creation to
 378  * allocate the default texture objects.
 379  * Fixup MaxAnisotropy according to user preference.
 380  */
 381 static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx,
 382                                                       GLuint name,
 383                                                       GLenum target)
 384 {
 385         context_t* rmesa = R700_CONTEXT(ctx);
 386         radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
 387
 388
 389         if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) {
 390                 fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__,
 391                         t, _mesa_lookup_enum_by_nr(target));
 392         }
 393
 394         _mesa_initialize_texture_object(&t->base, name, target);
 395         t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
 396
 397         /* Initialize hardware state */
 398         r600SetTexDefaultState(t);
 399         r600UpdateTexWrap(t);
 400         r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
 401         r600SetTexBorderColor(t, t->base.BorderColor);
 402
 403         return &t->base;
 404 }
 405
 406 void r600InitTextureFuncs(struct dd_function_table *functions)
 407 {
 408         /* Note: we only plug in the functions we implement in the driver
 409          * since _mesa_init_driver_functions() was already called.
 410          */
 411         functions->NewTextureImage = radeonNewTextureImage;
 412         functions->FreeTexImageData = radeonFreeTexImageData;
 413         functions->MapTexture = radeonMapTexture;
 414         functions->UnmapTexture = radeonUnmapTexture;
 415
 416         functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa;
 417         functions->TexImage1D = radeonTexImage1D;
 418         functions->TexImage2D = radeonTexImage2D;
 419         functions->TexImage3D = radeonTexImage3D;
 420         functions->TexSubImage1D = radeonTexSubImage1D;
 421         functions->TexSubImage2D = radeonTexSubImage2D;
 422         functions->TexSubImage3D = radeonTexSubImage3D;
 423         functions->GetTexImage = radeonGetTexImage;
 424         functions->GetCompressedTexImage = radeonGetCompressedTexImage;
 425         functions->NewTextureObject = r600NewTextureObject;
 426         functions->DeleteTexture = r600DeleteTexture;
 427         functions->IsTextureResident = driIsTextureResident;
 428
 429         functions->TexParameter = r600TexParameter;
 430
 431         functions->CompressedTexImage2D = radeonCompressedTexImage2D;
 432         functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D;
 433
 434         functions->GenerateMipmap = radeonGenerateMipmap;
 435
 436         driInitTextureFormats();
 437 }