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7d7e77d355b710d1a4f33f281e7cb37f5c9c1bb0
[mesa.git] / src / mesa / drivers / dri / r600 / r600_texstate.c
1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file
32 *
33 * \author Keith Whitwell <keith@tungstengraphics.com>
34 *
35 * \todo Enable R300 texture tiling code?
36 */
37
38 #include "main/glheader.h"
39 #include "main/imports.h"
40 #include "main/context.h"
41 #include "main/macros.h"
42 #include "main/texformat.h"
43 #include "main/teximage.h"
44 #include "main/texobj.h"
45 #include "main/enums.h"
46 #include "main/simple_list.h"
47
48 #include "r600_context.h"
49 #include "r700_state.h"
50 #include "radeon_mipmap_tree.h"
51 #include "r600_tex.h"
52 #include "r700_fragprog.h"
53 #include "r700_vertprog.h"
54
55 void r600UpdateTextureState(GLcontext * ctx);
56
57 void r600UpdateTextureState(GLcontext * ctx)
58 {
59 context_t *context = R700_CONTEXT(ctx);
60 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
61 struct gl_texture_unit *texUnit;
62 struct radeon_tex_obj *t;
63 GLuint unit;
64
65 R600_STATECHANGE(context, tx);
66 R600_STATECHANGE(context, tx_smplr);
67 R600_STATECHANGE(context, tx_brdr_clr);
68
69 for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) {
70 texUnit = &ctx->Texture.Unit[unit];
71 t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
72 r700->textures[unit] = NULL;
73 if (texUnit->_ReallyEnabled) {
74 if (!t)
75 continue;
76 r700->textures[unit] = t;
77 }
78 }
79 }
80
81 static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_format)
82 {
83 radeonTexObj *t = radeon_tex_obj(tObj);
84
85 CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
86 CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
87 CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
88 CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
89
90 switch (mesa_format) /* This is mesa format. */
91 {
92 case MESA_FORMAT_RGBA8888:
93 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
94 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
95
96 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
97 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
98 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
99 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
100 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
101 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
102 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
103 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
104 break;
105 case MESA_FORMAT_RGBA8888_REV:
106 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
107 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
108
109 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
110 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
111 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
112 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
113 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
114 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
115 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
116 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
117 break;
118 case MESA_FORMAT_ARGB8888:
119 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
120 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
121
122 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
123 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
124 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
125 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
126 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
127 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
128 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
129 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
130 break;
131 case MESA_FORMAT_ARGB8888_REV:
132 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
133 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
134
135 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
136 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
137 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
138 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
139 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
140 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
141 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
142 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
143 break;
144 case MESA_FORMAT_RGB888:
145 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8,
146 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
147
148 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
149 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
150 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
151 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
152 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
153 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
154 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
155 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
156 break;
157 case MESA_FORMAT_RGB565:
158 SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
159 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
160
161 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
162 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
163 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
164 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
165 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
166 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
167 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
168 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
169 break;
170 case MESA_FORMAT_RGB565_REV:
171 SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
172 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
173
174 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
175 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
176 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
177 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
178 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
179 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
180 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
181 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
182 break;
183 case MESA_FORMAT_ARGB4444:
184 SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
185 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
186
187 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
188 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
189 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
190 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
191 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
192 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
193 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
194 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
195 break;
196 case MESA_FORMAT_ARGB4444_REV:
197 SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
198 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
199
200 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
201 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
202 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
203 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
204 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
205 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
206 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
207 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
208 break;
209 case MESA_FORMAT_ARGB1555:
210 SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
211 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
212
213 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
214 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
215 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
216 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
217 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
218 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
219 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
220 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
221 break;
222 case MESA_FORMAT_ARGB1555_REV:
223 SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
224 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
225
226 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
227 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
228 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
229 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
230 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
231 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
232 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
233 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
234 break;
235 case MESA_FORMAT_AL88:
236 case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
237 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8,
238 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
239
240 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
241 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
242 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
243 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
244 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
245 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
246 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
247 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
248 break;
249 case MESA_FORMAT_RGB332:
250 SETfield(t->SQ_TEX_RESOURCE1, FMT_3_3_2,
251 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
252
253 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
254 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
255 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
256 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
257 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
258 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
259 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
260 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
261 break;
262 case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
263 SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
264 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
265
266 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
267 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
268 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
269 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
270 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
271 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
272 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
273 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
274 break;
275 case MESA_FORMAT_L8: /* X, X, X, ONE */
276 SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
277 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
278
279 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
280 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
281 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
282 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
283 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
284 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
285 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
286 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
287 break;
288 case MESA_FORMAT_I8: /* X, X, X, X */
289 case MESA_FORMAT_CI8:
290 SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
291 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
292
293 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
294 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
295 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
296 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
297 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
298 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
299 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
300 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
301 break;
302 /* YUV422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */
303 /*
304 case MESA_FORMAT_YCBCR:
305 t->SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ;
306 break;
307 */
308 /* VUY422 TODO conversion */ /* X, Y, Z, ONE, G8R8_G8B8 */
309 /*
310 case MESA_FORMAT_YCBCR_REV:
311 t->SQ_TEX_RESOURCE1.bitfields.DATA_FORMAT = ;
312 break;
313 */
314 case MESA_FORMAT_RGB_DXT1: /* not supported yet */
315
316 break;
317 case MESA_FORMAT_RGBA_DXT1: /* not supported yet */
318
319 break;
320 case MESA_FORMAT_RGBA_DXT3: /* not supported yet */
321
322 break;
323 case MESA_FORMAT_RGBA_DXT5: /* not supported yet */
324
325 break;
326 case MESA_FORMAT_RGBA_FLOAT32:
327 SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_32_FLOAT,
328 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
329
330 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
331 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
332 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
333 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
334 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
335 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
336 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
337 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
338 break;
339 case MESA_FORMAT_RGBA_FLOAT16:
340 SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_16_FLOAT,
341 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
342
343 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
344 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
345 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
346 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
347 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
348 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
349 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
350 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
351 break;
352 case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */
353 SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_FLOAT,
354 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
355
356 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
357 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
358 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
359 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
360 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
361 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
362 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
363 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
364 break;
365 case MESA_FORMAT_RGB_FLOAT16:
366 SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_FLOAT,
367 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
368
369 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
370 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
371 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
372 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
373 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
374 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
375 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
376 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
377 break;
378 case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
379 SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
380 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
381
382 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
383 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
384 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
385 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
386 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
387 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
388 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
389 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
390 break;
391 case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
392 SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
393 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
394
395 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
396 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
397 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
398 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
399 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
400 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
401 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
402 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
403 break;
404 case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
405 SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
406 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
407
408 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
409 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
410 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
411 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
412 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
413 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
414 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
415 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
416 break;
417 case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
418 SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
419 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
420
421 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
422 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
423 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
424 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
425 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
426 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
427 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
428 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
429 break;
430 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
431 SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_FLOAT,
432 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
433
434 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
435 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
436 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
437 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
438 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
439 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
440 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
441 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
442 break;
443 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
444 SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_FLOAT,
445 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
446
447 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
448 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
449 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
450 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
451 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
452 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
453 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
454 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
455 break;
456 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
457 SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
458 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
459
460 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
461 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
462 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
463 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
464 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
465 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
466 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
467 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
468 break;
469 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
470 SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
471 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
472
473 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
474 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
475 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
476 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
477 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
478 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
479 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
480 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
481 break;
482 case MESA_FORMAT_Z16:
483 case MESA_FORMAT_Z24_S8:
484 case MESA_FORMAT_Z32:
485 switch (mesa_format) {
486 case MESA_FORMAT_Z16:
487 SETfield(t->SQ_TEX_RESOURCE1, FMT_16,
488 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
489 break;
490 case MESA_FORMAT_Z24_S8:
491 SETfield(t->SQ_TEX_RESOURCE1, FMT_24_8,
492 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
493 break;
494 case MESA_FORMAT_Z32:
495 SETfield(t->SQ_TEX_RESOURCE1, FMT_32,
496 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
497 break;
498 };
499 switch (tObj->DepthMode) {
500 case GL_LUMINANCE: /* X, X, X, ONE */
501 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
502 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
503 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
504 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
505 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
506 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
507 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
508 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
509 break;
510 case GL_INTENSITY: /* X, X, X, X */
511 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
512 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
513 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
514 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
515 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
516 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
517 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
518 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
519 break;
520 case GL_ALPHA: /* ZERO, ZERO, ZERO, X */
521 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
522 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
523 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
524 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
525 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
526 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
527 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
528 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
529 break;
530 default:
531 return GL_FALSE;
532 }
533 break;
534 /* EXT_texture_sRGB */
535 case MESA_FORMAT_SRGBA8:
536 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
537 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
538
539 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
540 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
541 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
542 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
543 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
544 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
545 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
546 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
547 SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
548 break;
549 case MESA_FORMAT_SLA8:
550 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8,
551 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
552
553 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
554 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
555 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
556 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
557 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
558 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
559 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
560 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
561 SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
562 break;
563 case MESA_FORMAT_SL8: /* X, X, X, ONE */
564 SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
565 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
566
567 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
568 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
569 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
570 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
571 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
572 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
573 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
574 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
575 SETbit(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
576 break;
577 default:
578 /* Not supported format */
579 return GL_FALSE;
580 };
581
582 return GL_TRUE;
583 }
584
585 void r600SetDepthTexMode(struct gl_texture_object *tObj)
586 {
587 radeonTexObjPtr t;
588
589 if (!tObj)
590 return;
591
592 t = radeon_tex_obj(tObj);
593
594 r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat);
595
596 }
597
598 /**
599 * Compute the cached hardware register values for the given texture object.
600 *
601 * \param rmesa Context pointer
602 * \param t the r300 texture object
603 */
604 static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *texObj)
605 {
606 radeonTexObj *t = radeon_tex_obj(texObj);
607 const struct gl_texture_image *firstImage;
608 int firstlevel = t->mt ? t->mt->firstLevel : 0;
609 GLuint uTexelPitch, row_align;
610
611 if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled &&
612 t->image_override &&
613 t->bo)
614 return;
615
616 firstImage = t->base.Image[0][firstlevel];
617
618 if (!t->image_override) {
619 if (!r600GetTexFormat(texObj, firstImage->TexFormat->MesaFormat)) {
620 radeon_error("unexpected texture format in %s\n",
621 __FUNCTION__);
622 return;
623 }
624 }
625
626 switch (texObj->Target) {
627 case GL_TEXTURE_1D:
628 SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_1D, DIM_shift, DIM_mask);
629 SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask);
630 break;
631 case GL_TEXTURE_2D:
632 case GL_TEXTURE_RECTANGLE_NV:
633 SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
634 SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask);
635 break;
636 case GL_TEXTURE_3D:
637 SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_3D, DIM_shift, DIM_mask);
638 SETfield(t->SQ_TEX_RESOURCE1, firstImage->Depth - 1, // ???
639 TEX_DEPTH_shift, TEX_DEPTH_mask);
640 break;
641 case GL_TEXTURE_CUBE_MAP:
642 SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_CUBEMAP, DIM_shift, DIM_mask);
643 SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask);
644 break;
645 default:
646 radeon_error("unexpected texture target type in %s\n", __FUNCTION__);
647 return;
648 }
649
650 row_align = rmesa->radeon.texture_row_align - 1;
651 uTexelPitch = ((firstImage->Width * t->mt->bpp + row_align) & ~row_align) / t->mt->bpp;
652 uTexelPitch = (uTexelPitch + R700_TEXEL_PITCH_ALIGNMENT_MASK)
653 & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
654
655 /* min pitch is 8 */
656 if (uTexelPitch < 8)
657 uTexelPitch = 8;
658
659 SETfield(t->SQ_TEX_RESOURCE0, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask);
660 SETfield(t->SQ_TEX_RESOURCE0, firstImage->Width - 1,
661 TEX_WIDTH_shift, TEX_WIDTH_mask);
662 SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1,
663 TEX_HEIGHT_shift, TEX_HEIGHT_mask);
664
665 if ((t->mt->lastLevel - t->mt->firstLevel) > 0) {
666 t->SQ_TEX_RESOURCE3 = t->mt->levels[0].size / 256;
667 SETfield(t->SQ_TEX_RESOURCE4, t->mt->firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask);
668 SETfield(t->SQ_TEX_RESOURCE5, t->mt->lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask);
669 }
670 }
671
672 /**
673 * Ensure the given texture is ready for rendering.
674 *
675 * Mostly this means populating the texture object's mipmap tree.
676 */
677 static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj)
678 {
679 context_t *rmesa = R700_CONTEXT(ctx);
680 radeonTexObj *t = radeon_tex_obj(texObj);
681
682 if (!radeon_validate_texture_miptree(ctx, texObj))
683 return GL_FALSE;
684
685 /* Configure the hardware registers (more precisely, the cached version
686 * of the hardware registers). */
687 setup_hardware_state(rmesa, texObj);
688
689 t->validated = GL_TRUE;
690 return GL_TRUE;
691 }
692
693 /**
694 * Ensure all enabled and complete textures are uploaded along with any buffers being used.
695 */
696 GLboolean r600ValidateBuffers(GLcontext * ctx)
697 {
698 context_t *rmesa = R700_CONTEXT(ctx);
699 struct radeon_renderbuffer *rrb;
700 struct radeon_bo *pbo;
701 int i;
702 int ret;
703
704 radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
705
706 rrb = radeon_get_colorbuffer(&rmesa->radeon);
707 /* color buffer */
708 if (rrb && rrb->bo) {
709 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
710 rrb->bo, 0,
711 RADEON_GEM_DOMAIN_VRAM);
712 }
713
714 /* depth buffer */
715 rrb = radeon_get_depthbuffer(&rmesa->radeon);
716 if (rrb && rrb->bo) {
717 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
718 rrb->bo, 0,
719 RADEON_GEM_DOMAIN_VRAM);
720 }
721
722 for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
723 radeonTexObj *t;
724
725 if (!ctx->Texture.Unit[i]._ReallyEnabled)
726 continue;
727
728 if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) {
729 radeon_warning("failed to validate texture for unit %d.\n", i);
730 }
731 t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
732 if (t->image_override && t->bo)
733 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
734 t->bo,
735 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
736 else if (t->mt->bo)
737 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
738 t->mt->bo,
739 RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
740 }
741
742 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(ctx);
743 if (pbo) {
744 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
745 RADEON_GEM_DOMAIN_GTT, 0);
746 }
747
748 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(ctx);
749 if (pbo) {
750 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, pbo,
751 RADEON_GEM_DOMAIN_GTT, 0);
752 }
753
754 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, first_elem(&rmesa->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
755 if (ret)
756 return GL_FALSE;
757 return GL_TRUE;
758 }
759
760 void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
761 unsigned long long offset, GLint depth, GLuint pitch)
762 {
763 context_t *rmesa = pDRICtx->driverPrivate;
764 struct gl_texture_object *tObj =
765 _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
766 radeonTexObjPtr t = radeon_tex_obj(tObj);
767 uint32_t pitch_val, size;
768
769 if (!tObj)
770 return;
771
772 t->image_override = GL_TRUE;
773
774 if (!offset)
775 return;
776
777 size = pitch;//h * w * (depth / 8);
778 if (t->bo) {
779 radeon_bo_unref(t->bo);
780 t->bo = NULL;
781 }
782 t->bo = radeon_legacy_bo_alloc_fake(rmesa->radeon.radeonScreen->bom, size, offset);
783 t->override_offset = offset;
784 pitch_val = pitch;
785 switch (depth) {
786 case 32:
787 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
788 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
789
790 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
791 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
792 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
793 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
794 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
795 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
796 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
797 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
798 pitch_val /= 4;
799 break;
800 case 24:
801 default:
802 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
803 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
804
805 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
806 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
807 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
808 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
809 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
810 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
811 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
812 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
813 pitch_val /= 4;
814 break;
815 case 16:
816 SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
817 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
818
819 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
820 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
821 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
822 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
823 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
824 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
825 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
826 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
827 pitch_val /= 2;
828 break;
829 }
830
831 pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
832 & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
833
834 /* min pitch is 8 */
835 if (pitch_val < 8)
836 pitch_val = 8;
837
838 SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
839 }
840
841 void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv)
842 {
843 struct gl_texture_unit *texUnit;
844 struct gl_texture_object *texObj;
845 struct gl_texture_image *texImage;
846 struct radeon_renderbuffer *rb;
847 radeon_texture_image *rImage;
848 radeonContextPtr radeon;
849 context_t *rmesa;
850 struct radeon_framebuffer *rfb;
851 radeonTexObjPtr t;
852 uint32_t pitch_val;
853 uint32_t internalFormat, type, format;
854
855 type = GL_BGRA;
856 format = GL_UNSIGNED_BYTE;
857 internalFormat = (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT ? 3 : 4);
858
859 radeon = pDRICtx->driverPrivate;
860 rmesa = pDRICtx->driverPrivate;
861
862 rfb = dPriv->driverPrivate;
863 texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
864 texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
865 texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
866
867 rImage = get_radeon_texture_image(texImage);
868 t = radeon_tex_obj(texObj);
869 if (t == NULL) {
870 return;
871 }
872
873 radeon_update_renderbuffers(pDRICtx, dPriv);
874 /* back & depth buffer are useless free them right away */
875 rb = (void*)rfb->base.Attachment[BUFFER_DEPTH].Renderbuffer;
876 if (rb && rb->bo) {
877 radeon_bo_unref(rb->bo);
878 rb->bo = NULL;
879 }
880 rb = (void*)rfb->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer;
881 if (rb && rb->bo) {
882 radeon_bo_unref(rb->bo);
883 rb->bo = NULL;
884 }
885 rb = rfb->color_rb[0];
886 if (rb->bo == NULL) {
887 /* Failed to BO for the buffer */
888 return;
889 }
890
891 _mesa_lock_texture(radeon->glCtx, texObj);
892 if (t->bo) {
893 radeon_bo_unref(t->bo);
894 t->bo = NULL;
895 }
896 if (rImage->bo) {
897 radeon_bo_unref(rImage->bo);
898 rImage->bo = NULL;
899 }
900 if (t->mt) {
901 radeon_miptree_unreference(t->mt);
902 t->mt = NULL;
903 }
904 if (rImage->mt) {
905 radeon_miptree_unreference(rImage->mt);
906 rImage->mt = NULL;
907 }
908 _mesa_init_teximage_fields(radeon->glCtx, target, texImage,
909 rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
910 texImage->RowStride = rb->pitch / rb->cpp;
911 texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
912 internalFormat,
913 type, format, 0);
914 rImage->bo = rb->bo;
915 radeon_bo_ref(rImage->bo);
916 t->bo = rb->bo;
917 radeon_bo_ref(t->bo);
918 t->image_override = GL_TRUE;
919 t->override_offset = 0;
920 pitch_val = rb->pitch;
921 switch (rb->cpp) {
922 case 4:
923 if (glx_texture_format == GLX_TEXTURE_FORMAT_RGB_EXT) {
924 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
925 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
926
927 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
928 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
929 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
930 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
931 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
932 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
933 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
934 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
935 } else {
936 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
937 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
938
939 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
940 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
941 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
942 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
943 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
944 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
945 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
946 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
947 }
948 pitch_val /= 4;
949 break;
950 case 3:
951 default:
952 // FMT_8_8_8 ???
953 SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
954 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
955
956 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
957 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
958 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
959 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
960 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
961 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
962 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
963 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
964 pitch_val /= 4;
965 break;
966 case 2:
967 SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
968 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
969
970 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
971 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
972 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
973 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
974 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
975 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
976 SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
977 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
978 pitch_val /= 2;
979 break;
980 }
981
982 pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
983 & ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
984
985 /* min pitch is 8 */
986 if (pitch_val < 8)
987 pitch_val = 8;
988
989 SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
990 SETfield(t->SQ_TEX_RESOURCE0, rb->base.Width - 1,
991 TEX_WIDTH_shift, TEX_WIDTH_mask);
992 SETfield(t->SQ_TEX_RESOURCE1, rb->base.Height - 1,
993 TEX_HEIGHT_shift, TEX_HEIGHT_mask);
994
995 t->validated = GL_TRUE;
996 _mesa_unlock_texture(radeon->glCtx, texObj);
997 return;
998 }
999
1000 void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
1001 {
1002 r600SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv);
1003 }