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[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30 #include "main/simple_list.h"
31
32 #include "r600_context.h"
33 #include "r600_cmdbuf.h"
34
35 #include "r700_state.h"
36 #include "r600_tex.h"
37 #include "r700_oglprog.h"
38 #include "r700_fragprog.h"
39 #include "r700_vertprog.h"
40 #include "r700_ioctl.h"
41
42 #include "radeon_mipmap_tree.h"
43
44 static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
45 {
46 context_t *context = R700_CONTEXT(ctx);
47 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
48 struct radeon_bo *bo = NULL;
49 unsigned int i;
50 BATCH_LOCALS(&context->radeon);
51
52 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
53
54 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
55 radeonTexObj *t = r700->textures[i];
56 if (t) {
57 if (!t->image_override)
58 bo = t->mt->bo;
59 else
60 bo = t->bo;
61 if (bo) {
62
63 r700SyncSurf(context, bo,
64 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
65 0, TC_ACTION_ENA_bit);
66
67 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
68 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
69 R600_OUT_BATCH(i * 7);
70 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
71 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
72 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
73 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
74 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
75 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
76 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
77 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
78 bo,
79 0,
80 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
81 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
82 bo,
83 r700->textures[i]->SQ_TEX_RESOURCE3,
84 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
85 END_BATCH();
86 COMMIT_BATCH();
87 }
88 }
89 }
90 }
91
92 static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
93 {
94 context_t *context = R700_CONTEXT(ctx);
95 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
96 unsigned int i;
97 BATCH_LOCALS(&context->radeon);
98 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
99
100 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
101 radeonTexObj *t = r700->textures[i];
102 if (t) {
103 BEGIN_BATCH_NO_AUTOSTATE(5);
104 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
105 R600_OUT_BATCH(i * 3);
106 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
107 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
108 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
109 END_BATCH();
110 COMMIT_BATCH();
111 }
112 }
113 }
114
115 static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
116 {
117 context_t *context = R700_CONTEXT(ctx);
118 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
119 unsigned int i;
120 BATCH_LOCALS(&context->radeon);
121 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
122
123 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
124 radeonTexObj *t = r700->textures[i];
125 if (t) {
126 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
127 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
128 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
129 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
130 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
131 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
132 END_BATCH();
133 COMMIT_BATCH();
134 }
135 }
136 }
137
138 static void r700SetupVTXConstants(GLcontext * ctx,
139 unsigned int nStreamID,
140 void * pAos,
141 unsigned int size, /* number of elements in vector */
142 unsigned int stride,
143 unsigned int count) /* number of vectors in stream */
144 {
145 context_t *context = R700_CONTEXT(ctx);
146 struct radeon_aos * paos = (struct radeon_aos *)pAos;
147 BATCH_LOCALS(&context->radeon);
148 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
149
150 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
151 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
152 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
153 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
154 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
155
156 if (!paos->bo)
157 return;
158
159 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
160 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
161 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
162 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
163 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
164 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
165 else
166 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
167
168 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
169 uSQ_VTX_CONSTANT_WORD1_0 = count * (size * 4) - 1;
170
171 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
172 SETfield(uSQ_VTX_CONSTANT_WORD2_0, stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
173 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
174 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(GL_FLOAT, size, NULL),
175 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
176 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
177 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
178 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
179 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
180
181 SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
182 SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
183 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
184
185 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
186
187 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
188 R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
189 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
190 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
191 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
192 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
193 R600_OUT_BATCH(0);
194 R600_OUT_BATCH(0);
195 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
196 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
197 paos->bo,
198 uSQ_VTX_CONSTANT_WORD0_0,
199 RADEON_GEM_DOMAIN_GTT, 0, 0);
200 END_BATCH();
201 COMMIT_BATCH();
202
203 }
204
205 void r700SetupStreams(GLcontext *ctx)
206 {
207 context_t *context = R700_CONTEXT(ctx);
208 struct r700_vertex_program *vpc
209 = (struct r700_vertex_program *)ctx->VertexProgram._Current;
210 TNLcontext *tnl = TNL_CONTEXT(ctx);
211 struct vertex_buffer *vb = &tnl->vb;
212 unsigned int i, j = 0;
213 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
214
215 R600_STATECHANGE(context, vtx);
216
217 for(i=0; i<VERT_ATTRIB_MAX; i++) {
218 if(vpc->mesa_program.Base.InputsRead & (1 << i)) {
219 rcommon_emit_vector(ctx,
220 &context->radeon.tcl.aos[j],
221 vb->AttribPtr[i]->data,
222 vb->AttribPtr[i]->size,
223 vb->AttribPtr[i]->stride,
224 vb->Count);
225 j++;
226 }
227 }
228 context->radeon.tcl.aos_count = j;
229 }
230
231 static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
232 {
233 context_t *context = R700_CONTEXT(ctx);
234 struct r700_vertex_program *vpc
235 = (struct r700_vertex_program *)ctx->VertexProgram._Current;
236 unsigned int i, j = 0;
237 BATCH_LOCALS(&context->radeon);
238 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
239
240 if (context->radeon.tcl.aos_count == 0)
241 return;
242
243 BEGIN_BATCH_NO_AUTOSTATE(6);
244 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
245 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
246 R600_OUT_BATCH(0);
247
248 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
249 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
250 R600_OUT_BATCH(0);
251 END_BATCH();
252 COMMIT_BATCH();
253
254 for(i=0; i<VERT_ATTRIB_MAX; i++) {
255 if(vpc->mesa_program.Base.InputsRead & (1 << i)) {
256 /* currently aos are packed */
257 r700SetupVTXConstants(ctx,
258 i,
259 (void*)(&context->radeon.tcl.aos[j]),
260 (unsigned int)context->radeon.tcl.aos[j].components,
261 (unsigned int)context->radeon.tcl.aos[j].stride * 4,
262 (unsigned int)context->radeon.tcl.aos[j].count);
263 j++;
264 }
265 }
266 }
267
268 static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
269 {
270 context_t *context = R700_CONTEXT(ctx);
271 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
272 struct radeon_renderbuffer *rrb;
273 BATCH_LOCALS(&context->radeon);
274 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
275
276 rrb = radeon_get_depthbuffer(&context->radeon);
277 if (!rrb || !rrb->bo) {
278 fprintf(stderr, "no rrb\n");
279 return;
280 }
281
282 BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
283 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
284 R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
285 R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
286 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
287 R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
288 R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
289 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
290 rrb->bo,
291 r700->DB_DEPTH_BASE.u32All,
292 0, RADEON_GEM_DOMAIN_VRAM, 0);
293 END_BATCH();
294
295 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
296 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
297 BEGIN_BATCH_NO_AUTOSTATE(2);
298 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
299 R600_OUT_BATCH(1 << 0);
300 END_BATCH();
301 }
302
303 COMMIT_BATCH();
304
305 }
306
307 static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
308 {
309 context_t *context = R700_CONTEXT(ctx);
310 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
311 struct radeon_renderbuffer *rrb;
312 BATCH_LOCALS(&context->radeon);
313 int id = 0;
314 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
315
316 rrb = radeon_get_colorbuffer(&context->radeon);
317 if (!rrb || !rrb->bo) {
318 fprintf(stderr, "no rrb\n");
319 return;
320 }
321
322 if (id > R700_MAX_RENDER_TARGETS)
323 return;
324
325 if (!r700->render_target[id].enabled)
326 return;
327
328 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
329 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
330 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
331 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
332 rrb->bo,
333 r700->render_target[id].CB_COLOR0_BASE.u32All,
334 0, RADEON_GEM_DOMAIN_VRAM, 0);
335 END_BATCH();
336
337 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
338 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
339 BEGIN_BATCH_NO_AUTOSTATE(2);
340 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
341 R600_OUT_BATCH((2 << id));
342 END_BATCH();
343 }
344
345 BEGIN_BATCH_NO_AUTOSTATE(18);
346 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
347 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
348 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
349 R600_OUT_BATCH_REGVAL(CB_COLOR0_TILE + (4 * id), r700->render_target[id].CB_COLOR0_TILE.u32All);
350 R600_OUT_BATCH_REGVAL(CB_COLOR0_FRAG + (4 * id), r700->render_target[id].CB_COLOR0_FRAG.u32All);
351 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
352 END_BATCH();
353
354 COMMIT_BATCH();
355
356 }
357
358 static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
359 {
360 context_t *context = R700_CONTEXT(ctx);
361 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
362 struct radeon_bo * pbo;
363 BATCH_LOCALS(&context->radeon);
364 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
365
366 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
367
368 if (!pbo)
369 return;
370
371 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
372
373 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
374 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
375 R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
376 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
377 pbo,
378 r700->ps.SQ_PGM_START_PS.u32All,
379 RADEON_GEM_DOMAIN_GTT, 0, 0);
380 END_BATCH();
381
382 BEGIN_BATCH_NO_AUTOSTATE(9);
383 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
384 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
385 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
386 END_BATCH();
387
388 COMMIT_BATCH();
389
390 }
391
392 static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
393 {
394 context_t *context = R700_CONTEXT(ctx);
395 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
396 struct radeon_bo * pbo;
397 BATCH_LOCALS(&context->radeon);
398 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
399
400 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
401
402 if (!pbo)
403 return;
404
405 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
406
407 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
408 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
409 R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
410 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
411 pbo,
412 r700->vs.SQ_PGM_START_VS.u32All,
413 RADEON_GEM_DOMAIN_GTT, 0, 0);
414 END_BATCH();
415
416 BEGIN_BATCH_NO_AUTOSTATE(6);
417 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
418 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
419 END_BATCH();
420
421 COMMIT_BATCH();
422 }
423
424 static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
425 {
426 context_t *context = R700_CONTEXT(ctx);
427 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
428 struct radeon_bo * pbo;
429 BATCH_LOCALS(&context->radeon);
430 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
431
432 /* XXX fixme
433 * R6xx chips require a FS be emitted, even if it's not used.
434 * since we aren't using FS yet, just send the VS address to make
435 * the kernel command checker happy
436 */
437 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
438 r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
439 r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
440 r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
441 /* XXX */
442
443 if (!pbo)
444 return;
445
446 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
447
448 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
449 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
450 R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
451 R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
452 pbo,
453 r700->fs.SQ_PGM_START_FS.u32All,
454 RADEON_GEM_DOMAIN_GTT, 0, 0);
455 END_BATCH();
456
457 BEGIN_BATCH_NO_AUTOSTATE(6);
458 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
459 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
460 END_BATCH();
461
462 COMMIT_BATCH();
463
464 }
465
466 static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
467 {
468 context_t *context = R700_CONTEXT(ctx);
469 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
470 BATCH_LOCALS(&context->radeon);
471 int id = 0;
472 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
473
474 if (id > R700_MAX_VIEWPORTS)
475 return;
476
477 if (!r700->viewport[id].enabled)
478 return;
479
480 BEGIN_BATCH_NO_AUTOSTATE(16);
481 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
482 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
483 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
484 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
485 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
486 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
487 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
488 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
489 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
490 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
491 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
492 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
493 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
494 END_BATCH();
495
496 COMMIT_BATCH();
497
498 }
499
500 static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
501 {
502 context_t *context = R700_CONTEXT(ctx);
503 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
504 BATCH_LOCALS(&context->radeon);
505 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
506
507 BEGIN_BATCH_NO_AUTOSTATE(34);
508 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
509 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
510 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
511 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
512 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
513 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
514 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
515
516 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
517 R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
518 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
519 R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
520 R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
521
522 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
523 R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
524 R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
525 R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
526 R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
527 R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
528 R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
529 R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
530 R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
531 R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
532 END_BATCH();
533
534 COMMIT_BATCH();
535 }
536
537 static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
538 {
539 context_t *context = R700_CONTEXT(ctx);
540 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
541 BATCH_LOCALS(&context->radeon);
542 int i;
543 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
544
545 for (i = 0; i < R700_MAX_UCP; i++) {
546 if (r700->ucp[i].enabled) {
547 BEGIN_BATCH_NO_AUTOSTATE(6);
548 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
549 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
550 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
551 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
552 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
553 END_BATCH();
554 COMMIT_BATCH();
555 }
556 }
557 }
558
559 static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
560 {
561 context_t *context = R700_CONTEXT(ctx);
562 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
563 BATCH_LOCALS(&context->radeon);
564 unsigned int ui;
565 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
566
567 BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
568
569 R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
570 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
571 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
572 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
573 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
574 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
575 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
576 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
577 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
578 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
579 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
580 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
581 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
582 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
583 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
584 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
585 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
586 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
587 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
588 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
589 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
590 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
591 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
592 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
593 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
594 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
595 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
596 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
597 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
598 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
599 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
600 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
601 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
602
603 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
604 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
605 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
606 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
607 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
608 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
609 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
610 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
611 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
612 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
613 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
614
615 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
616 R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
617 R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
618 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
619 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
620 R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
621 R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
622 R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
623 R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
624 R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
625
626 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
627 for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
628 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
629
630 END_BATCH();
631 COMMIT_BATCH();
632 }
633
634 static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
635 {
636 context_t *context = R700_CONTEXT(ctx);
637 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
638 BATCH_LOCALS(&context->radeon);
639 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
640
641 BEGIN_BATCH_NO_AUTOSTATE(41);
642
643 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
644 R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
645 R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
646 R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
647 R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
648
649 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
650 R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
651 R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
652 R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
653 R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
654 R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
655 R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
656 R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
657 R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
658 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
659 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
660 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
661 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
662 R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
663
664 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
665 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
666 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
667 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
668
669 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
670 R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
671 R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
672 R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
673
674 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
675
676 END_BATCH();
677 COMMIT_BATCH();
678 }
679
680 static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
681 {
682 context_t *context = R700_CONTEXT(ctx);
683 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
684 BATCH_LOCALS(&context->radeon);
685 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
686
687 BEGIN_BATCH_NO_AUTOSTATE(9);
688 R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
689 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
690 R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
691 END_BATCH();
692 COMMIT_BATCH();
693 }
694
695 static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
696 {
697 context_t *context = R700_CONTEXT(ctx);
698 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
699 BATCH_LOCALS(&context->radeon);
700 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
701
702 BEGIN_BATCH_NO_AUTOSTATE(23);
703 R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All);
704
705 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
706 R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
707 R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
708
709 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
710 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
711
712 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
713 R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
714 R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
715
716 R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
717 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
718
719 END_BATCH();
720 COMMIT_BATCH();
721 }
722
723 static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
724 {
725 context_t *context = R700_CONTEXT(ctx);
726 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
727 BATCH_LOCALS(&context->radeon);
728
729 BEGIN_BATCH_NO_AUTOSTATE(4);
730 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
731 R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
732 R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
733 END_BATCH();
734 COMMIT_BATCH();
735 }
736
737 static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
738 {
739 context_t *context = R700_CONTEXT(ctx);
740 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
741 BATCH_LOCALS(&context->radeon);
742 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
743
744 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
745 BEGIN_BATCH_NO_AUTOSTATE(11);
746 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
747 R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
748 R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
749 R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
750 R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
751 R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
752 R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
753 R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
754 R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
755 END_BATCH();
756 }
757
758 BEGIN_BATCH_NO_AUTOSTATE(7);
759 R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
760 R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
761 R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
762 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
763 END_BATCH();
764 COMMIT_BATCH();
765 }
766
767 static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
768 {
769 context_t *context = R700_CONTEXT(ctx);
770 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
771 BATCH_LOCALS(&context->radeon);
772
773 BEGIN_BATCH_NO_AUTOSTATE(6);
774 R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
775 R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
776 R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
777 R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
778 R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
779 END_BATCH();
780 COMMIT_BATCH();
781 }
782
783 static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
784 {
785 context_t *context = R700_CONTEXT(ctx);
786 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
787 BATCH_LOCALS(&context->radeon);
788 unsigned int ui;
789 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
790
791 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
792 BEGIN_BATCH_NO_AUTOSTATE(3);
793 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
794 END_BATCH();
795 }
796
797 BEGIN_BATCH_NO_AUTOSTATE(3);
798 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
799 END_BATCH();
800
801 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
802 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
803 if (r700->render_target[ui].enabled) {
804 BEGIN_BATCH_NO_AUTOSTATE(3);
805 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
806 r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
807 END_BATCH();
808 }
809 }
810 }
811
812 COMMIT_BATCH();
813 }
814
815 static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
816 {
817 context_t *context = R700_CONTEXT(ctx);
818 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
819 BATCH_LOCALS(&context->radeon);
820 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
821
822 BEGIN_BATCH_NO_AUTOSTATE(6);
823 R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
824 R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
825 R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
826 R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
827 R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
828 END_BATCH();
829 COMMIT_BATCH();
830 }
831
832 static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
833 {
834 context_t *context = R700_CONTEXT(ctx);
835 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
836 BATCH_LOCALS(&context->radeon);
837
838 BEGIN_BATCH_NO_AUTOSTATE(9);
839 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
840 R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
841 R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
842 R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
843 R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
844 R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
845 END_BATCH();
846 COMMIT_BATCH();
847
848 }
849
850 static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
851 {
852 context_t *context = R700_CONTEXT(ctx);
853 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
854 BATCH_LOCALS(&context->radeon);
855
856 BEGIN_BATCH_NO_AUTOSTATE(10);
857 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
858 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
859 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
860 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
861 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
862 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
863 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
864 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
865 END_BATCH();
866 COMMIT_BATCH();
867
868 }
869
870 static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
871 {
872 context_t *context = R700_CONTEXT(ctx);
873 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
874 BATCH_LOCALS(&context->radeon);
875 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
876
877 BEGIN_BATCH_NO_AUTOSTATE(12);
878 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
879 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
880 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
881 R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
882 END_BATCH();
883 COMMIT_BATCH();
884 }
885
886 static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
887 {
888 context_t *context = R700_CONTEXT(ctx);
889 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
890 BATCH_LOCALS(&context->radeon);
891
892 BEGIN_BATCH_NO_AUTOSTATE(6);
893 R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
894 R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
895 R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
896 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
897 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
898 END_BATCH();
899 COMMIT_BATCH();
900 }
901
902 static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
903 {
904 context_t *context = R700_CONTEXT(ctx);
905 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
906 BATCH_LOCALS(&context->radeon);
907 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
908
909 BEGIN_BATCH_NO_AUTOSTATE(22);
910 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
911 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
912 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
913
914 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
915 R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
916 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
917 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
918 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
919 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
920 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
921 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
922 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
923 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
924 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
925 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
926 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
927
928 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
929 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
930 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
931 END_BATCH();
932 COMMIT_BATCH();
933 }
934
935 static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
936 {
937 context_t *context = R700_CONTEXT(ctx);
938 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
939 BATCH_LOCALS(&context->radeon);
940 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
941
942 BEGIN_BATCH_NO_AUTOSTATE(15);
943 R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
944 R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
945 R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
946 R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
947 R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
948 END_BATCH();
949 COMMIT_BATCH();
950 }
951
952 static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
953 {
954 context_t *context = R700_CONTEXT(ctx);
955 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
956 BATCH_LOCALS(&context->radeon);
957
958 BEGIN_BATCH_NO_AUTOSTATE(12);
959 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
960 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
961 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
962 R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
963 END_BATCH();
964 COMMIT_BATCH();
965 }
966
967 static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
968 {
969 context_t *context = R700_CONTEXT(ctx);
970 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
971 int i;
972 BATCH_LOCALS(&context->radeon);
973
974 if (r700->ps.num_consts == 0)
975 return;
976
977 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
978 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
979 /* assembler map const from very beginning. */
980 R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
981 for (i = 0; i < r700->ps.num_consts; i++) {
982 R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
983 R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
984 R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
985 R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
986 }
987 END_BATCH();
988 COMMIT_BATCH();
989 }
990
991 static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
992 {
993 context_t *context = R700_CONTEXT(ctx);
994 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
995 int i;
996 BATCH_LOCALS(&context->radeon);
997 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
998
999 if (r700->vs.num_consts == 0)
1000 return;
1001
1002 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
1003 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
1004 /* assembler map const from very beginning. */
1005 R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
1006 for (i = 0; i < r700->vs.num_consts; i++) {
1007 R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
1008 R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
1009 R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
1010 R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
1011 }
1012 END_BATCH();
1013 COMMIT_BATCH();
1014 }
1015
1016 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
1017 {
1018 return atom->cmd_size;
1019 }
1020
1021 static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
1022 {
1023 context_t *context = R700_CONTEXT(ctx);
1024 int count = 7;
1025
1026 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1027 count += 11;
1028 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1029
1030 return count;
1031 }
1032
1033 static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
1034 {
1035 context_t *context = R700_CONTEXT(ctx);
1036 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1037 unsigned int ui;
1038 int count = 3;
1039
1040 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1041 count += 3;
1042
1043 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1044 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
1045 if (r700->render_target[ui].enabled)
1046 count += 3;
1047 }
1048 }
1049 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1050
1051 return count;
1052 }
1053
1054 static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
1055 {
1056 context_t *context = R700_CONTEXT(ctx);
1057 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1058 int i;
1059 int count = 0;
1060
1061 for (i = 0; i < R700_MAX_UCP; i++) {
1062 if (r700->ucp[i].enabled)
1063 count += 6;
1064 }
1065 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1066 return count;
1067 }
1068
1069 static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
1070 {
1071 context_t *context = R700_CONTEXT(ctx);
1072 int count = context->radeon.tcl.aos_count * 18;
1073
1074 if (count)
1075 count += 6;
1076
1077 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1078 return count;
1079 }
1080
1081 static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
1082 {
1083 context_t *context = R700_CONTEXT(ctx);
1084 unsigned int i, count = 0;
1085 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1086
1087 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
1088 radeonTexObj *t = r700->textures[i];
1089 if (t)
1090 count++;
1091 }
1092 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1093 return count * 31;
1094 }
1095
1096 static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1097 {
1098 context_t *context = R700_CONTEXT(ctx);
1099 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1100 int count = r700->ps.num_consts * 4;
1101
1102 if (count)
1103 count += 2;
1104 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1105
1106 return count;
1107 }
1108
1109 static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1110 {
1111 context_t *context = R700_CONTEXT(ctx);
1112 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1113 int count = r700->vs.num_consts * 4;
1114
1115 if (count)
1116 count += 2;
1117 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1118
1119 return count;
1120 }
1121
1122 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
1123 do { \
1124 context->atoms.ATOM.cmd_size = (SZ); \
1125 context->atoms.ATOM.cmd = NULL; \
1126 context->atoms.ATOM.name = #ATOM; \
1127 context->atoms.ATOM.idx = 0; \
1128 context->atoms.ATOM.check = check_##CHK; \
1129 context->atoms.ATOM.dirty = GL_FALSE; \
1130 context->atoms.ATOM.emit = (EMIT); \
1131 context->radeon.hw.max_state_size += (SZ); \
1132 insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1133 } while (0)
1134
1135 void r600InitAtoms(context_t *context)
1136 {
1137 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1138 context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1139
1140 /* Setup the atom linked list */
1141 make_empty_list(&context->radeon.hw.atomlist);
1142 context->radeon.hw.atomlist.name = "atom-list";
1143
1144 ALLOC_STATE(sq, always, 34, r700SendSQConfig);
1145 ALLOC_STATE(db, always, 23, r700SendDBState);
1146 ALLOC_STATE(stencil, always, 4, r700SendStencilState);
1147 ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
1148 ALLOC_STATE(sc, always, 15, r700SendSCState);
1149 ALLOC_STATE(scissor, always, 22, r700SendScissorState);
1150 ALLOC_STATE(aa, always, 12, r700SendAAState);
1151 ALLOC_STATE(cl, always, 12, r700SendCLState);
1152 ALLOC_STATE(gb, always, 6, r700SendGBState);
1153 ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
1154 ALLOC_STATE(su, always, 9, r700SendSUState);
1155 ALLOC_STATE(poly, always, 10, r700SendPolyState);
1156 ALLOC_STATE(cb, cb, 18, r700SendCBState);
1157 ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
1158 ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
1159 ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
1160 ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState);
1161 ALLOC_STATE(sx, always, 9, r700SendSXState);
1162 ALLOC_STATE(vgt, always, 41, r700SendVGTState);
1163 ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
1164 ALLOC_STATE(vpt, always, 16, r700SendViewportState);
1165 ALLOC_STATE(fs, always, 18, r700SendFSState);
1166 ALLOC_STATE(vs, always, 18, r700SendVSState);
1167 ALLOC_STATE(ps, always, 21, r700SendPSState);
1168 ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
1169 ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
1170 ALLOC_STATE(vtx, vtx, (6 + (VERT_ATTRIB_MAX * 18)), r700SendVTXState);
1171 ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
1172 ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
1173 ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
1174
1175 context->radeon.hw.is_dirty = GL_TRUE;
1176 context->radeon.hw.all_dirty = GL_TRUE;
1177 }