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[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "r700_state.h"
35 #include "r600_tex.h"
36 #include "r700_oglprog.h"
37 #include "r700_fragprog.h"
38 #include "r700_vertprog.h"
39 #include "r700_ioctl.h"
40
41 #define LINK_STATES(reg) \
42 do \
43 { \
44 pStateListWork->puiValue = (unsigned int*)&(r700->reg); \
45 pStateListWork->unOffset = mm##reg - ASIC_CONTEXT_BASE_INDEX; \
46 pStateListWork->pNext = pStateListWork + 1; \
47 pStateListWork++; \
48 }while(0)
49
50 GLboolean r700InitChipObject(context_t *context)
51 {
52 ContextState * pStateListWork;
53
54 R700_CHIP_CONTEXT *r700 = &context->hw;
55
56 /* init state list */
57 r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int));
58 pStateListWork = r700->pStateList;
59
60 // misc
61 LINK_STATES(TA_CNTL_AUX);
62 LINK_STATES(VC_ENHANCE);
63 LINK_STATES(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ);
64 LINK_STATES(DB_DEBUG);
65 LINK_STATES(DB_WATERMARKS);
66
67 // DB
68 LINK_STATES(DB_DEPTH_SIZE);
69 LINK_STATES(DB_DEPTH_VIEW);
70 LINK_STATES(DB_DEPTH_BASE);
71 LINK_STATES(DB_DEPTH_INFO);
72 LINK_STATES(DB_HTILE_DATA_BASE);
73 LINK_STATES(DB_STENCIL_CLEAR);
74 LINK_STATES(DB_DEPTH_CLEAR);
75 LINK_STATES(DB_DEPTH_CONTROL);
76 LINK_STATES(DB_SHADER_CONTROL);
77 LINK_STATES(DB_RENDER_CONTROL);
78 LINK_STATES(DB_RENDER_OVERRIDE);
79 LINK_STATES(DB_HTILE_SURFACE);
80 LINK_STATES(DB_ALPHA_TO_MASK);
81
82 // SC
83 LINK_STATES(PA_SC_SCREEN_SCISSOR_TL);
84 LINK_STATES(PA_SC_SCREEN_SCISSOR_BR);
85 LINK_STATES(PA_SC_WINDOW_OFFSET);
86 LINK_STATES(PA_SC_WINDOW_SCISSOR_TL);
87 LINK_STATES(PA_SC_WINDOW_SCISSOR_BR);
88 LINK_STATES(PA_SC_CLIPRECT_RULE);
89 LINK_STATES(PA_SC_CLIPRECT_0_TL);
90 LINK_STATES(PA_SC_CLIPRECT_0_BR);
91 LINK_STATES(PA_SC_CLIPRECT_1_TL);
92 LINK_STATES(PA_SC_CLIPRECT_1_BR);
93 LINK_STATES(PA_SC_CLIPRECT_2_TL);
94 LINK_STATES(PA_SC_CLIPRECT_2_BR);
95 LINK_STATES(PA_SC_CLIPRECT_3_TL);
96 LINK_STATES(PA_SC_CLIPRECT_3_BR);
97 LINK_STATES(PA_SC_EDGERULE);
98 LINK_STATES(PA_SC_GENERIC_SCISSOR_TL);
99 LINK_STATES(PA_SC_GENERIC_SCISSOR_BR);
100 LINK_STATES(PA_SC_LINE_STIPPLE);
101 LINK_STATES(PA_SC_MPASS_PS_CNTL);
102 LINK_STATES(PA_SC_MODE_CNTL);
103 LINK_STATES(PA_SC_LINE_CNTL);
104 LINK_STATES(PA_SC_AA_CONFIG);
105 LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX);
106 LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX);
107 LINK_STATES(PA_SC_AA_MASK);
108
109 // SU
110 LINK_STATES(PA_SU_POINT_SIZE);
111 LINK_STATES(PA_SU_POINT_MINMAX);
112 LINK_STATES(PA_SU_LINE_CNTL);
113 LINK_STATES(PA_SU_SC_MODE_CNTL);
114 LINK_STATES(PA_SU_VTX_CNTL);
115 LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL);
116 LINK_STATES(PA_SU_POLY_OFFSET_CLAMP);
117 LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE);
118 LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET);
119 LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE);
120
121 // CL
122 LINK_STATES(PA_CL_CLIP_CNTL);
123 LINK_STATES(PA_CL_VTE_CNTL);
124 LINK_STATES(PA_CL_VS_OUT_CNTL);
125 LINK_STATES(PA_CL_NANINF_CNTL);
126 LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ);
127 LINK_STATES(PA_CL_GB_VERT_DISC_ADJ);
128 LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ);
129 LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ);
130
131 // CB
132 LINK_STATES(CB_CLEAR_RED_R6XX);
133 LINK_STATES(CB_CLEAR_GREEN_R6XX);
134 LINK_STATES(CB_CLEAR_BLUE_R6XX);
135 LINK_STATES(CB_CLEAR_ALPHA_R6XX);
136 LINK_STATES(CB_TARGET_MASK);
137 LINK_STATES(CB_SHADER_MASK);
138 LINK_STATES(CB_BLEND_RED);
139 LINK_STATES(CB_BLEND_GREEN);
140 LINK_STATES(CB_BLEND_BLUE);
141 LINK_STATES(CB_BLEND_ALPHA);
142 LINK_STATES(CB_FOG_RED_R6XX);
143 LINK_STATES(CB_FOG_GREEN_R6XX);
144 LINK_STATES(CB_FOG_BLUE_R6XX);
145 LINK_STATES(CB_SHADER_CONTROL);
146 LINK_STATES(CB_COLOR_CONTROL);
147 LINK_STATES(CB_CLRCMP_CONTROL);
148 LINK_STATES(CB_CLRCMP_SRC);
149 LINK_STATES(CB_CLRCMP_DST);
150 LINK_STATES(CB_CLRCMP_MSK);
151 LINK_STATES(CB_BLEND_CONTROL);
152
153 // SX
154 LINK_STATES(SX_MISC);
155 LINK_STATES(SX_ALPHA_TEST_CONTROL);
156
157 // VGT
158 LINK_STATES(VGT_MAX_VTX_INDX);
159 LINK_STATES(VGT_MIN_VTX_INDX);
160 LINK_STATES(VGT_INDX_OFFSET);
161 LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX);
162 LINK_STATES(VGT_OUTPUT_PATH_CNTL);
163 LINK_STATES(VGT_HOS_CNTL);
164 LINK_STATES(VGT_HOS_MAX_TESS_LEVEL);
165 LINK_STATES(VGT_HOS_MIN_TESS_LEVEL);
166 LINK_STATES(VGT_HOS_REUSE_DEPTH);
167 LINK_STATES(VGT_GROUP_PRIM_TYPE);
168 LINK_STATES(VGT_GROUP_FIRST_DECR);
169 LINK_STATES(VGT_GROUP_DECR);
170 LINK_STATES(VGT_GROUP_VECT_0_CNTL);
171 LINK_STATES(VGT_GROUP_VECT_1_CNTL);
172 LINK_STATES(VGT_GROUP_VECT_0_FMT_CNTL);
173 LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL);
174 LINK_STATES(VGT_GS_MODE);
175 LINK_STATES(VGT_PRIMITIVEID_EN);
176 LINK_STATES(VGT_DMA_NUM_INSTANCES);
177 LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN);
178 LINK_STATES(VGT_INSTANCE_STEP_RATE_0);
179 LINK_STATES(VGT_INSTANCE_STEP_RATE_1);
180 LINK_STATES(VGT_STRMOUT_EN);
181 LINK_STATES(VGT_REUSE_OFF);
182 LINK_STATES(VGT_VTX_CNT_EN);
183 LINK_STATES(VGT_STRMOUT_BUFFER_EN);
184
185 LINK_STATES(SQ_VTX_SEMANTIC_0);
186 LINK_STATES(SQ_VTX_SEMANTIC_1);
187 LINK_STATES(SQ_VTX_SEMANTIC_2);
188 LINK_STATES(SQ_VTX_SEMANTIC_3);
189 LINK_STATES(SQ_VTX_SEMANTIC_4);
190 LINK_STATES(SQ_VTX_SEMANTIC_5);
191 LINK_STATES(SQ_VTX_SEMANTIC_6);
192 LINK_STATES(SQ_VTX_SEMANTIC_7);
193 LINK_STATES(SQ_VTX_SEMANTIC_8);
194 LINK_STATES(SQ_VTX_SEMANTIC_9);
195 LINK_STATES(SQ_VTX_SEMANTIC_10);
196 LINK_STATES(SQ_VTX_SEMANTIC_11);
197 LINK_STATES(SQ_VTX_SEMANTIC_12);
198 LINK_STATES(SQ_VTX_SEMANTIC_13);
199 LINK_STATES(SQ_VTX_SEMANTIC_14);
200 LINK_STATES(SQ_VTX_SEMANTIC_15);
201 LINK_STATES(SQ_VTX_SEMANTIC_16);
202 LINK_STATES(SQ_VTX_SEMANTIC_17);
203 LINK_STATES(SQ_VTX_SEMANTIC_18);
204 LINK_STATES(SQ_VTX_SEMANTIC_19);
205 LINK_STATES(SQ_VTX_SEMANTIC_20);
206 LINK_STATES(SQ_VTX_SEMANTIC_21);
207 LINK_STATES(SQ_VTX_SEMANTIC_22);
208 LINK_STATES(SQ_VTX_SEMANTIC_23);
209 LINK_STATES(SQ_VTX_SEMANTIC_24);
210 LINK_STATES(SQ_VTX_SEMANTIC_25);
211 LINK_STATES(SQ_VTX_SEMANTIC_26);
212 LINK_STATES(SQ_VTX_SEMANTIC_27);
213 LINK_STATES(SQ_VTX_SEMANTIC_28);
214 LINK_STATES(SQ_VTX_SEMANTIC_29);
215 LINK_STATES(SQ_VTX_SEMANTIC_30);
216 LINK_STATES(SQ_VTX_SEMANTIC_31);
217
218 // SPI
219 LINK_STATES(SPI_VS_OUT_ID_0);
220 LINK_STATES(SPI_VS_OUT_ID_1);
221 LINK_STATES(SPI_VS_OUT_ID_2);
222 LINK_STATES(SPI_VS_OUT_ID_3);
223 LINK_STATES(SPI_VS_OUT_ID_4);
224 LINK_STATES(SPI_VS_OUT_ID_5);
225 LINK_STATES(SPI_VS_OUT_ID_6);
226 LINK_STATES(SPI_VS_OUT_ID_7);
227 LINK_STATES(SPI_VS_OUT_ID_8);
228 LINK_STATES(SPI_VS_OUT_ID_9);
229
230 LINK_STATES(SPI_PS_INPUT_CNTL_0);
231 LINK_STATES(SPI_PS_INPUT_CNTL_1);
232 LINK_STATES(SPI_PS_INPUT_CNTL_2);
233 LINK_STATES(SPI_PS_INPUT_CNTL_3);
234 LINK_STATES(SPI_PS_INPUT_CNTL_4);
235 LINK_STATES(SPI_PS_INPUT_CNTL_5);
236 LINK_STATES(SPI_PS_INPUT_CNTL_6);
237 LINK_STATES(SPI_PS_INPUT_CNTL_7);
238 LINK_STATES(SPI_PS_INPUT_CNTL_8);
239 LINK_STATES(SPI_PS_INPUT_CNTL_9);
240 LINK_STATES(SPI_PS_INPUT_CNTL_10);
241 LINK_STATES(SPI_PS_INPUT_CNTL_11);
242 LINK_STATES(SPI_PS_INPUT_CNTL_12);
243 LINK_STATES(SPI_PS_INPUT_CNTL_13);
244 LINK_STATES(SPI_PS_INPUT_CNTL_14);
245 LINK_STATES(SPI_PS_INPUT_CNTL_15);
246 LINK_STATES(SPI_PS_INPUT_CNTL_16);
247 LINK_STATES(SPI_PS_INPUT_CNTL_17);
248 LINK_STATES(SPI_PS_INPUT_CNTL_18);
249 LINK_STATES(SPI_PS_INPUT_CNTL_19);
250 LINK_STATES(SPI_PS_INPUT_CNTL_20);
251 LINK_STATES(SPI_PS_INPUT_CNTL_21);
252 LINK_STATES(SPI_PS_INPUT_CNTL_22);
253 LINK_STATES(SPI_PS_INPUT_CNTL_23);
254 LINK_STATES(SPI_PS_INPUT_CNTL_24);
255 LINK_STATES(SPI_PS_INPUT_CNTL_25);
256 LINK_STATES(SPI_PS_INPUT_CNTL_26);
257 LINK_STATES(SPI_PS_INPUT_CNTL_27);
258 LINK_STATES(SPI_PS_INPUT_CNTL_28);
259 LINK_STATES(SPI_PS_INPUT_CNTL_29);
260 LINK_STATES(SPI_PS_INPUT_CNTL_30);
261 LINK_STATES(SPI_PS_INPUT_CNTL_31);
262
263 LINK_STATES(SPI_VS_OUT_CONFIG);
264 LINK_STATES(SPI_THREAD_GROUPING);
265 LINK_STATES(SPI_PS_IN_CONTROL_0);
266 LINK_STATES(SPI_PS_IN_CONTROL_1);
267 LINK_STATES(SPI_INTERP_CONTROL_0);
268 LINK_STATES(SPI_INPUT_Z);
269 LINK_STATES(SPI_FOG_CNTL);
270 LINK_STATES(SPI_FOG_FUNC_SCALE);
271 LINK_STATES(SPI_FOG_FUNC_BIAS);
272
273 // SQ
274 LINK_STATES(SQ_ESGS_RING_ITEMSIZE);
275 LINK_STATES(SQ_GSVS_RING_ITEMSIZE);
276 LINK_STATES(SQ_ESTMP_RING_ITEMSIZE);
277 LINK_STATES(SQ_GSTMP_RING_ITEMSIZE);
278 LINK_STATES(SQ_VSTMP_RING_ITEMSIZE);
279 LINK_STATES(SQ_PSTMP_RING_ITEMSIZE);
280 LINK_STATES(SQ_FBUF_RING_ITEMSIZE);
281 LINK_STATES(SQ_REDUC_RING_ITEMSIZE);
282 //LINK_STATES(SQ_GS_VERT_ITEMSIZE);
283
284 pStateListWork->puiValue = (unsigned int*)&(r700->SQ_GS_VERT_ITEMSIZE);
285 pStateListWork->unOffset = mmSQ_GS_VERT_ITEMSIZE - ASIC_CONTEXT_BASE_INDEX;
286 pStateListWork->pNext = NULL; /* END OF STATE LIST */
287
288 return GL_TRUE;
289 }
290
291 void r700SetupVTXConstants(GLcontext * ctx,
292 unsigned int nStreamID,
293 void * pAos,
294 unsigned int size, /* number of elements in vector */
295 unsigned int stride,
296 unsigned int count) /* number of vectors in stream */
297 {
298 context_t *context = R700_CONTEXT(ctx);
299 uint32_t *dest;
300 struct radeon_aos * paos = (struct radeon_aos *)pAos;
301 offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF};
302
303 BATCH_LOCALS(&context->radeon);
304
305 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
306 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
307 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
308 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
309 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
310
311 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
312 uSQ_VTX_CONSTANT_WORD1_0 = count * (size * 4) - 1;
313
314 uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */
315 |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift
316 |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */
317 |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift
318 |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit;
319
320 uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift;
321
322 uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift;
323
324 BEGIN_BATCH_NO_AUTOSTATE(9);
325
326 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
327 R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
328
329 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
330 paos->bo,
331 uSQ_VTX_CONSTANT_WORD0_0,
332 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
333 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
334 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
335 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
336 R600_OUT_BATCH(0);
337 R600_OUT_BATCH(0);
338 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
339
340 END_BATCH();
341 COMMIT_BATCH();
342
343 }
344
345 int r700SetupStreams(GLcontext * ctx)
346 {
347 context_t *context = R700_CONTEXT(ctx);
348
349 BATCH_LOCALS(&context->radeon);
350
351 struct r700_vertex_program *vpc
352 = (struct r700_vertex_program *)ctx->VertexProgram._Current;
353
354 TNLcontext *tnl = TNL_CONTEXT(ctx);
355 struct vertex_buffer *vb = &tnl->vb;
356
357 unsigned int unBit;
358 unsigned int i;
359
360 BEGIN_BATCH_NO_AUTOSTATE(6);
361 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
362 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
363 R600_OUT_BATCH(0);
364
365 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
366 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
367 R600_OUT_BATCH(0);
368 END_BATCH();
369 COMMIT_BATCH();
370
371 context->radeon.tcl.aos_count = 0;
372 for(i=0; i<VERT_ATTRIB_MAX; i++)
373 {
374 unBit = 1 << i;
375 if(vpc->mesa_program.Base.InputsRead & unBit)
376 {
377 rcommon_emit_vector(ctx,
378 &context->radeon.tcl.aos[i],
379 vb->AttribPtr[i]->data,
380 vb->AttribPtr[i]->size,
381 vb->AttribPtr[i]->stride,
382 vb->Count);
383
384 /* currently aos are packed */
385 r700SetupVTXConstants(ctx,
386 i,
387 (void*)(&context->radeon.tcl.aos[i]),
388 (unsigned int)context->radeon.tcl.aos[i].components,
389 (unsigned int)context->radeon.tcl.aos[i].stride * 4,
390 (unsigned int)context->radeon.tcl.aos[i].count);
391
392 context->radeon.tcl.aos_count++;
393 }
394 }
395
396 return R600_FALLBACK_NONE;
397 }
398
399 inline GLboolean needRelocReg(context_t *context, unsigned int reg)
400 {
401 switch (reg + ASIC_CONTEXT_BASE_INDEX)
402 {
403 case mmCB_COLOR0_BASE:
404 case mmCB_COLOR1_BASE:
405 case mmCB_COLOR2_BASE:
406 case mmCB_COLOR3_BASE:
407 case mmCB_COLOR4_BASE:
408 case mmCB_COLOR5_BASE:
409 case mmCB_COLOR6_BASE:
410 case mmCB_COLOR7_BASE:
411 case mmDB_DEPTH_BASE:
412 case mmSQ_PGM_START_VS:
413 case mmSQ_PGM_START_FS:
414 case mmSQ_PGM_START_ES:
415 case mmSQ_PGM_START_GS:
416 case mmSQ_PGM_START_PS:
417 return GL_TRUE;
418 break;
419 }
420
421 return GL_FALSE;
422 }
423
424 inline GLboolean setRelocReg(context_t *context, unsigned int reg)
425 {
426 BATCH_LOCALS(&context->radeon);
427 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
428
429 struct radeon_bo * pbo;
430 uint32_t voffset;
431 offset_modifiers offset_mod;
432
433 switch (reg + ASIC_CONTEXT_BASE_INDEX)
434 {
435 case mmDB_DEPTH_BASE:
436 {
437 GLcontext *ctx = GL_CONTEXT(context);
438 struct radeon_renderbuffer *rrb;
439 rrb = radeon_get_depthbuffer(&context->radeon);
440
441 offset_mod.shift = NO_SHIFT;
442 offset_mod.shiftbits = 0;
443 offset_mod.mask = 0xFFFFFFFF;
444
445 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
446 rrb->bo,
447 r700->DB_DEPTH_BASE.u32All,
448 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
449
450 return GL_TRUE;
451 }
452 break;
453 }
454
455 return GL_FALSE;
456 }
457
458 GLboolean r700SendContextStates(context_t *context)
459 {
460 BATCH_LOCALS(&context->radeon);
461
462 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
463
464 ContextState * pState = r700->pStateList;
465 ContextState * pInit;
466 unsigned int toSend;
467 unsigned int ui;
468
469 while(NULL != pState)
470 {
471 toSend = 1;
472
473 pInit = pState;
474
475 if(GL_FALSE == needRelocReg(context, pState->unOffset))
476 {
477 while(NULL != pState->pNext)
478 {
479 if( ((pState->pNext->unOffset - pState->unOffset) > 1)
480 || (GL_TRUE == needRelocReg(context, pState->pNext->unOffset)) )
481 {
482 break;
483 }
484 else
485 {
486 pState = pState->pNext;
487 toSend++;
488 }
489 };
490 }
491
492 pState = pState->pNext;
493
494 BEGIN_BATCH_NO_AUTOSTATE(toSend + 2);
495 R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend);
496 for(ui=0; ui<toSend; ui++)
497 {
498 if( GL_FALSE == setRelocReg(context, pInit->unOffset) )
499 {
500 /* for not reloc reg. */
501 R600_OUT_BATCH(*(pInit->puiValue));
502 }
503 pInit = pInit->pNext;
504 };
505 END_BATCH();
506 };
507 COMMIT_BATCH();
508
509 return GL_TRUE;
510 }
511
512
513 GLboolean r700SendRenderTargetState(context_t *context, int id)
514 {
515 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
516 struct radeon_renderbuffer *rrb;
517 struct radeon_bo * pbo;
518 offset_modifiers offset_mod;
519 BATCH_LOCALS(&context->radeon);
520
521 rrb = radeon_get_colorbuffer(&context->radeon);
522 if (!rrb || !rrb->bo) {
523 fprintf(stderr, "no rrb\n");
524 return GL_FALSE;
525 }
526
527 if (id > R700_MAX_RENDER_TARGETS)
528 return GL_FALSE;
529
530 if (!r700->render_target[id].enabled)
531 return GL_FALSE;
532
533 offset_mod.shift = NO_SHIFT;
534 offset_mod.shiftbits = 0;
535 offset_mod.mask = 0xFFFFFFFF;
536
537 BEGIN_BATCH_NO_AUTOSTATE(3);
538 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
539 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
540 rrb->bo,
541 r700->render_target[id].CB_COLOR0_BASE.u32All,
542 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
543 END_BATCH();
544
545 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
546 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
547 BEGIN_BATCH_NO_AUTOSTATE(2);
548 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
549 R600_OUT_BATCH((2 << id));
550 END_BATCH();
551 }
552
553 BEGIN_BATCH_NO_AUTOSTATE(18);
554 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
555 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
556 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
557 R600_OUT_BATCH_REGVAL(CB_COLOR0_TILE + (4 * id), r700->render_target[id].CB_COLOR0_TILE.u32All);
558 R600_OUT_BATCH_REGVAL(CB_COLOR0_FRAG + (4 * id), r700->render_target[id].CB_COLOR0_FRAG.u32All);
559 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
560 END_BATCH();
561
562 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
563 BEGIN_BATCH_NO_AUTOSTATE(3);
564 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * id), r700->render_target[id].CB_BLEND0_CONTROL.u32All);
565 END_BATCH();
566 }
567
568 COMMIT_BATCH();
569
570 return GL_TRUE;
571 }
572
573 GLboolean r700SendPSState(context_t *context)
574 {
575 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
576 struct radeon_renderbuffer *rrb;
577 struct radeon_bo * pbo;
578 offset_modifiers offset_mod;
579 BATCH_LOCALS(&context->radeon);
580
581 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
582
583 offset_mod.shift = NO_SHIFT;
584 offset_mod.shiftbits = 0;
585 offset_mod.mask = 0xFFFFFFFF;
586
587 BEGIN_BATCH_NO_AUTOSTATE(3);
588 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
589 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
590 pbo,
591 r700->ps.SQ_PGM_START_PS.u32All,
592 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
593 END_BATCH();
594
595 BEGIN_BATCH_NO_AUTOSTATE(9);
596 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
597 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
598 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
599 END_BATCH();
600
601 COMMIT_BATCH();
602
603 return GL_TRUE;
604 }
605
606 GLboolean r700SendVSState(context_t *context)
607 {
608 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
609 struct radeon_renderbuffer *rrb;
610 struct radeon_bo * pbo;
611 offset_modifiers offset_mod;
612 BATCH_LOCALS(&context->radeon);
613
614 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
615
616 offset_mod.shift = NO_SHIFT;
617 offset_mod.shiftbits = 0;
618 offset_mod.mask = 0xFFFFFFFF;
619
620 BEGIN_BATCH_NO_AUTOSTATE(3);
621 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
622 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
623 pbo,
624 r700->vs.SQ_PGM_START_VS.u32All,
625 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
626 END_BATCH();
627
628 BEGIN_BATCH_NO_AUTOSTATE(6);
629 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
630 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
631 END_BATCH();
632
633 COMMIT_BATCH();
634
635 return GL_TRUE;
636 }
637
638 GLboolean r700SendViewportState(context_t *context, int id)
639 {
640 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
641 struct radeon_renderbuffer *rrb;
642 struct radeon_bo * pbo;
643 offset_modifiers offset_mod;
644 BATCH_LOCALS(&context->radeon);
645
646 if (id > R700_MAX_VIEWPORTS)
647 return GL_FALSE;
648
649 if (!r700->viewport[id].enabled)
650 return GL_FALSE;
651
652 BEGIN_BATCH_NO_AUTOSTATE(16);
653 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
654 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
655 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
656 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
657 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
658 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
659 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
660 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
661 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
662 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
663 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
664 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
665 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
666 END_BATCH();
667
668 COMMIT_BATCH();
669
670 return GL_TRUE;
671 }
672
673 GLboolean r700SendSQConfig(context_t *context)
674 {
675 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
676 BATCH_LOCALS(&context->radeon);
677
678 BEGIN_BATCH_NO_AUTOSTATE(8);
679 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
680 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
681 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
682 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
683 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
684 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
685 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
686 END_BATCH();
687 COMMIT_BATCH();
688
689 return GL_TRUE;
690 }
691