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r600: add support for draw_elements_base_vertex
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30 #include "main/simple_list.h"
31
32 #include "r600_context.h"
33 #include "r600_cmdbuf.h"
34
35 #include "r600_tex.h"
36 #include "r700_oglprog.h"
37 #include "r700_fragprog.h"
38 #include "r700_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
43 {
44 context_t *context = R700_CONTEXT(ctx);
45 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
46
47 struct r700_vertex_program *vp = context->selected_vp;
48
49 struct radeon_bo *bo = NULL;
50 unsigned int i;
51 BATCH_LOCALS(&context->radeon);
52
53 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
54
55 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
56 if (ctx->Texture.Unit[i]._ReallyEnabled) {
57 radeonTexObj *t = r700->textures[i];
58 if (t) {
59 if (!t->image_override) {
60 bo = t->mt->bo;
61 } else {
62 bo = t->bo;
63 }
64 if (bo) {
65
66 r700SyncSurf(context, bo,
67 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
68 0, TC_ACTION_ENA_bit);
69
70 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
71 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
72
73 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
74 { /* vs texture */
75 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
76 }
77 else
78 {
79 R600_OUT_BATCH(i * 7);
80 }
81
82 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
83 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
84 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
85 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
86 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
87 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
88 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
89 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
90 bo,
91 r700->textures[i]->SQ_TEX_RESOURCE2,
92 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
93 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
94 bo,
95 r700->textures[i]->SQ_TEX_RESOURCE3,
96 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
97 END_BATCH();
98 COMMIT_BATCH();
99 }
100 }
101 }
102 }
103 }
104
105 #define SAMPLER_STRIDE 3
106
107 static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
108 {
109 context_t *context = R700_CONTEXT(ctx);
110 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
111 unsigned int i;
112
113 struct r700_vertex_program *vp = context->selected_vp;
114
115 BATCH_LOCALS(&context->radeon);
116 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
117
118 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
119 if (ctx->Texture.Unit[i]._ReallyEnabled) {
120 radeonTexObj *t = r700->textures[i];
121 if (t) {
122 BEGIN_BATCH_NO_AUTOSTATE(5);
123 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
124
125 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
126 { /* vs texture */
127 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * SAMPLER_STRIDE); //work 1
128 }
129 else
130 {
131 R600_OUT_BATCH(i * 3);
132 }
133
134 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
135 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
136 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
137 END_BATCH();
138 COMMIT_BATCH();
139 }
140 }
141 }
142 }
143
144 static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
145 {
146 context_t *context = R700_CONTEXT(ctx);
147 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
148 unsigned int i;
149 BATCH_LOCALS(&context->radeon);
150 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
151
152 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
153 if (ctx->Texture.Unit[i]._ReallyEnabled) {
154 radeonTexObj *t = r700->textures[i];
155 if (t) {
156 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
157 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
158 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
159 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
160 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
161 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
162 END_BATCH();
163 COMMIT_BATCH();
164 }
165 }
166 }
167 }
168
169 extern int getTypeSize(GLenum type);
170 static void r700SetupVTXConstants(GLcontext * ctx,
171 void * pAos,
172 StreamDesc * pStreamDesc)
173 {
174 context_t *context = R700_CONTEXT(ctx);
175 struct radeon_aos * paos = (struct radeon_aos *)pAos;
176 unsigned int nVBsize;
177 BATCH_LOCALS(&context->radeon);
178
179 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
180 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
181 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
182 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
183 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
184
185 if (!paos->bo)
186 return;
187
188 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
189 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
190 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
191 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
192 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
193 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
194 else
195 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
196
197 if(0 == pStreamDesc->stride)
198 {
199 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
200 }
201 else
202 {
203 nVBsize = (paos->count - 1) * pStreamDesc->stride
204 + pStreamDesc->size * getTypeSize(pStreamDesc->type);
205 }
206
207 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
208 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize - 1;
209
210 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
211 SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
212 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
213 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
214 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
215 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
216
217 if(GL_TRUE == pStreamDesc->normalize)
218 {
219 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
220 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
221 }
222 else
223 {
224 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
225 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
226 }
227
228 if(1 == pStreamDesc->_signed)
229 {
230 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
231 }
232
233 SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
234 SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
235 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
236
237 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
238
239 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
240 R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
241 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
242 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
243 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
244 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
245 R600_OUT_BATCH(0);
246 R600_OUT_BATCH(0);
247 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
248 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
249 paos->bo,
250 uSQ_VTX_CONSTANT_WORD0_0,
251 RADEON_GEM_DOMAIN_GTT, 0, 0);
252 END_BATCH();
253 COMMIT_BATCH();
254
255 }
256
257 static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
258 {
259 context_t *context = R700_CONTEXT(ctx);
260 struct r700_vertex_program *vp = context->selected_vp;
261 unsigned int i, j = 0;
262 BATCH_LOCALS(&context->radeon);
263 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
264
265 if (context->radeon.tcl.aos_count == 0)
266 return;
267
268 for(i=0; i<VERT_ATTRIB_MAX; i++) {
269 if(vp->mesa_program->Base.InputsRead & (1 << i))
270 {
271 r700SetupVTXConstants(ctx,
272 (void*)(&context->radeon.tcl.aos[j]),
273 &(context->stream_desc[j]));
274 j++;
275 }
276 }
277 }
278
279 static void r700SetRenderTarget(context_t *context, int id)
280 {
281 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
282 uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM;
283 struct radeon_renderbuffer *rrb;
284 unsigned int nPitchInPixel;
285
286 rrb = radeon_get_colorbuffer(&context->radeon);
287 if (!rrb || !rrb->bo) {
288 return;
289 }
290
291 R600_STATECHANGE(context, cb_target);
292
293 /* color buffer */
294 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
295
296 nPitchInPixel = rrb->pitch/rrb->cpp;
297 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
298 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
299 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
300 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
301 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
302 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
303 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
304
305 switch (rrb->base.Format) {
306 case MESA_FORMAT_RGBA8888:
307 format = COLOR_8_8_8_8;
308 comp_swap = SWAP_STD_REV;
309 number_type = NUMBER_UNORM;
310 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
311 break;
312 case MESA_FORMAT_SIGNED_RGBA8888:
313 format = COLOR_8_8_8_8;
314 comp_swap = SWAP_STD_REV;
315 number_type = NUMBER_SNORM;
316 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
317 break;
318 case MESA_FORMAT_RGBA8888_REV:
319 format = COLOR_8_8_8_8;
320 comp_swap = SWAP_STD;
321 number_type = NUMBER_UNORM;
322 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
323 break;
324 case MESA_FORMAT_SIGNED_RGBA8888_REV:
325 format = COLOR_8_8_8_8;
326 comp_swap = SWAP_STD;
327 number_type = NUMBER_SNORM;
328 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
329 break;
330 case MESA_FORMAT_ARGB8888:
331 case MESA_FORMAT_XRGB8888:
332 format = COLOR_8_8_8_8;
333 comp_swap = SWAP_ALT;
334 number_type = NUMBER_UNORM;
335 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
336 break;
337 case MESA_FORMAT_ARGB8888_REV:
338 case MESA_FORMAT_XRGB8888_REV:
339 format = COLOR_8_8_8_8;
340 comp_swap = SWAP_ALT_REV;
341 number_type = NUMBER_UNORM;
342 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
343 break;
344 case MESA_FORMAT_RGB565:
345 format = COLOR_5_6_5;
346 comp_swap = SWAP_STD_REV;
347 number_type = NUMBER_UNORM;
348 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
349 break;
350 case MESA_FORMAT_RGB565_REV:
351 format = COLOR_5_6_5;
352 comp_swap = SWAP_STD;
353 number_type = NUMBER_UNORM;
354 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
355 break;
356 case MESA_FORMAT_ARGB4444:
357 format = COLOR_4_4_4_4;
358 comp_swap = SWAP_ALT;
359 number_type = NUMBER_UNORM;
360 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
361 break;
362 case MESA_FORMAT_ARGB4444_REV:
363 format = COLOR_4_4_4_4;
364 comp_swap = SWAP_ALT_REV;
365 number_type = NUMBER_UNORM;
366 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
367 break;
368 case MESA_FORMAT_ARGB1555:
369 format = COLOR_1_5_5_5;
370 comp_swap = SWAP_ALT;
371 number_type = NUMBER_UNORM;
372 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
373 break;
374 case MESA_FORMAT_ARGB1555_REV:
375 format = COLOR_1_5_5_5;
376 comp_swap = SWAP_ALT_REV;
377 number_type = NUMBER_UNORM;
378 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
379 break;
380 case MESA_FORMAT_AL88:
381 format = COLOR_8_8;
382 comp_swap = SWAP_STD;
383 number_type = NUMBER_UNORM;
384 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
385 break;
386 case MESA_FORMAT_AL88_REV:
387 format = COLOR_8_8;
388 comp_swap = SWAP_STD_REV;
389 number_type = NUMBER_UNORM;
390 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
391 break;
392 case MESA_FORMAT_RGB332:
393 format = COLOR_3_3_2;
394 comp_swap = SWAP_STD_REV;
395 number_type = NUMBER_UNORM;
396 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
397 break;
398 case MESA_FORMAT_A8:
399 format = COLOR_8;
400 comp_swap = SWAP_ALT_REV;
401 number_type = NUMBER_UNORM;
402 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
403 break;
404 case MESA_FORMAT_I8:
405 case MESA_FORMAT_CI8:
406 format = COLOR_8;
407 comp_swap = SWAP_STD;
408 number_type = NUMBER_UNORM;
409 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
410 break;
411 case MESA_FORMAT_L8:
412 format = COLOR_8;
413 comp_swap = SWAP_ALT;
414 number_type = NUMBER_UNORM;
415 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
416 break;
417 case MESA_FORMAT_RGBA_FLOAT32:
418 format = COLOR_32_32_32_32_FLOAT;
419 comp_swap = SWAP_STD_REV;
420 number_type = NUMBER_FLOAT;
421 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
422 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
423 break;
424 case MESA_FORMAT_RGBA_FLOAT16:
425 format = COLOR_16_16_16_16_FLOAT;
426 comp_swap = SWAP_STD_REV;
427 number_type = NUMBER_FLOAT;
428 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
429 break;
430 case MESA_FORMAT_ALPHA_FLOAT32:
431 format = COLOR_32_FLOAT;
432 comp_swap = SWAP_ALT_REV;
433 number_type = NUMBER_FLOAT;
434 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
435 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
436 break;
437 case MESA_FORMAT_ALPHA_FLOAT16:
438 format = COLOR_16_FLOAT;
439 comp_swap = SWAP_ALT_REV;
440 number_type = NUMBER_FLOAT;
441 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
442 break;
443 case MESA_FORMAT_LUMINANCE_FLOAT32:
444 format = COLOR_32_FLOAT;
445 comp_swap = SWAP_ALT;
446 number_type = NUMBER_FLOAT;
447 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
448 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
449 break;
450 case MESA_FORMAT_LUMINANCE_FLOAT16:
451 format = COLOR_16_FLOAT;
452 comp_swap = SWAP_ALT;
453 number_type = NUMBER_FLOAT;
454 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
455 break;
456 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
457 format = COLOR_32_32_FLOAT;
458 comp_swap = SWAP_ALT_REV;
459 number_type = NUMBER_FLOAT;
460 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
461 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
462 break;
463 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
464 format = COLOR_16_16_FLOAT;
465 comp_swap = SWAP_ALT_REV;
466 number_type = NUMBER_FLOAT;
467 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
468 break;
469 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
470 format = COLOR_32_FLOAT;
471 comp_swap = SWAP_STD;
472 number_type = NUMBER_FLOAT;
473 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
474 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
475 break;
476 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
477 format = COLOR_16_FLOAT;
478 comp_swap = SWAP_STD;
479 number_type = NUMBER_UNORM;
480 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
481 break;
482 case MESA_FORMAT_X8_Z24:
483 case MESA_FORMAT_S8_Z24:
484 format = COLOR_8_24;
485 comp_swap = SWAP_STD;
486 number_type = NUMBER_UNORM;
487 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
488 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
489 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
490 break;
491 case MESA_FORMAT_Z24_S8:
492 format = COLOR_24_8;
493 comp_swap = SWAP_STD;
494 number_type = NUMBER_UNORM;
495 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
496 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
497 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
498 break;
499 case MESA_FORMAT_Z16:
500 format = COLOR_16;
501 comp_swap = SWAP_STD;
502 number_type = NUMBER_UNORM;
503 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
504 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
505 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
506 break;
507 case MESA_FORMAT_Z32:
508 format = COLOR_32;
509 comp_swap = SWAP_STD;
510 number_type = NUMBER_UNORM;
511 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
512 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
513 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
514 break;
515 case MESA_FORMAT_SARGB8:
516 format = COLOR_8_8_8_8;
517 comp_swap = SWAP_ALT;
518 number_type = NUMBER_SRGB;
519 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
520 break;
521 case MESA_FORMAT_SLA8:
522 format = COLOR_8_8;
523 comp_swap = SWAP_ALT_REV;
524 number_type = NUMBER_SRGB;
525 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
526 break;
527 case MESA_FORMAT_SL8:
528 format = COLOR_8;
529 comp_swap = SWAP_ALT_REV;
530 number_type = NUMBER_SRGB;
531 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
532 break;
533 default:
534 _mesa_problem(context->radeon.glCtx, "unexpected format in r700SetRenderTarget()");
535 break;
536 }
537
538 /* must be 0 on r7xx */
539 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
540 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
541
542 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, format,
543 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
544 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, comp_swap,
545 COMP_SWAP_shift, COMP_SWAP_mask);
546 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, number_type,
547 NUMBER_TYPE_shift, NUMBER_TYPE_mask);
548 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
549
550 r700->render_target[id].enabled = GL_TRUE;
551 }
552
553 static void r700SetDepthTarget(context_t *context)
554 {
555 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
556
557 struct radeon_renderbuffer *rrb;
558 unsigned int nPitchInPixel;
559
560 rrb = radeon_get_depthbuffer(&context->radeon);
561 if (!rrb)
562 return;
563
564 R600_STATECHANGE(context, db_target);
565
566 /* depth buf */
567 r700->DB_DEPTH_SIZE.u32All = 0;
568 r700->DB_DEPTH_BASE.u32All = 0;
569 r700->DB_DEPTH_INFO.u32All = 0;
570 r700->DB_DEPTH_VIEW.u32All = 0;
571
572 nPitchInPixel = rrb->pitch/rrb->cpp;
573
574 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
575 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
576 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
577 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
578
579 if(4 == rrb->cpp)
580 {
581 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
582 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
583 }
584 else
585 {
586 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
587 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
588 }
589 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
590 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
591 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
592 }
593
594 static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
595 {
596 context_t *context = R700_CONTEXT(ctx);
597 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
598 struct radeon_renderbuffer *rrb;
599 BATCH_LOCALS(&context->radeon);
600 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
601
602 rrb = radeon_get_depthbuffer(&context->radeon);
603 if (!rrb || !rrb->bo) {
604 return;
605 }
606
607 r700SetDepthTarget(context);
608
609 BEGIN_BATCH_NO_AUTOSTATE(7 + 2);
610 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
611 R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
612 R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
613 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1);
614 R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
615 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
616 rrb->bo,
617 r700->DB_DEPTH_BASE.u32All,
618 0, RADEON_GEM_DOMAIN_VRAM, 0);
619 END_BATCH();
620 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
621 R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1);
622 R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
623 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All,
624 rrb->bo,
625 r700->DB_DEPTH_INFO.u32All,
626 0, RADEON_GEM_DOMAIN_VRAM, 0);
627 END_BATCH();
628
629 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
630 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
631 BEGIN_BATCH_NO_AUTOSTATE(2);
632 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
633 R600_OUT_BATCH(1 << 0);
634 END_BATCH();
635 }
636
637 COMMIT_BATCH();
638
639 }
640
641 static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
642 {
643 context_t *context = R700_CONTEXT(ctx);
644 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
645 struct radeon_renderbuffer *rrb;
646 BATCH_LOCALS(&context->radeon);
647 int id = 0;
648 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
649
650 rrb = radeon_get_colorbuffer(&context->radeon);
651 if (!rrb || !rrb->bo) {
652 return;
653 }
654
655 r700SetRenderTarget(context, 0);
656
657 if (id > R700_MAX_RENDER_TARGETS)
658 return;
659
660 if (!r700->render_target[id].enabled)
661 return;
662
663 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
664 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
665 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
666 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
667 rrb->bo,
668 r700->render_target[id].CB_COLOR0_BASE.u32All,
669 0, RADEON_GEM_DOMAIN_VRAM, 0);
670 END_BATCH();
671
672 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
673 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
674 BEGIN_BATCH_NO_AUTOSTATE(2);
675 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
676 R600_OUT_BATCH((2 << id));
677 END_BATCH();
678 }
679 /* Set CMASK & TILE buffer to the offset of color buffer as
680 * we don't use those this shouldn't cause any issue and we
681 * then have a valid cmd stream
682 */
683 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
684 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
685 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
686 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All,
687 rrb->bo,
688 r700->render_target[id].CB_COLOR0_TILE.u32All,
689 0, RADEON_GEM_DOMAIN_VRAM, 0);
690 END_BATCH();
691 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
692 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
693 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All);
694 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_FRAG.u32All,
695 rrb->bo,
696 r700->render_target[id].CB_COLOR0_FRAG.u32All,
697 0, RADEON_GEM_DOMAIN_VRAM, 0);
698 END_BATCH();
699
700 BEGIN_BATCH_NO_AUTOSTATE(9);
701 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
702 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
703 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
704 END_BATCH();
705
706 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
707 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
708 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_INFO.u32All,
709 rrb->bo,
710 r700->render_target[id].CB_COLOR0_INFO.u32All,
711 0, RADEON_GEM_DOMAIN_VRAM, 0);
712
713 END_BATCH();
714
715 COMMIT_BATCH();
716
717 }
718
719 static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
720 {
721 context_t *context = R700_CONTEXT(ctx);
722 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
723 struct radeon_bo * pbo;
724 BATCH_LOCALS(&context->radeon);
725 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
726
727 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
728
729 if (!pbo)
730 return;
731
732 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
733
734 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
735 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
736 R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
737 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
738 pbo,
739 r700->ps.SQ_PGM_START_PS.u32All,
740 RADEON_GEM_DOMAIN_GTT, 0, 0);
741 END_BATCH();
742
743 BEGIN_BATCH_NO_AUTOSTATE(9);
744 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
745 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
746 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
747 END_BATCH();
748
749 BEGIN_BATCH_NO_AUTOSTATE(3);
750 R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
751 END_BATCH();
752
753 COMMIT_BATCH();
754
755 }
756
757 static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
758 {
759 context_t *context = R700_CONTEXT(ctx);
760 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
761 struct radeon_bo * pbo;
762 BATCH_LOCALS(&context->radeon);
763 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
764
765 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
766
767 if (!pbo)
768 return;
769
770 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
771
772 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
773 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
774 R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
775 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
776 pbo,
777 r700->vs.SQ_PGM_START_VS.u32All,
778 RADEON_GEM_DOMAIN_GTT, 0, 0);
779 END_BATCH();
780
781 BEGIN_BATCH_NO_AUTOSTATE(6);
782 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
783 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
784 END_BATCH();
785
786 BEGIN_BATCH_NO_AUTOSTATE(3);
787 R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
788 //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
789 END_BATCH();
790
791 COMMIT_BATCH();
792 }
793
794 static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
795 {
796 context_t *context = R700_CONTEXT(ctx);
797 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
798 struct radeon_bo * pbo;
799 BATCH_LOCALS(&context->radeon);
800 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
801
802 /* XXX fixme
803 * R6xx chips require a FS be emitted, even if it's not used.
804 * since we aren't using FS yet, just send the VS address to make
805 * the kernel command checker happy
806 */
807 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
808 r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
809 r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
810 r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
811 /* XXX */
812
813 if (!pbo)
814 return;
815
816 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
817
818 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
819 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
820 R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
821 R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
822 pbo,
823 r700->fs.SQ_PGM_START_FS.u32All,
824 RADEON_GEM_DOMAIN_GTT, 0, 0);
825 END_BATCH();
826
827 BEGIN_BATCH_NO_AUTOSTATE(6);
828 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
829 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
830 END_BATCH();
831
832 COMMIT_BATCH();
833
834 }
835
836 static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
837 {
838 context_t *context = R700_CONTEXT(ctx);
839 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
840 BATCH_LOCALS(&context->radeon);
841 int id = 0;
842 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
843
844 if (id > R700_MAX_VIEWPORTS)
845 return;
846
847 if (!r700->viewport[id].enabled)
848 return;
849
850 BEGIN_BATCH_NO_AUTOSTATE(16);
851 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
852 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
853 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
854 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
855 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
856 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
857 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
858 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
859 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
860 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
861 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
862 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
863 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
864 END_BATCH();
865
866 COMMIT_BATCH();
867
868 }
869
870 static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
871 {
872 context_t *context = R700_CONTEXT(ctx);
873 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
874 BATCH_LOCALS(&context->radeon);
875 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
876
877 BEGIN_BATCH_NO_AUTOSTATE(34);
878 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
879 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
880 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
881 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
882 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
883 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
884 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
885
886 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
887 R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
888 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
889 R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
890 R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
891
892 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
893 R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
894 R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
895 R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
896 R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
897 R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
898 R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
899 R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
900 R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
901 R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
902 END_BATCH();
903
904 COMMIT_BATCH();
905 }
906
907 static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
908 {
909 context_t *context = R700_CONTEXT(ctx);
910 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
911 BATCH_LOCALS(&context->radeon);
912 int i;
913 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
914
915 for (i = 0; i < R700_MAX_UCP; i++) {
916 if (r700->ucp[i].enabled) {
917 BEGIN_BATCH_NO_AUTOSTATE(6);
918 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
919 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
920 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
921 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
922 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
923 END_BATCH();
924 COMMIT_BATCH();
925 }
926 }
927 }
928
929 static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
930 {
931 context_t *context = R700_CONTEXT(ctx);
932 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
933 BATCH_LOCALS(&context->radeon);
934 unsigned int ui;
935 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
936
937 BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
938
939 R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
940 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
941 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
942 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
943 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
944 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
945 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
946 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
947 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
948 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
949 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
950 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
951 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
952 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
953 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
954 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
955 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
956 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
957 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
958 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
959 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
960 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
961 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
962 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
963 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
964 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
965 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
966 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
967 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
968 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
969 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
970 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
971 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
972
973 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
974 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
975 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
976 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
977 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
978 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
979 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
980 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
981 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
982 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
983 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
984
985 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
986 R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
987 R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
988 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
989 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
990 R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
991 R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
992 R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
993 R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
994 R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
995
996 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
997 for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
998 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
999
1000 END_BATCH();
1001 COMMIT_BATCH();
1002 }
1003
1004 static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
1005 {
1006 context_t *context = R700_CONTEXT(ctx);
1007 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1008 BATCH_LOCALS(&context->radeon);
1009 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1010
1011 BEGIN_BATCH_NO_AUTOSTATE(41);
1012
1013 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1014 R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
1015 R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
1016 R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
1017 R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
1018
1019 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1020 R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
1021 R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
1022 R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
1023 R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
1024 R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
1025 R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
1026 R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
1027 R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
1028 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
1029 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
1030 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
1031 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
1032 R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
1033
1034 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
1035 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
1036 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
1037 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
1038
1039 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1040 R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
1041 R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
1042 R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
1043
1044 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
1045
1046 END_BATCH();
1047 COMMIT_BATCH();
1048 }
1049
1050 static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
1051 {
1052 context_t *context = R700_CONTEXT(ctx);
1053 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1054 BATCH_LOCALS(&context->radeon);
1055 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1056
1057 BEGIN_BATCH_NO_AUTOSTATE(9);
1058 R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
1059 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
1060 R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
1061 END_BATCH();
1062 COMMIT_BATCH();
1063 }
1064
1065 static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
1066 {
1067 context_t *context = R700_CONTEXT(ctx);
1068 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1069 BATCH_LOCALS(&context->radeon);
1070 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1071
1072 BEGIN_BATCH_NO_AUTOSTATE(17);
1073
1074 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
1075 R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
1076 R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
1077
1078 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
1079 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
1080
1081 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
1082 R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
1083 R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
1084
1085 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
1086
1087 END_BATCH();
1088 COMMIT_BATCH();
1089 }
1090
1091 static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
1092 {
1093 context_t *context = R700_CONTEXT(ctx);
1094 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1095 BATCH_LOCALS(&context->radeon);
1096
1097 BEGIN_BATCH_NO_AUTOSTATE(4);
1098 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
1099 R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
1100 R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
1101 END_BATCH();
1102 COMMIT_BATCH();
1103 }
1104
1105 static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
1106 {
1107 context_t *context = R700_CONTEXT(ctx);
1108 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1109 BATCH_LOCALS(&context->radeon);
1110 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1111
1112 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1113 BEGIN_BATCH_NO_AUTOSTATE(11);
1114 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
1115 R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
1116 R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
1117 R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
1118 R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
1119 R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
1120 R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
1121 R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
1122 R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
1123 END_BATCH();
1124 }
1125
1126 BEGIN_BATCH_NO_AUTOSTATE(7);
1127 R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
1128 R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
1129 R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
1130 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
1131 END_BATCH();
1132 COMMIT_BATCH();
1133 }
1134
1135 static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
1136 {
1137 context_t *context = R700_CONTEXT(ctx);
1138 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1139 BATCH_LOCALS(&context->radeon);
1140
1141 BEGIN_BATCH_NO_AUTOSTATE(6);
1142 R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
1143 R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
1144 R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
1145 R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
1146 R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
1147 END_BATCH();
1148 COMMIT_BATCH();
1149 }
1150
1151 static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
1152 {
1153 context_t *context = R700_CONTEXT(ctx);
1154 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1155 BATCH_LOCALS(&context->radeon);
1156 unsigned int ui;
1157 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1158
1159 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1160 BEGIN_BATCH_NO_AUTOSTATE(3);
1161 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
1162 END_BATCH();
1163 }
1164
1165 BEGIN_BATCH_NO_AUTOSTATE(3);
1166 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
1167 END_BATCH();
1168
1169 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1170 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
1171 if (r700->render_target[ui].enabled) {
1172 BEGIN_BATCH_NO_AUTOSTATE(3);
1173 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
1174 r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
1175 END_BATCH();
1176 }
1177 }
1178 }
1179
1180 COMMIT_BATCH();
1181 }
1182
1183 static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
1184 {
1185 context_t *context = R700_CONTEXT(ctx);
1186 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1187 BATCH_LOCALS(&context->radeon);
1188 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1189
1190 BEGIN_BATCH_NO_AUTOSTATE(6);
1191 R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
1192 R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
1193 R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
1194 R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
1195 R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
1196 END_BATCH();
1197 COMMIT_BATCH();
1198 }
1199
1200 static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
1201 {
1202 context_t *context = R700_CONTEXT(ctx);
1203 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1204 BATCH_LOCALS(&context->radeon);
1205
1206 BEGIN_BATCH_NO_AUTOSTATE(9);
1207 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
1208 R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
1209 R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
1210 R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
1211 R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
1212 R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
1213 END_BATCH();
1214 COMMIT_BATCH();
1215
1216 }
1217
1218 static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
1219 {
1220 context_t *context = R700_CONTEXT(ctx);
1221 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1222 BATCH_LOCALS(&context->radeon);
1223
1224 BEGIN_BATCH_NO_AUTOSTATE(10);
1225 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
1226 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
1227 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
1228 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1229 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
1230 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
1231 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
1232 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
1233 END_BATCH();
1234 COMMIT_BATCH();
1235
1236 }
1237
1238 static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
1239 {
1240 context_t *context = R700_CONTEXT(ctx);
1241 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1242 BATCH_LOCALS(&context->radeon);
1243 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1244
1245 BEGIN_BATCH_NO_AUTOSTATE(12);
1246 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
1247 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
1248 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
1249 R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
1250 END_BATCH();
1251 COMMIT_BATCH();
1252 }
1253
1254 static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
1255 {
1256 context_t *context = R700_CONTEXT(ctx);
1257 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1258 BATCH_LOCALS(&context->radeon);
1259
1260 BEGIN_BATCH_NO_AUTOSTATE(6);
1261 R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
1262 R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
1263 R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
1264 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
1265 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
1266 END_BATCH();
1267 COMMIT_BATCH();
1268 }
1269
1270 static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
1271 {
1272 context_t *context = R700_CONTEXT(ctx);
1273 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1274 BATCH_LOCALS(&context->radeon);
1275 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1276
1277 BEGIN_BATCH_NO_AUTOSTATE(22);
1278 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1279 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
1280 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
1281
1282 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
1283 R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
1284 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
1285 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
1286 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
1287 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
1288 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
1289 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
1290 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
1291 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
1292 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
1293 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
1294 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
1295
1296 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1297 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
1298 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
1299 END_BATCH();
1300 COMMIT_BATCH();
1301 }
1302
1303 static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
1304 {
1305 context_t *context = R700_CONTEXT(ctx);
1306 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1307 BATCH_LOCALS(&context->radeon);
1308 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1309
1310 BEGIN_BATCH_NO_AUTOSTATE(15);
1311 R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
1312 R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
1313 R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
1314 R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
1315 R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
1316 END_BATCH();
1317 COMMIT_BATCH();
1318 }
1319
1320 static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
1321 {
1322 context_t *context = R700_CONTEXT(ctx);
1323 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1324 BATCH_LOCALS(&context->radeon);
1325
1326 BEGIN_BATCH_NO_AUTOSTATE(12);
1327 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
1328 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
1329 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
1330 R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
1331 END_BATCH();
1332 COMMIT_BATCH();
1333 }
1334
1335 static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1336 {
1337 context_t *context = R700_CONTEXT(ctx);
1338 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1339 int i;
1340 BATCH_LOCALS(&context->radeon);
1341
1342 if (r700->ps.num_consts == 0)
1343 return;
1344
1345 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
1346 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
1347 /* assembler map const from very beginning. */
1348 R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
1349 for (i = 0; i < r700->ps.num_consts; i++) {
1350 R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
1351 R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
1352 R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
1353 R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
1354 }
1355 END_BATCH();
1356 COMMIT_BATCH();
1357 }
1358
1359 static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1360 {
1361 context_t *context = R700_CONTEXT(ctx);
1362 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1363 int i;
1364 BATCH_LOCALS(&context->radeon);
1365 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1366
1367 if (r700->vs.num_consts == 0)
1368 return;
1369
1370 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
1371 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
1372 /* assembler map const from very beginning. */
1373 R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
1374 for (i = 0; i < r700->vs.num_consts; i++) {
1375 R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
1376 R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
1377 R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
1378 R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
1379 }
1380 END_BATCH();
1381 COMMIT_BATCH();
1382 }
1383
1384 static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
1385 {
1386 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1387 struct radeon_query_object *query = radeon->query.current;
1388 BATCH_LOCALS(radeon);
1389 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1390
1391 /* clear the buffer */
1392 radeon_bo_map(query->bo, GL_FALSE);
1393 memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
1394 radeon_bo_unmap(query->bo);
1395
1396 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
1397 query->bo,
1398 0, RADEON_GEM_DOMAIN_GTT);
1399
1400 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
1401 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
1402 R600_OUT_BATCH(ZPASS_DONE);
1403 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
1404 R600_OUT_BATCH(0x00000000);
1405 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
1406 END_BATCH();
1407 query->emitted_begin = GL_TRUE;
1408 }
1409
1410 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
1411 {
1412 return atom->cmd_size;
1413 }
1414
1415 static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
1416 {
1417 context_t *context = R700_CONTEXT(ctx);
1418 int count = 7;
1419
1420 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1421 count += 11;
1422 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1423
1424 return count;
1425 }
1426
1427 static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
1428 {
1429 context_t *context = R700_CONTEXT(ctx);
1430 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1431 unsigned int ui;
1432 int count = 3;
1433
1434 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1435 count += 3;
1436
1437 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1438 /* targets are enabled in r700SetRenderTarget but state
1439 size is calculated before that. Until MRT's are done
1440 hardcode target0 as enabled. */
1441 count += 3;
1442 for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) {
1443 if (r700->render_target[ui].enabled)
1444 count += 3;
1445 }
1446 }
1447 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1448
1449 return count;
1450 }
1451
1452 static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
1453 {
1454 context_t *context = R700_CONTEXT(ctx);
1455 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1456 int i;
1457 int count = 0;
1458
1459 for (i = 0; i < R700_MAX_UCP; i++) {
1460 if (r700->ucp[i].enabled)
1461 count += 6;
1462 }
1463 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1464 return count;
1465 }
1466
1467 static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
1468 {
1469 context_t *context = R700_CONTEXT(ctx);
1470 int count = context->radeon.tcl.aos_count * 18;
1471
1472 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1473 return count;
1474 }
1475
1476 static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
1477 {
1478 context_t *context = R700_CONTEXT(ctx);
1479 unsigned int i, count = 0;
1480 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1481
1482 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
1483 if (ctx->Texture.Unit[i]._ReallyEnabled) {
1484 radeonTexObj *t = r700->textures[i];
1485 if (t)
1486 count++;
1487 }
1488 }
1489 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1490 return count * 31;
1491 }
1492
1493 static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1494 {
1495 context_t *context = R700_CONTEXT(ctx);
1496 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1497 int count = r700->ps.num_consts * 4;
1498
1499 if (count)
1500 count += 2;
1501 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1502
1503 return count;
1504 }
1505
1506 static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1507 {
1508 context_t *context = R700_CONTEXT(ctx);
1509 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1510 int count = r700->vs.num_consts * 4;
1511
1512 if (count)
1513 count += 2;
1514 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1515
1516 return count;
1517 }
1518
1519 static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
1520 {
1521 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1522 struct radeon_query_object *query = radeon->query.current;
1523 int count;
1524
1525 if (!query || query->emitted_begin)
1526 count = 0;
1527 else
1528 count = atom->cmd_size;
1529 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1530 return count;
1531 }
1532
1533 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
1534 do { \
1535 context->atoms.ATOM.cmd_size = (SZ); \
1536 context->atoms.ATOM.cmd = NULL; \
1537 context->atoms.ATOM.name = #ATOM; \
1538 context->atoms.ATOM.idx = 0; \
1539 context->atoms.ATOM.check = check_##CHK; \
1540 context->atoms.ATOM.dirty = GL_FALSE; \
1541 context->atoms.ATOM.emit = (EMIT); \
1542 context->radeon.hw.max_state_size += (SZ); \
1543 insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1544 } while (0)
1545
1546 static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
1547 {
1548 radeon->query.queryobj.cmd_size = (SZ);
1549 radeon->query.queryobj.cmd = NULL;
1550 radeon->query.queryobj.name = "queryobj";
1551 radeon->query.queryobj.idx = 0;
1552 radeon->query.queryobj.check = check_queryobj;
1553 radeon->query.queryobj.dirty = GL_FALSE;
1554 radeon->query.queryobj.emit = r700SendQueryBegin;
1555 radeon->hw.max_state_size += (SZ);
1556 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
1557 }
1558
1559 void r600InitAtoms(context_t *context)
1560 {
1561 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1562 context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1563
1564 /* Setup the atom linked list */
1565 make_empty_list(&context->radeon.hw.atomlist);
1566 context->radeon.hw.atomlist.name = "atom-list";
1567
1568 ALLOC_STATE(sq, always, 34, r700SendSQConfig);
1569 ALLOC_STATE(db, always, 17, r700SendDBState);
1570 ALLOC_STATE(stencil, always, 4, r700SendStencilState);
1571 ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState);
1572 ALLOC_STATE(sc, always, 15, r700SendSCState);
1573 ALLOC_STATE(scissor, always, 22, r700SendScissorState);
1574 ALLOC_STATE(aa, always, 12, r700SendAAState);
1575 ALLOC_STATE(cl, always, 12, r700SendCLState);
1576 ALLOC_STATE(gb, always, 6, r700SendGBState);
1577 ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
1578 ALLOC_STATE(su, always, 9, r700SendSUState);
1579 ALLOC_STATE(poly, always, 10, r700SendPolyState);
1580 ALLOC_STATE(cb, cb, 18, r700SendCBState);
1581 ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
1582 ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState);
1583 ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
1584 ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
1585 ALLOC_STATE(sx, always, 9, r700SendSXState);
1586 ALLOC_STATE(vgt, always, 41, r700SendVGTState);
1587 ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
1588 ALLOC_STATE(vpt, always, 16, r700SendViewportState);
1589 ALLOC_STATE(fs, always, 18, r700SendFSState);
1590 ALLOC_STATE(vs, always, 21, r700SendVSState);
1591 ALLOC_STATE(ps, always, 24, r700SendPSState);
1592 ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
1593 ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
1594 ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState);
1595 ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
1596 ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
1597 ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
1598 r600_init_query_stateobj(&context->radeon, 6 * 2);
1599
1600 context->radeon.hw.is_dirty = GL_TRUE;
1601 context->radeon.hw.all_dirty = GL_TRUE;
1602 }