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Merge commit 'nha/r300-compiler-gallium'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "r700_state.h"
35 #include "r600_tex.h"
36 #include "r700_oglprog.h"
37 #include "r700_fragprog.h"
38 #include "r700_vertprog.h"
39 #include "r700_ioctl.h"
40
41 #include "radeon_mipmap_tree.h"
42
43 #define LINK_STATES(reg) \
44 do \
45 { \
46 pStateListWork->puiValue = (unsigned int*)&(r700->reg); \
47 pStateListWork->unOffset = mm##reg - ASIC_CONTEXT_BASE_INDEX; \
48 pStateListWork->pNext = pStateListWork + 1; \
49 pStateListWork++; \
50 }while(0)
51
52 GLboolean r700InitChipObject(context_t *context)
53 {
54 ContextState * pStateListWork;
55
56 R700_CHIP_CONTEXT *r700 = &context->hw;
57
58 /* init state list */
59 r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int));
60 pStateListWork = r700->pStateList;
61
62 // misc
63 LINK_STATES(TA_CNTL_AUX);
64 LINK_STATES(VC_ENHANCE);
65 LINK_STATES(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ);
66 LINK_STATES(DB_DEBUG);
67 LINK_STATES(DB_WATERMARKS);
68
69 // SC
70 LINK_STATES(PA_SC_SCREEN_SCISSOR_TL);
71 LINK_STATES(PA_SC_SCREEN_SCISSOR_BR);
72 LINK_STATES(PA_SC_WINDOW_OFFSET);
73 LINK_STATES(PA_SC_WINDOW_SCISSOR_TL);
74 LINK_STATES(PA_SC_WINDOW_SCISSOR_BR);
75 LINK_STATES(PA_SC_CLIPRECT_RULE);
76 LINK_STATES(PA_SC_CLIPRECT_0_TL);
77 LINK_STATES(PA_SC_CLIPRECT_0_BR);
78 LINK_STATES(PA_SC_CLIPRECT_1_TL);
79 LINK_STATES(PA_SC_CLIPRECT_1_BR);
80 LINK_STATES(PA_SC_CLIPRECT_2_TL);
81 LINK_STATES(PA_SC_CLIPRECT_2_BR);
82 LINK_STATES(PA_SC_CLIPRECT_3_TL);
83 LINK_STATES(PA_SC_CLIPRECT_3_BR);
84 LINK_STATES(PA_SC_EDGERULE);
85 LINK_STATES(PA_SC_GENERIC_SCISSOR_TL);
86 LINK_STATES(PA_SC_GENERIC_SCISSOR_BR);
87 LINK_STATES(PA_SC_LINE_STIPPLE);
88 LINK_STATES(PA_SC_MPASS_PS_CNTL);
89 LINK_STATES(PA_SC_MODE_CNTL);
90 LINK_STATES(PA_SC_LINE_CNTL);
91 LINK_STATES(PA_SC_AA_CONFIG);
92 LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX);
93 LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX);
94 LINK_STATES(PA_SC_AA_MASK);
95
96 // SU
97 LINK_STATES(PA_SU_POINT_SIZE);
98 LINK_STATES(PA_SU_POINT_MINMAX);
99 LINK_STATES(PA_SU_LINE_CNTL);
100 LINK_STATES(PA_SU_SC_MODE_CNTL);
101 LINK_STATES(PA_SU_VTX_CNTL);
102 LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL);
103 LINK_STATES(PA_SU_POLY_OFFSET_CLAMP);
104 LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE);
105 LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET);
106 LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE);
107 LINK_STATES(PA_SU_POLY_OFFSET_BACK_OFFSET);
108
109 // CL
110 LINK_STATES(PA_CL_CLIP_CNTL);
111 LINK_STATES(PA_CL_VTE_CNTL);
112 LINK_STATES(PA_CL_VS_OUT_CNTL);
113 LINK_STATES(PA_CL_NANINF_CNTL);
114 LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ);
115 LINK_STATES(PA_CL_GB_VERT_DISC_ADJ);
116 LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ);
117 LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ);
118
119 // CB
120 LINK_STATES(CB_CLEAR_RED_R6XX);
121 LINK_STATES(CB_CLEAR_GREEN_R6XX);
122 LINK_STATES(CB_CLEAR_BLUE_R6XX);
123 LINK_STATES(CB_CLEAR_ALPHA_R6XX);
124 LINK_STATES(CB_TARGET_MASK);
125 LINK_STATES(CB_SHADER_MASK);
126 LINK_STATES(CB_BLEND_RED);
127 LINK_STATES(CB_BLEND_GREEN);
128 LINK_STATES(CB_BLEND_BLUE);
129 LINK_STATES(CB_BLEND_ALPHA);
130 LINK_STATES(CB_FOG_RED_R6XX);
131 LINK_STATES(CB_FOG_GREEN_R6XX);
132 LINK_STATES(CB_FOG_BLUE_R6XX);
133 LINK_STATES(CB_SHADER_CONTROL);
134 LINK_STATES(CB_COLOR_CONTROL);
135 LINK_STATES(CB_CLRCMP_CONTROL);
136 LINK_STATES(CB_CLRCMP_SRC);
137 LINK_STATES(CB_CLRCMP_DST);
138 LINK_STATES(CB_CLRCMP_MSK);
139 LINK_STATES(CB_BLEND_CONTROL);
140
141 // SX
142 LINK_STATES(SX_MISC);
143 LINK_STATES(SX_ALPHA_TEST_CONTROL);
144 LINK_STATES(SX_ALPHA_REF);
145
146 // VGT
147 LINK_STATES(VGT_MAX_VTX_INDX);
148 LINK_STATES(VGT_MIN_VTX_INDX);
149 LINK_STATES(VGT_INDX_OFFSET);
150 LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX);
151 LINK_STATES(VGT_OUTPUT_PATH_CNTL);
152 LINK_STATES(VGT_HOS_CNTL);
153 LINK_STATES(VGT_HOS_MAX_TESS_LEVEL);
154 LINK_STATES(VGT_HOS_MIN_TESS_LEVEL);
155 LINK_STATES(VGT_HOS_REUSE_DEPTH);
156 LINK_STATES(VGT_GROUP_PRIM_TYPE);
157 LINK_STATES(VGT_GROUP_FIRST_DECR);
158 LINK_STATES(VGT_GROUP_DECR);
159 LINK_STATES(VGT_GROUP_VECT_0_CNTL);
160 LINK_STATES(VGT_GROUP_VECT_1_CNTL);
161 LINK_STATES(VGT_GROUP_VECT_0_FMT_CNTL);
162 LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL);
163 LINK_STATES(VGT_GS_MODE);
164 LINK_STATES(VGT_PRIMITIVEID_EN);
165 LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN);
166 LINK_STATES(VGT_INSTANCE_STEP_RATE_0);
167 LINK_STATES(VGT_INSTANCE_STEP_RATE_1);
168 LINK_STATES(VGT_STRMOUT_EN);
169 LINK_STATES(VGT_REUSE_OFF);
170 LINK_STATES(VGT_VTX_CNT_EN);
171 LINK_STATES(VGT_STRMOUT_BUFFER_EN);
172
173 LINK_STATES(SQ_VTX_SEMANTIC_0);
174 LINK_STATES(SQ_VTX_SEMANTIC_1);
175 LINK_STATES(SQ_VTX_SEMANTIC_2);
176 LINK_STATES(SQ_VTX_SEMANTIC_3);
177 LINK_STATES(SQ_VTX_SEMANTIC_4);
178 LINK_STATES(SQ_VTX_SEMANTIC_5);
179 LINK_STATES(SQ_VTX_SEMANTIC_6);
180 LINK_STATES(SQ_VTX_SEMANTIC_7);
181 LINK_STATES(SQ_VTX_SEMANTIC_8);
182 LINK_STATES(SQ_VTX_SEMANTIC_9);
183 LINK_STATES(SQ_VTX_SEMANTIC_10);
184 LINK_STATES(SQ_VTX_SEMANTIC_11);
185 LINK_STATES(SQ_VTX_SEMANTIC_12);
186 LINK_STATES(SQ_VTX_SEMANTIC_13);
187 LINK_STATES(SQ_VTX_SEMANTIC_14);
188 LINK_STATES(SQ_VTX_SEMANTIC_15);
189 LINK_STATES(SQ_VTX_SEMANTIC_16);
190 LINK_STATES(SQ_VTX_SEMANTIC_17);
191 LINK_STATES(SQ_VTX_SEMANTIC_18);
192 LINK_STATES(SQ_VTX_SEMANTIC_19);
193 LINK_STATES(SQ_VTX_SEMANTIC_20);
194 LINK_STATES(SQ_VTX_SEMANTIC_21);
195 LINK_STATES(SQ_VTX_SEMANTIC_22);
196 LINK_STATES(SQ_VTX_SEMANTIC_23);
197 LINK_STATES(SQ_VTX_SEMANTIC_24);
198 LINK_STATES(SQ_VTX_SEMANTIC_25);
199 LINK_STATES(SQ_VTX_SEMANTIC_26);
200 LINK_STATES(SQ_VTX_SEMANTIC_27);
201 LINK_STATES(SQ_VTX_SEMANTIC_28);
202 LINK_STATES(SQ_VTX_SEMANTIC_29);
203 LINK_STATES(SQ_VTX_SEMANTIC_30);
204 LINK_STATES(SQ_VTX_SEMANTIC_31);
205
206 // SPI
207 LINK_STATES(SPI_VS_OUT_ID_0);
208 LINK_STATES(SPI_VS_OUT_ID_1);
209 LINK_STATES(SPI_VS_OUT_ID_2);
210 LINK_STATES(SPI_VS_OUT_ID_3);
211 LINK_STATES(SPI_VS_OUT_ID_4);
212 LINK_STATES(SPI_VS_OUT_ID_5);
213 LINK_STATES(SPI_VS_OUT_ID_6);
214 LINK_STATES(SPI_VS_OUT_ID_7);
215 LINK_STATES(SPI_VS_OUT_ID_8);
216 LINK_STATES(SPI_VS_OUT_ID_9);
217
218 LINK_STATES(SPI_VS_OUT_CONFIG);
219 LINK_STATES(SPI_THREAD_GROUPING);
220 LINK_STATES(SPI_PS_IN_CONTROL_0);
221 LINK_STATES(SPI_PS_IN_CONTROL_1);
222 LINK_STATES(SPI_INTERP_CONTROL_0);
223 LINK_STATES(SPI_INPUT_Z);
224 LINK_STATES(SPI_FOG_CNTL);
225 LINK_STATES(SPI_FOG_FUNC_SCALE);
226 LINK_STATES(SPI_FOG_FUNC_BIAS);
227
228 // SQ
229 LINK_STATES(SQ_ESGS_RING_ITEMSIZE);
230 LINK_STATES(SQ_GSVS_RING_ITEMSIZE);
231 LINK_STATES(SQ_ESTMP_RING_ITEMSIZE);
232 LINK_STATES(SQ_GSTMP_RING_ITEMSIZE);
233 LINK_STATES(SQ_VSTMP_RING_ITEMSIZE);
234 LINK_STATES(SQ_PSTMP_RING_ITEMSIZE);
235 LINK_STATES(SQ_FBUF_RING_ITEMSIZE);
236 LINK_STATES(SQ_REDUC_RING_ITEMSIZE);
237 //LINK_STATES(SQ_GS_VERT_ITEMSIZE);
238
239 pStateListWork->puiValue = (unsigned int*)&(r700->SQ_GS_VERT_ITEMSIZE);
240 pStateListWork->unOffset = mmSQ_GS_VERT_ITEMSIZE - ASIC_CONTEXT_BASE_INDEX;
241 pStateListWork->pNext = NULL; /* END OF STATE LIST */
242
243 return GL_TRUE;
244 }
245
246 GLboolean r700SendTextureState(context_t *context)
247 {
248 unsigned int i;
249 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
250 struct radeon_bo *bo = NULL;
251 BATCH_LOCALS(&context->radeon);
252
253 for (i=0; i<R700_TEXTURE_NUMBERUNITS; i++) {
254 radeonTexObj *t = r700->textures[i];
255 if (t) {
256 if (!t->image_override)
257 bo = t->mt->bo;
258 else
259 bo = t->bo;
260 if (bo) {
261
262 r700SyncSurf(context, bo,
263 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
264 0, TC_ACTION_ENA_bit);
265
266 BEGIN_BATCH_NO_AUTOSTATE(9);
267 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
268 R600_OUT_BATCH(i * 7);
269 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
270 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
271 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
272 bo,
273 0,
274 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
275 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
276 bo,
277 r700->textures[i]->SQ_TEX_RESOURCE3,
278 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
279 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
280 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
281 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
282 END_BATCH();
283
284 BEGIN_BATCH_NO_AUTOSTATE(5);
285 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
286 R600_OUT_BATCH(i * 3);
287 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
288 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
289 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
290 END_BATCH();
291
292 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
293 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
294 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
295 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
296 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
297 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
298 END_BATCH();
299
300 COMMIT_BATCH();
301 }
302 }
303 }
304 return GL_TRUE;
305 }
306
307 void r700SetupVTXConstants(GLcontext * ctx,
308 unsigned int nStreamID,
309 void * pAos,
310 unsigned int size, /* number of elements in vector */
311 unsigned int stride,
312 unsigned int count) /* number of vectors in stream */
313 {
314 context_t *context = R700_CONTEXT(ctx);
315 struct radeon_aos * paos = (struct radeon_aos *)pAos;
316 BATCH_LOCALS(&context->radeon);
317
318 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
319 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
320 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
321 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
322 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
323
324 if (!paos->bo)
325 return GL_FALSE;
326
327 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
328 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
329 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
330 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
331 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
332 else
333 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
334
335 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
336 uSQ_VTX_CONSTANT_WORD1_0 = count * (size * 4) - 1;
337
338 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
339 SETfield(uSQ_VTX_CONSTANT_WORD2_0, stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
340 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
341 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(GL_FLOAT, size, NULL),
342 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
343 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
344 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
345 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
346 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
347
348 SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
349 SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
350 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
351
352 BEGIN_BATCH_NO_AUTOSTATE(9);
353
354 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
355 R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
356
357 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
358 paos->bo,
359 uSQ_VTX_CONSTANT_WORD0_0,
360 RADEON_GEM_DOMAIN_GTT, 0, 0);
361 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
362 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
363 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
364 R600_OUT_BATCH(0);
365 R600_OUT_BATCH(0);
366 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
367
368 END_BATCH();
369 COMMIT_BATCH();
370
371 }
372
373 int r700SetupStreams(GLcontext * ctx)
374 {
375 context_t *context = R700_CONTEXT(ctx);
376 BATCH_LOCALS(&context->radeon);
377
378 struct r700_vertex_program *vpc
379 = (struct r700_vertex_program *)ctx->VertexProgram._Current;
380
381 TNLcontext *tnl = TNL_CONTEXT(ctx);
382 struct vertex_buffer *vb = &tnl->vb;
383
384 unsigned int unBit;
385 unsigned int i, j = 0;
386
387 BEGIN_BATCH_NO_AUTOSTATE(6);
388 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
389 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
390 R600_OUT_BATCH(0);
391
392 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
393 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
394 R600_OUT_BATCH(0);
395 END_BATCH();
396 COMMIT_BATCH();
397
398 context->radeon.tcl.aos_count = 0;
399 for(i=0; i<VERT_ATTRIB_MAX; i++)
400 {
401 unBit = 1 << i;
402 if(vpc->mesa_program.Base.InputsRead & unBit)
403 {
404 rcommon_emit_vector(ctx,
405 &context->radeon.tcl.aos[j],
406 vb->AttribPtr[i]->data,
407 vb->AttribPtr[i]->size,
408 vb->AttribPtr[i]->stride,
409 vb->Count);
410
411 /* currently aos are packed */
412 r700SetupVTXConstants(ctx,
413 i,
414 (void*)(&context->radeon.tcl.aos[j]),
415 (unsigned int)context->radeon.tcl.aos[j].components,
416 (unsigned int)context->radeon.tcl.aos[j].stride * 4,
417 (unsigned int)context->radeon.tcl.aos[j].count);
418 j++;
419 context->radeon.tcl.aos_count++;
420 }
421 }
422
423 return R600_FALLBACK_NONE;
424 }
425
426 GLboolean r700SendContextStates(context_t *context)
427 {
428 BATCH_LOCALS(&context->radeon);
429
430 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
431
432 ContextState * pState = r700->pStateList;
433 ContextState * pInit;
434 unsigned int toSend;
435 unsigned int ui;
436
437 while(NULL != pState)
438 {
439 toSend = 1;
440
441 pInit = pState;
442
443 while(NULL != pState->pNext)
444 {
445 if ((pState->pNext->unOffset - pState->unOffset) > 1)
446 {
447 break;
448 }
449 else
450 {
451 pState = pState->pNext;
452 toSend++;
453 }
454 }
455
456 pState = pState->pNext;
457
458 BEGIN_BATCH_NO_AUTOSTATE(toSend + 2);
459 R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend);
460 for(ui=0; ui<toSend; ui++)
461 {
462 R600_OUT_BATCH(*(pInit->puiValue));
463 pInit = pInit->pNext;
464 };
465 END_BATCH();
466 };
467
468 /* todo:
469 * - split this into a separate function?
470 * - only emit the ones we use
471 */
472 BEGIN_BATCH_NO_AUTOSTATE(2 + R700_MAX_SHADER_EXPORTS);
473 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
474 for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
475 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
476 END_BATCH();
477 COMMIT_BATCH();
478
479 return GL_TRUE;
480 }
481
482 GLboolean r700SendDepthTargetState(context_t *context)
483 {
484 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
485 struct radeon_renderbuffer *rrb;
486 BATCH_LOCALS(&context->radeon);
487
488 rrb = radeon_get_depthbuffer(&context->radeon);
489 if (!rrb || !rrb->bo) {
490 fprintf(stderr, "no rrb\n");
491 return GL_FALSE;
492 }
493
494 BEGIN_BATCH_NO_AUTOSTATE(9);
495 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
496 R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
497 R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
498 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 3);
499 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
500 rrb->bo,
501 r700->DB_DEPTH_BASE.u32All,
502 0, RADEON_GEM_DOMAIN_VRAM, 0);
503 R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
504 R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All);
505 END_BATCH();
506
507 BEGIN_BATCH_NO_AUTOSTATE(24);
508 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
509 R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
510 R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
511
512 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
513 R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
514 R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
515
516 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
517 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
518
519 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
520 R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
521 R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
522
523 R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
524 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
525 END_BATCH();
526
527 COMMIT_BATCH();
528
529 r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
530 DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
531
532 return GL_TRUE;
533 }
534
535 GLboolean r700SendRenderTargetState(context_t *context, int id)
536 {
537 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
538 struct radeon_renderbuffer *rrb;
539 BATCH_LOCALS(&context->radeon);
540
541 rrb = radeon_get_colorbuffer(&context->radeon);
542 if (!rrb || !rrb->bo) {
543 fprintf(stderr, "no rrb\n");
544 return GL_FALSE;
545 }
546
547 if (id > R700_MAX_RENDER_TARGETS)
548 return GL_FALSE;
549
550 if (!r700->render_target[id].enabled)
551 return GL_FALSE;
552
553 BEGIN_BATCH_NO_AUTOSTATE(3);
554 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
555 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
556 rrb->bo,
557 r700->render_target[id].CB_COLOR0_BASE.u32All,
558 0, RADEON_GEM_DOMAIN_VRAM, 0);
559 END_BATCH();
560
561 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
562 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
563 BEGIN_BATCH_NO_AUTOSTATE(2);
564 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
565 R600_OUT_BATCH((2 << id));
566 END_BATCH();
567 }
568
569 BEGIN_BATCH_NO_AUTOSTATE(18);
570 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
571 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
572 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
573 R600_OUT_BATCH_REGVAL(CB_COLOR0_TILE + (4 * id), r700->render_target[id].CB_COLOR0_TILE.u32All);
574 R600_OUT_BATCH_REGVAL(CB_COLOR0_FRAG + (4 * id), r700->render_target[id].CB_COLOR0_FRAG.u32All);
575 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
576 END_BATCH();
577
578 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
579 BEGIN_BATCH_NO_AUTOSTATE(3);
580 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * id), r700->render_target[id].CB_BLEND0_CONTROL.u32All);
581 END_BATCH();
582 }
583
584 COMMIT_BATCH();
585
586 r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
587 CB_ACTION_ENA_bit | (1 << (id + 6)));
588
589 return GL_TRUE;
590 }
591
592 GLboolean r700SendPSState(context_t *context)
593 {
594 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
595 struct radeon_bo * pbo;
596 BATCH_LOCALS(&context->radeon);
597
598 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
599
600 if (!pbo)
601 return GL_FALSE;
602
603 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
604
605 BEGIN_BATCH_NO_AUTOSTATE(3);
606 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
607 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
608 pbo,
609 r700->ps.SQ_PGM_START_PS.u32All,
610 RADEON_GEM_DOMAIN_GTT, 0, 0);
611 END_BATCH();
612
613 BEGIN_BATCH_NO_AUTOSTATE(9);
614 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
615 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
616 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
617 END_BATCH();
618
619 COMMIT_BATCH();
620
621 return GL_TRUE;
622 }
623
624 GLboolean r700SendVSState(context_t *context)
625 {
626 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
627 struct radeon_bo * pbo;
628 BATCH_LOCALS(&context->radeon);
629
630 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
631
632 if (!pbo)
633 return GL_FALSE;
634
635 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
636
637 BEGIN_BATCH_NO_AUTOSTATE(3);
638 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
639 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
640 pbo,
641 r700->vs.SQ_PGM_START_VS.u32All,
642 RADEON_GEM_DOMAIN_GTT, 0, 0);
643 END_BATCH();
644
645 BEGIN_BATCH_NO_AUTOSTATE(6);
646 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
647 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
648 END_BATCH();
649
650 COMMIT_BATCH();
651
652 return GL_TRUE;
653 }
654
655 GLboolean r700SendFSState(context_t *context)
656 {
657 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
658 struct radeon_bo * pbo;
659 BATCH_LOCALS(&context->radeon);
660
661 /* XXX fixme
662 * R6xx chips require a FS be emitted, even if it's not used.
663 * since we aren't using FS yet, just send the VS address to make
664 * the kernel command checker happy
665 */
666 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
667 r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
668 r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
669 r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
670 /* XXX */
671
672 if (!pbo)
673 return GL_FALSE;
674
675 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
676
677 BEGIN_BATCH_NO_AUTOSTATE(3);
678 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
679 R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
680 pbo,
681 r700->fs.SQ_PGM_START_FS.u32All,
682 RADEON_GEM_DOMAIN_GTT, 0, 0);
683 END_BATCH();
684
685 BEGIN_BATCH_NO_AUTOSTATE(6);
686 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
687 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
688 END_BATCH();
689
690 COMMIT_BATCH();
691
692 return GL_TRUE;
693 }
694
695 GLboolean r700SendViewportState(context_t *context, int id)
696 {
697 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
698 BATCH_LOCALS(&context->radeon);
699
700 if (id > R700_MAX_VIEWPORTS)
701 return GL_FALSE;
702
703 if (!r700->viewport[id].enabled)
704 return GL_FALSE;
705
706 BEGIN_BATCH_NO_AUTOSTATE(16);
707 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
708 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
709 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
710 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
711 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
712 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
713 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
714 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
715 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
716 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
717 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
718 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
719 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
720 END_BATCH();
721
722 COMMIT_BATCH();
723
724 return GL_TRUE;
725 }
726
727 GLboolean r700SendSQConfig(context_t *context)
728 {
729 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
730 BATCH_LOCALS(&context->radeon);
731
732 BEGIN_BATCH_NO_AUTOSTATE(8);
733 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
734 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
735 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
736 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
737 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
738 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
739 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
740 END_BATCH();
741 COMMIT_BATCH();
742
743 return GL_TRUE;
744 }
745
746 GLboolean r700SendUCPState(context_t *context)
747 {
748 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
749 BATCH_LOCALS(&context->radeon);
750 int i;
751
752 for (i = 0; i < R700_MAX_UCP; i++) {
753 if (r700->ucp[i].enabled) {
754 BEGIN_BATCH_NO_AUTOSTATE(6);
755 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
756 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
757 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
758 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
759 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
760 END_BATCH();
761 COMMIT_BATCH();
762 }
763 }
764
765 return GL_TRUE;
766 }
767