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r600 : Initial version of glsl fc.
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30 #include "main/simple_list.h"
31
32 #include "r600_context.h"
33 #include "r600_cmdbuf.h"
34
35 #include "r700_state.h"
36 #include "r600_tex.h"
37 #include "r700_oglprog.h"
38 #include "r700_fragprog.h"
39 #include "r700_vertprog.h"
40 #include "r700_ioctl.h"
41
42 #include "radeon_mipmap_tree.h"
43
44 static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
45 {
46 context_t *context = R700_CONTEXT(ctx);
47 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
48 struct radeon_bo *bo = NULL;
49 unsigned int i;
50 BATCH_LOCALS(&context->radeon);
51
52 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
53
54 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
55 if (ctx->Texture.Unit[i]._ReallyEnabled) {
56 radeonTexObj *t = r700->textures[i];
57 if (t) {
58 if (!t->image_override)
59 bo = t->mt->bo;
60 else
61 bo = t->bo;
62 if (bo) {
63
64 r700SyncSurf(context, bo,
65 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
66 0, TC_ACTION_ENA_bit);
67
68 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
69 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
70 R600_OUT_BATCH(i * 7);
71 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
72 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
73 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
74 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
75 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
76 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
77 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
78 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
79 bo,
80 0,
81 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
82 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
83 bo,
84 r700->textures[i]->SQ_TEX_RESOURCE3,
85 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
86 END_BATCH();
87 COMMIT_BATCH();
88 }
89 }
90 }
91 }
92 }
93
94 static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
95 {
96 context_t *context = R700_CONTEXT(ctx);
97 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
98 unsigned int i;
99 BATCH_LOCALS(&context->radeon);
100 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
101
102 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
103 if (ctx->Texture.Unit[i]._ReallyEnabled) {
104 radeonTexObj *t = r700->textures[i];
105 if (t) {
106 BEGIN_BATCH_NO_AUTOSTATE(5);
107 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
108 R600_OUT_BATCH(i * 3);
109 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
110 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
111 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
112 END_BATCH();
113 COMMIT_BATCH();
114 }
115 }
116 }
117 }
118
119 static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
120 {
121 context_t *context = R700_CONTEXT(ctx);
122 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
123 unsigned int i;
124 BATCH_LOCALS(&context->radeon);
125 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
126
127 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
128 if (ctx->Texture.Unit[i]._ReallyEnabled) {
129 radeonTexObj *t = r700->textures[i];
130 if (t) {
131 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
132 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
133 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
134 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
135 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
136 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
137 END_BATCH();
138 COMMIT_BATCH();
139 }
140 }
141 }
142 }
143
144 extern int getTypeSize(GLenum type);
145 static void r700SetupVTXConstants(GLcontext * ctx,
146 void * pAos,
147 StreamDesc * pStreamDesc)
148 {
149 context_t *context = R700_CONTEXT(ctx);
150 struct radeon_aos * paos = (struct radeon_aos *)pAos;
151 unsigned int nVBsize;
152 BATCH_LOCALS(&context->radeon);
153
154 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
155 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
156 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
157 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
158 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
159
160 if (!paos->bo)
161 return;
162
163 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
164 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
165 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
166 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
167 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
168 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
169 else
170 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
171
172 if(0 == pStreamDesc->stride)
173 {
174 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
175 }
176 else
177 {
178 nVBsize = paos->count * pStreamDesc->stride;
179 }
180
181 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
182 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize - 1;
183
184 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
185 SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
186 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
187 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
188 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
189 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
190
191 if(GL_TRUE == pStreamDesc->normalize)
192 {
193 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
194 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
195 }
196 //else
197 //{
198 // SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_INT,
199 // SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
200 //}
201
202 if(1 == pStreamDesc->_signed)
203 {
204 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
205 }
206
207 SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
208 SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
209 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
210
211 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
212
213 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
214 R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
215 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
216 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
217 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
218 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
219 R600_OUT_BATCH(0);
220 R600_OUT_BATCH(0);
221 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
222 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
223 paos->bo,
224 uSQ_VTX_CONSTANT_WORD0_0,
225 RADEON_GEM_DOMAIN_GTT, 0, 0);
226 END_BATCH();
227 COMMIT_BATCH();
228
229 }
230
231 static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
232 {
233 context_t *context = R700_CONTEXT(ctx);
234 struct r700_vertex_program *vp = context->selected_vp;
235 unsigned int i, j = 0;
236 BATCH_LOCALS(&context->radeon);
237 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
238
239 if (context->radeon.tcl.aos_count == 0)
240 return;
241
242 BEGIN_BATCH_NO_AUTOSTATE(6);
243 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
244 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
245 R600_OUT_BATCH(0);
246
247 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
248 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
249 R600_OUT_BATCH(0);
250 END_BATCH();
251 COMMIT_BATCH();
252
253 for(i=0; i<VERT_ATTRIB_MAX; i++) {
254 if(vp->mesa_program->Base.InputsRead & (1 << i))
255 {
256 r700SetupVTXConstants(ctx,
257 (void*)(&context->radeon.tcl.aos[j]),
258 &(context->stream_desc[j]));
259 j++;
260 }
261 }
262 }
263
264 static void r700SetRenderTarget(context_t *context, int id)
265 {
266 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
267
268 struct radeon_renderbuffer *rrb;
269 unsigned int nPitchInPixel;
270
271 rrb = radeon_get_colorbuffer(&context->radeon);
272 if (!rrb || !rrb->bo) {
273 return;
274 }
275
276 R600_STATECHANGE(context, cb_target);
277
278 /* color buffer */
279 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
280
281 nPitchInPixel = rrb->pitch/rrb->cpp;
282 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
283 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
284 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
285 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
286 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
287 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
288 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
289 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
290 if(4 == rrb->cpp)
291 {
292 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
293 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
294 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
295 }
296 else
297 {
298 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
299 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
300 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
301 COMP_SWAP_shift, COMP_SWAP_mask);
302 }
303 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
304 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
305 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
306
307 r700->render_target[id].enabled = GL_TRUE;
308 }
309
310 static void r700SetDepthTarget(context_t *context)
311 {
312 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
313
314 struct radeon_renderbuffer *rrb;
315 unsigned int nPitchInPixel;
316
317 rrb = radeon_get_depthbuffer(&context->radeon);
318 if (!rrb)
319 return;
320
321 R600_STATECHANGE(context, db_target);
322
323 /* depth buf */
324 r700->DB_DEPTH_SIZE.u32All = 0;
325 r700->DB_DEPTH_BASE.u32All = 0;
326 r700->DB_DEPTH_INFO.u32All = 0;
327 r700->DB_DEPTH_VIEW.u32All = 0;
328
329 nPitchInPixel = rrb->pitch/rrb->cpp;
330
331 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
332 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
333 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
334 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
335
336 if(4 == rrb->cpp)
337 {
338 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
339 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
340 }
341 else
342 {
343 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
344 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
345 }
346 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
347 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
348 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
349 }
350
351 static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
352 {
353 context_t *context = R700_CONTEXT(ctx);
354 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
355 struct radeon_renderbuffer *rrb;
356 BATCH_LOCALS(&context->radeon);
357 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
358
359 rrb = radeon_get_depthbuffer(&context->radeon);
360 if (!rrb || !rrb->bo) {
361 return;
362 }
363
364 r700SetDepthTarget(context);
365
366 BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
367 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
368 R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
369 R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
370 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
371 R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
372 R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
373 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
374 rrb->bo,
375 r700->DB_DEPTH_BASE.u32All,
376 0, RADEON_GEM_DOMAIN_VRAM, 0);
377 END_BATCH();
378
379 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
380 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
381 BEGIN_BATCH_NO_AUTOSTATE(2);
382 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
383 R600_OUT_BATCH(1 << 0);
384 END_BATCH();
385 }
386
387 COMMIT_BATCH();
388
389 }
390
391 static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
392 {
393 context_t *context = R700_CONTEXT(ctx);
394 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
395 struct radeon_renderbuffer *rrb;
396 BATCH_LOCALS(&context->radeon);
397 int id = 0;
398 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
399
400 rrb = radeon_get_colorbuffer(&context->radeon);
401 if (!rrb || !rrb->bo) {
402 return;
403 }
404
405 r700SetRenderTarget(context, 0);
406
407 if (id > R700_MAX_RENDER_TARGETS)
408 return;
409
410 if (!r700->render_target[id].enabled)
411 return;
412
413 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
414 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
415 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
416 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
417 rrb->bo,
418 r700->render_target[id].CB_COLOR0_BASE.u32All,
419 0, RADEON_GEM_DOMAIN_VRAM, 0);
420 END_BATCH();
421
422 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
423 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
424 BEGIN_BATCH_NO_AUTOSTATE(2);
425 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
426 R600_OUT_BATCH((2 << id));
427 END_BATCH();
428 }
429
430 BEGIN_BATCH_NO_AUTOSTATE(18);
431 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
432 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
433 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
434 R600_OUT_BATCH_REGVAL(CB_COLOR0_TILE + (4 * id), r700->render_target[id].CB_COLOR0_TILE.u32All);
435 R600_OUT_BATCH_REGVAL(CB_COLOR0_FRAG + (4 * id), r700->render_target[id].CB_COLOR0_FRAG.u32All);
436 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
437 END_BATCH();
438
439 COMMIT_BATCH();
440
441 }
442
443 static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
444 {
445 context_t *context = R700_CONTEXT(ctx);
446 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
447 struct radeon_bo * pbo;
448 BATCH_LOCALS(&context->radeon);
449 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
450
451 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
452
453 if (!pbo)
454 return;
455
456 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
457
458 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
459 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
460 R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
461 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
462 pbo,
463 r700->ps.SQ_PGM_START_PS.u32All,
464 RADEON_GEM_DOMAIN_GTT, 0, 0);
465 END_BATCH();
466
467 BEGIN_BATCH_NO_AUTOSTATE(9);
468 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
469 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
470 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
471 END_BATCH();
472
473 BEGIN_BATCH_NO_AUTOSTATE(3);
474 R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
475 END_BATCH();
476
477 COMMIT_BATCH();
478
479 }
480
481 static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
482 {
483 context_t *context = R700_CONTEXT(ctx);
484 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
485 struct radeon_bo * pbo;
486 BATCH_LOCALS(&context->radeon);
487 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
488
489 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
490
491 if (!pbo)
492 return;
493
494 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
495
496 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
497 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
498 R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
499 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
500 pbo,
501 r700->vs.SQ_PGM_START_VS.u32All,
502 RADEON_GEM_DOMAIN_GTT, 0, 0);
503 END_BATCH();
504
505 BEGIN_BATCH_NO_AUTOSTATE(6);
506 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
507 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
508 END_BATCH();
509
510 BEGIN_BATCH_NO_AUTOSTATE(3);
511 R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
512 //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
513 END_BATCH();
514
515 COMMIT_BATCH();
516 }
517
518 static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
519 {
520 context_t *context = R700_CONTEXT(ctx);
521 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
522 struct radeon_bo * pbo;
523 BATCH_LOCALS(&context->radeon);
524 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
525
526 /* XXX fixme
527 * R6xx chips require a FS be emitted, even if it's not used.
528 * since we aren't using FS yet, just send the VS address to make
529 * the kernel command checker happy
530 */
531 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
532 r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
533 r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
534 r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
535 /* XXX */
536
537 if (!pbo)
538 return;
539
540 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
541
542 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
543 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
544 R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
545 R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
546 pbo,
547 r700->fs.SQ_PGM_START_FS.u32All,
548 RADEON_GEM_DOMAIN_GTT, 0, 0);
549 END_BATCH();
550
551 BEGIN_BATCH_NO_AUTOSTATE(6);
552 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
553 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
554 END_BATCH();
555
556 COMMIT_BATCH();
557
558 }
559
560 static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
561 {
562 context_t *context = R700_CONTEXT(ctx);
563 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
564 BATCH_LOCALS(&context->radeon);
565 int id = 0;
566 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
567
568 if (id > R700_MAX_VIEWPORTS)
569 return;
570
571 if (!r700->viewport[id].enabled)
572 return;
573
574 BEGIN_BATCH_NO_AUTOSTATE(16);
575 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
576 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
577 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
578 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
579 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
580 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
581 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
582 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
583 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
584 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
585 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
586 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
587 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
588 END_BATCH();
589
590 COMMIT_BATCH();
591
592 }
593
594 static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
595 {
596 context_t *context = R700_CONTEXT(ctx);
597 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
598 BATCH_LOCALS(&context->radeon);
599 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
600
601 BEGIN_BATCH_NO_AUTOSTATE(34);
602 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
603 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
604 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
605 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
606 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
607 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
608 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
609
610 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
611 R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
612 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
613 R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
614 R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
615
616 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
617 R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
618 R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
619 R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
620 R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
621 R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
622 R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
623 R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
624 R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
625 R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
626 END_BATCH();
627
628 COMMIT_BATCH();
629 }
630
631 static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
632 {
633 context_t *context = R700_CONTEXT(ctx);
634 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
635 BATCH_LOCALS(&context->radeon);
636 int i;
637 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
638
639 for (i = 0; i < R700_MAX_UCP; i++) {
640 if (r700->ucp[i].enabled) {
641 BEGIN_BATCH_NO_AUTOSTATE(6);
642 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
643 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
644 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
645 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
646 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
647 END_BATCH();
648 COMMIT_BATCH();
649 }
650 }
651 }
652
653 static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
654 {
655 context_t *context = R700_CONTEXT(ctx);
656 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
657 BATCH_LOCALS(&context->radeon);
658 unsigned int ui;
659 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
660
661 BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
662
663 R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
664 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
665 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
666 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
667 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
668 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
669 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
670 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
671 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
672 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
673 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
674 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
675 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
676 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
677 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
678 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
679 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
680 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
681 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
682 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
683 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
684 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
685 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
686 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
687 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
688 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
689 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
690 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
691 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
692 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
693 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
694 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
695 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
696
697 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
698 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
699 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
700 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
701 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
702 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
703 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
704 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
705 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
706 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
707 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
708
709 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
710 R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
711 R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
712 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
713 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
714 R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
715 R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
716 R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
717 R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
718 R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
719
720 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
721 for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
722 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
723
724 END_BATCH();
725 COMMIT_BATCH();
726 }
727
728 static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
729 {
730 context_t *context = R700_CONTEXT(ctx);
731 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
732 BATCH_LOCALS(&context->radeon);
733 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
734
735 BEGIN_BATCH_NO_AUTOSTATE(41);
736
737 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
738 R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
739 R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
740 R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
741 R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
742
743 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
744 R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
745 R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
746 R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
747 R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
748 R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
749 R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
750 R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
751 R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
752 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
753 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
754 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
755 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
756 R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
757
758 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
759 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
760 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
761 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
762
763 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
764 R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
765 R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
766 R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
767
768 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
769
770 END_BATCH();
771 COMMIT_BATCH();
772 }
773
774 static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
775 {
776 context_t *context = R700_CONTEXT(ctx);
777 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
778 BATCH_LOCALS(&context->radeon);
779 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
780
781 BEGIN_BATCH_NO_AUTOSTATE(9);
782 R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
783 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
784 R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
785 END_BATCH();
786 COMMIT_BATCH();
787 }
788
789 static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
790 {
791 context_t *context = R700_CONTEXT(ctx);
792 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
793 BATCH_LOCALS(&context->radeon);
794 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
795
796 BEGIN_BATCH_NO_AUTOSTATE(17);
797
798 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
799 R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
800 R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
801
802 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
803 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
804
805 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
806 R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
807 R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
808
809 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
810
811 END_BATCH();
812 COMMIT_BATCH();
813 }
814
815 static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
816 {
817 context_t *context = R700_CONTEXT(ctx);
818 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
819 BATCH_LOCALS(&context->radeon);
820
821 BEGIN_BATCH_NO_AUTOSTATE(4);
822 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
823 R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
824 R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
825 END_BATCH();
826 COMMIT_BATCH();
827 }
828
829 static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
830 {
831 context_t *context = R700_CONTEXT(ctx);
832 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
833 BATCH_LOCALS(&context->radeon);
834 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
835
836 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
837 BEGIN_BATCH_NO_AUTOSTATE(11);
838 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
839 R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
840 R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
841 R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
842 R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
843 R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
844 R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
845 R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
846 R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
847 END_BATCH();
848 }
849
850 BEGIN_BATCH_NO_AUTOSTATE(7);
851 R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
852 R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
853 R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
854 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
855 END_BATCH();
856 COMMIT_BATCH();
857 }
858
859 static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
860 {
861 context_t *context = R700_CONTEXT(ctx);
862 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
863 BATCH_LOCALS(&context->radeon);
864
865 BEGIN_BATCH_NO_AUTOSTATE(6);
866 R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
867 R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
868 R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
869 R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
870 R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
871 END_BATCH();
872 COMMIT_BATCH();
873 }
874
875 static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
876 {
877 context_t *context = R700_CONTEXT(ctx);
878 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
879 BATCH_LOCALS(&context->radeon);
880 unsigned int ui;
881 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
882
883 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
884 BEGIN_BATCH_NO_AUTOSTATE(3);
885 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
886 END_BATCH();
887 }
888
889 BEGIN_BATCH_NO_AUTOSTATE(3);
890 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
891 END_BATCH();
892
893 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
894 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
895 if (r700->render_target[ui].enabled) {
896 BEGIN_BATCH_NO_AUTOSTATE(3);
897 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
898 r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
899 END_BATCH();
900 }
901 }
902 }
903
904 COMMIT_BATCH();
905 }
906
907 static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
908 {
909 context_t *context = R700_CONTEXT(ctx);
910 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
911 BATCH_LOCALS(&context->radeon);
912 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
913
914 BEGIN_BATCH_NO_AUTOSTATE(6);
915 R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
916 R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
917 R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
918 R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
919 R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
920 END_BATCH();
921 COMMIT_BATCH();
922 }
923
924 static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
925 {
926 context_t *context = R700_CONTEXT(ctx);
927 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
928 BATCH_LOCALS(&context->radeon);
929
930 BEGIN_BATCH_NO_AUTOSTATE(9);
931 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
932 R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
933 R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
934 R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
935 R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
936 R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
937 END_BATCH();
938 COMMIT_BATCH();
939
940 }
941
942 static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
943 {
944 context_t *context = R700_CONTEXT(ctx);
945 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
946 BATCH_LOCALS(&context->radeon);
947
948 BEGIN_BATCH_NO_AUTOSTATE(10);
949 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
950 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
951 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
952 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
953 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
954 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
955 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
956 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
957 END_BATCH();
958 COMMIT_BATCH();
959
960 }
961
962 static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
963 {
964 context_t *context = R700_CONTEXT(ctx);
965 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
966 BATCH_LOCALS(&context->radeon);
967 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
968
969 BEGIN_BATCH_NO_AUTOSTATE(12);
970 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
971 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
972 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
973 R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
974 END_BATCH();
975 COMMIT_BATCH();
976 }
977
978 static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
979 {
980 context_t *context = R700_CONTEXT(ctx);
981 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
982 BATCH_LOCALS(&context->radeon);
983
984 BEGIN_BATCH_NO_AUTOSTATE(6);
985 R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
986 R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
987 R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
988 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
989 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
990 END_BATCH();
991 COMMIT_BATCH();
992 }
993
994 static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
995 {
996 context_t *context = R700_CONTEXT(ctx);
997 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
998 BATCH_LOCALS(&context->radeon);
999 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1000
1001 BEGIN_BATCH_NO_AUTOSTATE(22);
1002 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1003 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
1004 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
1005
1006 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
1007 R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
1008 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
1009 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
1010 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
1011 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
1012 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
1013 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
1014 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
1015 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
1016 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
1017 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
1018 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
1019
1020 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1021 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
1022 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
1023 END_BATCH();
1024 COMMIT_BATCH();
1025 }
1026
1027 static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
1028 {
1029 context_t *context = R700_CONTEXT(ctx);
1030 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1031 BATCH_LOCALS(&context->radeon);
1032 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1033
1034 BEGIN_BATCH_NO_AUTOSTATE(15);
1035 R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
1036 R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
1037 R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
1038 R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
1039 R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
1040 END_BATCH();
1041 COMMIT_BATCH();
1042 }
1043
1044 static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
1045 {
1046 context_t *context = R700_CONTEXT(ctx);
1047 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1048 BATCH_LOCALS(&context->radeon);
1049
1050 BEGIN_BATCH_NO_AUTOSTATE(12);
1051 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
1052 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
1053 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
1054 R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
1055 END_BATCH();
1056 COMMIT_BATCH();
1057 }
1058
1059 static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1060 {
1061 context_t *context = R700_CONTEXT(ctx);
1062 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1063 int i;
1064 BATCH_LOCALS(&context->radeon);
1065
1066 if (r700->ps.num_consts == 0)
1067 return;
1068
1069 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
1070 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
1071 /* assembler map const from very beginning. */
1072 R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
1073 for (i = 0; i < r700->ps.num_consts; i++) {
1074 R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
1075 R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
1076 R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
1077 R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
1078 }
1079 END_BATCH();
1080 COMMIT_BATCH();
1081 }
1082
1083 static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1084 {
1085 context_t *context = R700_CONTEXT(ctx);
1086 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1087 int i;
1088 BATCH_LOCALS(&context->radeon);
1089 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1090
1091 if (r700->vs.num_consts == 0)
1092 return;
1093
1094 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
1095 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
1096 /* assembler map const from very beginning. */
1097 R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
1098 for (i = 0; i < r700->vs.num_consts; i++) {
1099 R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
1100 R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
1101 R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
1102 R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
1103 }
1104 END_BATCH();
1105 COMMIT_BATCH();
1106 }
1107
1108 static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
1109 {
1110 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1111 struct radeon_query_object *query = radeon->query.current;
1112 BATCH_LOCALS(radeon);
1113 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1114
1115 /* clear the buffer */
1116 radeon_bo_map(query->bo, GL_FALSE);
1117 memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
1118 radeon_bo_unmap(query->bo);
1119
1120 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
1121 query->bo,
1122 0, RADEON_GEM_DOMAIN_GTT);
1123
1124 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
1125 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
1126 R600_OUT_BATCH(ZPASS_DONE);
1127 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
1128 R600_OUT_BATCH(0x00000000);
1129 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
1130 END_BATCH();
1131 query->emitted_begin = GL_TRUE;
1132 }
1133
1134 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
1135 {
1136 return atom->cmd_size;
1137 }
1138
1139 static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
1140 {
1141 context_t *context = R700_CONTEXT(ctx);
1142 int count = 7;
1143
1144 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1145 count += 11;
1146 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1147
1148 return count;
1149 }
1150
1151 static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
1152 {
1153 context_t *context = R700_CONTEXT(ctx);
1154 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1155 unsigned int ui;
1156 int count = 3;
1157
1158 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1159 count += 3;
1160
1161 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1162 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
1163 if (r700->render_target[ui].enabled)
1164 count += 3;
1165 }
1166 }
1167 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1168
1169 return count;
1170 }
1171
1172 static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
1173 {
1174 context_t *context = R700_CONTEXT(ctx);
1175 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1176 int i;
1177 int count = 0;
1178
1179 for (i = 0; i < R700_MAX_UCP; i++) {
1180 if (r700->ucp[i].enabled)
1181 count += 6;
1182 }
1183 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1184 return count;
1185 }
1186
1187 static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
1188 {
1189 context_t *context = R700_CONTEXT(ctx);
1190 int count = context->radeon.tcl.aos_count * 18;
1191
1192 if (count)
1193 count += 6;
1194
1195 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1196 return count;
1197 }
1198
1199 static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
1200 {
1201 context_t *context = R700_CONTEXT(ctx);
1202 unsigned int i, count = 0;
1203 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1204
1205 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
1206 if (ctx->Texture.Unit[i]._ReallyEnabled) {
1207 radeonTexObj *t = r700->textures[i];
1208 if (t)
1209 count++;
1210 }
1211 }
1212 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1213 return count * 31;
1214 }
1215
1216 static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1217 {
1218 context_t *context = R700_CONTEXT(ctx);
1219 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1220 int count = r700->ps.num_consts * 4;
1221
1222 if (count)
1223 count += 2;
1224 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1225
1226 return count;
1227 }
1228
1229 static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1230 {
1231 context_t *context = R700_CONTEXT(ctx);
1232 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1233 int count = r700->vs.num_consts * 4;
1234
1235 if (count)
1236 count += 2;
1237 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1238
1239 return count;
1240 }
1241
1242 static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
1243 {
1244 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1245 struct radeon_query_object *query = radeon->query.current;
1246 int count;
1247
1248 if (!query || query->emitted_begin)
1249 count = 0;
1250 else
1251 count = atom->cmd_size;
1252 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1253 return count;
1254 }
1255
1256 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
1257 do { \
1258 context->atoms.ATOM.cmd_size = (SZ); \
1259 context->atoms.ATOM.cmd = NULL; \
1260 context->atoms.ATOM.name = #ATOM; \
1261 context->atoms.ATOM.idx = 0; \
1262 context->atoms.ATOM.check = check_##CHK; \
1263 context->atoms.ATOM.dirty = GL_FALSE; \
1264 context->atoms.ATOM.emit = (EMIT); \
1265 context->radeon.hw.max_state_size += (SZ); \
1266 insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1267 } while (0)
1268
1269 static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
1270 {
1271 radeon->query.queryobj.cmd_size = (SZ);
1272 radeon->query.queryobj.cmd = NULL;
1273 radeon->query.queryobj.name = "queryobj";
1274 radeon->query.queryobj.idx = 0;
1275 radeon->query.queryobj.check = check_queryobj;
1276 radeon->query.queryobj.dirty = GL_FALSE;
1277 radeon->query.queryobj.emit = r700SendQueryBegin;
1278 radeon->hw.max_state_size += (SZ);
1279 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
1280 }
1281
1282 void r600InitAtoms(context_t *context)
1283 {
1284 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1285 context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1286
1287 /* Setup the atom linked list */
1288 make_empty_list(&context->radeon.hw.atomlist);
1289 context->radeon.hw.atomlist.name = "atom-list";
1290
1291 ALLOC_STATE(sq, always, 34, r700SendSQConfig);
1292 ALLOC_STATE(db, always, 17, r700SendDBState);
1293 ALLOC_STATE(stencil, always, 4, r700SendStencilState);
1294 ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
1295 ALLOC_STATE(sc, always, 15, r700SendSCState);
1296 ALLOC_STATE(scissor, always, 22, r700SendScissorState);
1297 ALLOC_STATE(aa, always, 12, r700SendAAState);
1298 ALLOC_STATE(cl, always, 12, r700SendCLState);
1299 ALLOC_STATE(gb, always, 6, r700SendGBState);
1300 ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
1301 ALLOC_STATE(su, always, 9, r700SendSUState);
1302 ALLOC_STATE(poly, always, 10, r700SendPolyState);
1303 ALLOC_STATE(cb, cb, 18, r700SendCBState);
1304 ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
1305 ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
1306 ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
1307 ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState);
1308 ALLOC_STATE(sx, always, 9, r700SendSXState);
1309 ALLOC_STATE(vgt, always, 41, r700SendVGTState);
1310 ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
1311 ALLOC_STATE(vpt, always, 16, r700SendViewportState);
1312 ALLOC_STATE(fs, always, 18, r700SendFSState);
1313 ALLOC_STATE(vs, always, 18, r700SendVSState);
1314 ALLOC_STATE(ps, always, 21, r700SendPSState);
1315 ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
1316 ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
1317 ALLOC_STATE(vtx, vtx, (6 + (VERT_ATTRIB_MAX * 18)), r700SendVTXState);
1318 ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
1319 ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
1320 ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
1321 r600_init_query_stateobj(&context->radeon, 6 * 2);
1322
1323 context->radeon.hw.is_dirty = GL_TRUE;
1324 context->radeon.hw.all_dirty = GL_TRUE;
1325 }