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Merge branch 'master' into glsl2
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30 #include "main/simple_list.h"
31
32 #include "r600_context.h"
33 #include "r600_cmdbuf.h"
34
35 #include "r600_tex.h"
36 #include "r700_oglprog.h"
37 #include "r700_fragprog.h"
38 #include "r700_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
43 {
44 context_t *context = R700_CONTEXT(ctx);
45 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
46
47 struct r700_vertex_program *vp = context->selected_vp;
48
49 struct radeon_bo *bo = NULL;
50 unsigned int i;
51 BATCH_LOCALS(&context->radeon);
52
53 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
54
55 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
56 if (ctx->Texture.Unit[i]._ReallyEnabled) {
57 radeonTexObj *t = r700->textures[i];
58 if (t) {
59 if (!t->image_override) {
60 bo = t->mt->bo;
61 } else {
62 bo = t->bo;
63 }
64 if (bo) {
65
66 r700SyncSurf(context, bo,
67 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
68 0, TC_ACTION_ENA_bit);
69
70 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
71 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
72
73 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
74 { /* vs texture */
75 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
76 }
77 else
78 {
79 R600_OUT_BATCH(i * 7);
80 }
81
82 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
83 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
84 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
85 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
86 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
87 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
88 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
89 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
90 bo,
91 r700->textures[i]->SQ_TEX_RESOURCE2,
92 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
93 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
94 bo,
95 r700->textures[i]->SQ_TEX_RESOURCE3,
96 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
97 END_BATCH();
98 COMMIT_BATCH();
99 }
100 }
101 }
102 }
103 }
104
105 #define SAMPLER_STRIDE 3
106
107 static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
108 {
109 context_t *context = R700_CONTEXT(ctx);
110 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
111 unsigned int i;
112
113 struct r700_vertex_program *vp = context->selected_vp;
114
115 BATCH_LOCALS(&context->radeon);
116 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
117
118 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
119 if (ctx->Texture.Unit[i]._ReallyEnabled) {
120 radeonTexObj *t = r700->textures[i];
121 if (t) {
122 BEGIN_BATCH_NO_AUTOSTATE(5);
123 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
124
125 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
126 { /* vs texture */
127 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * SAMPLER_STRIDE); //work 1
128 }
129 else
130 {
131 R600_OUT_BATCH(i * 3);
132 }
133
134 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
135 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
136 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
137 END_BATCH();
138 COMMIT_BATCH();
139 }
140 }
141 }
142 }
143
144 static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
145 {
146 context_t *context = R700_CONTEXT(ctx);
147 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
148 unsigned int i;
149 BATCH_LOCALS(&context->radeon);
150 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
151
152 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
153 if (ctx->Texture.Unit[i]._ReallyEnabled) {
154 radeonTexObj *t = r700->textures[i];
155 if (t) {
156 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
157 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
158 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
159 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
160 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
161 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
162 END_BATCH();
163 COMMIT_BATCH();
164 }
165 }
166 }
167 }
168
169 extern int getTypeSize(GLenum type);
170 static void r700SetupVTXConstants(GLcontext * ctx,
171 void * pAos,
172 StreamDesc * pStreamDesc)
173 {
174 context_t *context = R700_CONTEXT(ctx);
175 struct radeon_aos * paos = (struct radeon_aos *)pAos;
176 unsigned int nVBsize;
177 BATCH_LOCALS(&context->radeon);
178
179 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
180 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
181 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
182 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
183 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
184
185 if (!paos->bo)
186 return;
187
188 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
189 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
190 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
191 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
192 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
193 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
194 else
195 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
196
197 if(0 == pStreamDesc->stride)
198 {
199 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
200 }
201 else
202 {
203 nVBsize = (paos->count - 1) * pStreamDesc->stride
204 + pStreamDesc->size * getTypeSize(pStreamDesc->type);
205 }
206
207 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
208 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize - 1;
209
210 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
211 SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
212 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
213 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
214 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
215 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
216
217 if(GL_TRUE == pStreamDesc->normalize)
218 {
219 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
220 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
221 }
222 else
223 {
224 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
225 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
226 }
227
228 if(1 == pStreamDesc->_signed)
229 {
230 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
231 }
232
233 SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
234 SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
235 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
236
237 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
238
239 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
240 R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
241 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
242 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
243 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
244 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
245 R600_OUT_BATCH(0);
246 R600_OUT_BATCH(0);
247 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
248 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
249 paos->bo,
250 uSQ_VTX_CONSTANT_WORD0_0,
251 RADEON_GEM_DOMAIN_GTT, 0, 0);
252 END_BATCH();
253 COMMIT_BATCH();
254
255 }
256
257 static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
258 {
259 context_t *context = R700_CONTEXT(ctx);
260 struct r700_vertex_program *vp = context->selected_vp;
261 unsigned int i, j = 0;
262 BATCH_LOCALS(&context->radeon);
263 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
264
265 if (context->radeon.tcl.aos_count == 0)
266 return;
267
268 BEGIN_BATCH_NO_AUTOSTATE(6);
269 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
270 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
271 R600_OUT_BATCH(0);
272
273 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
274 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
275 R600_OUT_BATCH(0);
276 END_BATCH();
277 COMMIT_BATCH();
278
279 for(i=0; i<VERT_ATTRIB_MAX; i++) {
280 if(vp->mesa_program->Base.InputsRead & (1 << i))
281 {
282 r700SetupVTXConstants(ctx,
283 (void*)(&context->radeon.tcl.aos[j]),
284 &(context->stream_desc[j]));
285 j++;
286 }
287 }
288 }
289
290 static void r700SetRenderTarget(context_t *context, int id)
291 {
292 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
293 uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM;
294 struct radeon_renderbuffer *rrb;
295 unsigned int nPitchInPixel;
296
297 rrb = radeon_get_colorbuffer(&context->radeon);
298 if (!rrb || !rrb->bo) {
299 return;
300 }
301
302 R600_STATECHANGE(context, cb_target);
303
304 /* color buffer */
305 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
306
307 nPitchInPixel = rrb->pitch/rrb->cpp;
308 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
309 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
310 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
311 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
312 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
313 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
314 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
315
316 switch (rrb->base.Format) {
317 case MESA_FORMAT_RGBA8888:
318 format = COLOR_8_8_8_8;
319 comp_swap = SWAP_STD_REV;
320 number_type = NUMBER_UNORM;
321 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
322 break;
323 case MESA_FORMAT_SIGNED_RGBA8888:
324 format = COLOR_8_8_8_8;
325 comp_swap = SWAP_STD_REV;
326 number_type = NUMBER_SNORM;
327 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
328 break;
329 case MESA_FORMAT_RGBA8888_REV:
330 format = COLOR_8_8_8_8;
331 comp_swap = SWAP_STD;
332 number_type = NUMBER_UNORM;
333 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
334 break;
335 case MESA_FORMAT_SIGNED_RGBA8888_REV:
336 format = COLOR_8_8_8_8;
337 comp_swap = SWAP_STD;
338 number_type = NUMBER_SNORM;
339 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
340 break;
341 case MESA_FORMAT_ARGB8888:
342 case MESA_FORMAT_XRGB8888:
343 format = COLOR_8_8_8_8;
344 comp_swap = SWAP_ALT;
345 number_type = NUMBER_UNORM;
346 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
347 break;
348 case MESA_FORMAT_ARGB8888_REV:
349 case MESA_FORMAT_XRGB8888_REV:
350 format = COLOR_8_8_8_8;
351 comp_swap = SWAP_ALT_REV;
352 number_type = NUMBER_UNORM;
353 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
354 break;
355 case MESA_FORMAT_RGB565:
356 format = COLOR_5_6_5;
357 comp_swap = SWAP_STD_REV;
358 number_type = NUMBER_UNORM;
359 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
360 break;
361 case MESA_FORMAT_RGB565_REV:
362 format = COLOR_5_6_5;
363 comp_swap = SWAP_STD;
364 number_type = NUMBER_UNORM;
365 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
366 break;
367 case MESA_FORMAT_ARGB4444:
368 format = COLOR_4_4_4_4;
369 comp_swap = SWAP_ALT;
370 number_type = NUMBER_UNORM;
371 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
372 break;
373 case MESA_FORMAT_ARGB4444_REV:
374 format = COLOR_4_4_4_4;
375 comp_swap = SWAP_ALT_REV;
376 number_type = NUMBER_UNORM;
377 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
378 break;
379 case MESA_FORMAT_ARGB1555:
380 format = COLOR_1_5_5_5;
381 comp_swap = SWAP_ALT;
382 number_type = NUMBER_UNORM;
383 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
384 break;
385 case MESA_FORMAT_ARGB1555_REV:
386 format = COLOR_1_5_5_5;
387 comp_swap = SWAP_ALT_REV;
388 number_type = NUMBER_UNORM;
389 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
390 break;
391 case MESA_FORMAT_AL88:
392 format = COLOR_8_8;
393 comp_swap = SWAP_STD;
394 number_type = NUMBER_UNORM;
395 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
396 break;
397 case MESA_FORMAT_AL88_REV:
398 format = COLOR_8_8;
399 comp_swap = SWAP_STD_REV;
400 number_type = NUMBER_UNORM;
401 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
402 break;
403 case MESA_FORMAT_RGB332:
404 format = COLOR_3_3_2;
405 comp_swap = SWAP_STD_REV;
406 number_type = NUMBER_UNORM;
407 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
408 break;
409 case MESA_FORMAT_A8:
410 format = COLOR_8;
411 comp_swap = SWAP_ALT_REV;
412 number_type = NUMBER_UNORM;
413 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
414 break;
415 case MESA_FORMAT_I8:
416 case MESA_FORMAT_CI8:
417 format = COLOR_8;
418 comp_swap = SWAP_STD;
419 number_type = NUMBER_UNORM;
420 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
421 break;
422 case MESA_FORMAT_L8:
423 format = COLOR_8;
424 comp_swap = SWAP_ALT;
425 number_type = NUMBER_UNORM;
426 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
427 break;
428 case MESA_FORMAT_RGBA_FLOAT32:
429 format = COLOR_32_32_32_32_FLOAT;
430 comp_swap = SWAP_STD_REV;
431 number_type = NUMBER_FLOAT;
432 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
433 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
434 break;
435 case MESA_FORMAT_RGBA_FLOAT16:
436 format = COLOR_16_16_16_16_FLOAT;
437 comp_swap = SWAP_STD_REV;
438 number_type = NUMBER_FLOAT;
439 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
440 break;
441 case MESA_FORMAT_ALPHA_FLOAT32:
442 format = COLOR_32_FLOAT;
443 comp_swap = SWAP_ALT_REV;
444 number_type = NUMBER_FLOAT;
445 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
446 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
447 break;
448 case MESA_FORMAT_ALPHA_FLOAT16:
449 format = COLOR_16_FLOAT;
450 comp_swap = SWAP_ALT_REV;
451 number_type = NUMBER_FLOAT;
452 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
453 break;
454 case MESA_FORMAT_LUMINANCE_FLOAT32:
455 format = COLOR_32_FLOAT;
456 comp_swap = SWAP_ALT;
457 number_type = NUMBER_FLOAT;
458 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
459 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
460 break;
461 case MESA_FORMAT_LUMINANCE_FLOAT16:
462 format = COLOR_16_FLOAT;
463 comp_swap = SWAP_ALT;
464 number_type = NUMBER_FLOAT;
465 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
466 break;
467 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
468 format = COLOR_32_32_FLOAT;
469 comp_swap = SWAP_ALT_REV;
470 number_type = NUMBER_FLOAT;
471 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
472 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
473 break;
474 case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
475 format = COLOR_16_16_FLOAT;
476 comp_swap = SWAP_ALT_REV;
477 number_type = NUMBER_FLOAT;
478 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
479 break;
480 case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
481 format = COLOR_32_FLOAT;
482 comp_swap = SWAP_STD;
483 number_type = NUMBER_FLOAT;
484 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
485 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
486 break;
487 case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
488 format = COLOR_16_FLOAT;
489 comp_swap = SWAP_STD;
490 number_type = NUMBER_UNORM;
491 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
492 break;
493 case MESA_FORMAT_X8_Z24:
494 case MESA_FORMAT_S8_Z24:
495 format = COLOR_8_24;
496 comp_swap = SWAP_STD;
497 number_type = NUMBER_UNORM;
498 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
499 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
500 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
501 break;
502 case MESA_FORMAT_Z24_S8:
503 format = COLOR_24_8;
504 comp_swap = SWAP_STD;
505 number_type = NUMBER_UNORM;
506 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
507 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
508 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
509 break;
510 case MESA_FORMAT_Z16:
511 format = COLOR_16;
512 comp_swap = SWAP_STD;
513 number_type = NUMBER_UNORM;
514 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
515 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
516 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
517 break;
518 case MESA_FORMAT_Z32:
519 format = COLOR_32;
520 comp_swap = SWAP_STD;
521 number_type = NUMBER_UNORM;
522 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
523 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
524 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
525 break;
526 case MESA_FORMAT_SRGBA8:
527 format = COLOR_8_8_8_8;
528 comp_swap = SWAP_STD_REV;
529 number_type = NUMBER_SRGB;
530 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
531 break;
532 case MESA_FORMAT_SLA8:
533 format = COLOR_8_8;
534 comp_swap = SWAP_ALT_REV;
535 number_type = NUMBER_SRGB;
536 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
537 break;
538 case MESA_FORMAT_SL8:
539 format = COLOR_8;
540 comp_swap = SWAP_ALT_REV;
541 number_type = NUMBER_SRGB;
542 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
543 break;
544 default:
545 _mesa_problem(context->radeon.glCtx, "unexpected format in r700SetRenderTarget()");
546 break;
547 }
548
549 /* must be 0 on r7xx */
550 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
551 CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
552
553 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, format,
554 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
555 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, comp_swap,
556 COMP_SWAP_shift, COMP_SWAP_mask);
557 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, number_type,
558 NUMBER_TYPE_shift, NUMBER_TYPE_mask);
559 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
560
561 r700->render_target[id].enabled = GL_TRUE;
562 }
563
564 static void r700SetDepthTarget(context_t *context)
565 {
566 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
567
568 struct radeon_renderbuffer *rrb;
569 unsigned int nPitchInPixel;
570
571 rrb = radeon_get_depthbuffer(&context->radeon);
572 if (!rrb)
573 return;
574
575 R600_STATECHANGE(context, db_target);
576
577 /* depth buf */
578 r700->DB_DEPTH_SIZE.u32All = 0;
579 r700->DB_DEPTH_BASE.u32All = 0;
580 r700->DB_DEPTH_INFO.u32All = 0;
581 r700->DB_DEPTH_VIEW.u32All = 0;
582
583 nPitchInPixel = rrb->pitch/rrb->cpp;
584
585 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
586 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
587 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
588 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
589
590 if(4 == rrb->cpp)
591 {
592 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
593 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
594 }
595 else
596 {
597 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
598 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
599 }
600 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
601 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
602 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
603 }
604
605 static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
606 {
607 context_t *context = R700_CONTEXT(ctx);
608 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
609 struct radeon_renderbuffer *rrb;
610 BATCH_LOCALS(&context->radeon);
611 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
612
613 rrb = radeon_get_depthbuffer(&context->radeon);
614 if (!rrb || !rrb->bo) {
615 return;
616 }
617
618 r700SetDepthTarget(context);
619
620 BEGIN_BATCH_NO_AUTOSTATE(7 + 2);
621 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
622 R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
623 R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
624 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1);
625 R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
626 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
627 rrb->bo,
628 r700->DB_DEPTH_BASE.u32All,
629 0, RADEON_GEM_DOMAIN_VRAM, 0);
630 END_BATCH();
631 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
632 R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1);
633 R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
634 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All,
635 rrb->bo,
636 r700->DB_DEPTH_INFO.u32All,
637 0, RADEON_GEM_DOMAIN_VRAM, 0);
638 END_BATCH();
639
640 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
641 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
642 BEGIN_BATCH_NO_AUTOSTATE(2);
643 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
644 R600_OUT_BATCH(1 << 0);
645 END_BATCH();
646 }
647
648 COMMIT_BATCH();
649
650 }
651
652 static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
653 {
654 context_t *context = R700_CONTEXT(ctx);
655 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
656 struct radeon_renderbuffer *rrb;
657 BATCH_LOCALS(&context->radeon);
658 int id = 0;
659 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
660
661 rrb = radeon_get_colorbuffer(&context->radeon);
662 if (!rrb || !rrb->bo) {
663 return;
664 }
665
666 r700SetRenderTarget(context, 0);
667
668 if (id > R700_MAX_RENDER_TARGETS)
669 return;
670
671 if (!r700->render_target[id].enabled)
672 return;
673
674 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
675 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
676 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
677 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
678 rrb->bo,
679 r700->render_target[id].CB_COLOR0_BASE.u32All,
680 0, RADEON_GEM_DOMAIN_VRAM, 0);
681 END_BATCH();
682
683 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
684 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
685 BEGIN_BATCH_NO_AUTOSTATE(2);
686 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
687 R600_OUT_BATCH((2 << id));
688 END_BATCH();
689 }
690 /* Set CMASK & TILE buffer to the offset of color buffer as
691 * we don't use those this shouldn't cause any issue and we
692 * then have a valid cmd stream
693 */
694 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
695 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
696 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
697 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All,
698 rrb->bo,
699 r700->render_target[id].CB_COLOR0_TILE.u32All,
700 0, RADEON_GEM_DOMAIN_VRAM, 0);
701 END_BATCH();
702 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
703 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
704 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All);
705 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_FRAG.u32All,
706 rrb->bo,
707 r700->render_target[id].CB_COLOR0_FRAG.u32All,
708 0, RADEON_GEM_DOMAIN_VRAM, 0);
709 END_BATCH();
710
711 BEGIN_BATCH_NO_AUTOSTATE(9);
712 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
713 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
714 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
715 END_BATCH();
716
717 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
718 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
719 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_INFO.u32All,
720 rrb->bo,
721 r700->render_target[id].CB_COLOR0_INFO.u32All,
722 0, RADEON_GEM_DOMAIN_VRAM, 0);
723
724 END_BATCH();
725
726 COMMIT_BATCH();
727
728 }
729
730 static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
731 {
732 context_t *context = R700_CONTEXT(ctx);
733 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
734 struct radeon_bo * pbo;
735 BATCH_LOCALS(&context->radeon);
736 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
737
738 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
739
740 if (!pbo)
741 return;
742
743 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
744
745 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
746 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
747 R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
748 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
749 pbo,
750 r700->ps.SQ_PGM_START_PS.u32All,
751 RADEON_GEM_DOMAIN_GTT, 0, 0);
752 END_BATCH();
753
754 BEGIN_BATCH_NO_AUTOSTATE(9);
755 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
756 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
757 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
758 END_BATCH();
759
760 BEGIN_BATCH_NO_AUTOSTATE(3);
761 R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
762 END_BATCH();
763
764 COMMIT_BATCH();
765
766 }
767
768 static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
769 {
770 context_t *context = R700_CONTEXT(ctx);
771 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
772 struct radeon_bo * pbo;
773 BATCH_LOCALS(&context->radeon);
774 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
775
776 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
777
778 if (!pbo)
779 return;
780
781 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
782
783 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
784 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
785 R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
786 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
787 pbo,
788 r700->vs.SQ_PGM_START_VS.u32All,
789 RADEON_GEM_DOMAIN_GTT, 0, 0);
790 END_BATCH();
791
792 BEGIN_BATCH_NO_AUTOSTATE(6);
793 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
794 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
795 END_BATCH();
796
797 BEGIN_BATCH_NO_AUTOSTATE(3);
798 R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
799 //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
800 END_BATCH();
801
802 COMMIT_BATCH();
803 }
804
805 static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
806 {
807 context_t *context = R700_CONTEXT(ctx);
808 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
809 struct radeon_bo * pbo;
810 BATCH_LOCALS(&context->radeon);
811 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
812
813 /* XXX fixme
814 * R6xx chips require a FS be emitted, even if it's not used.
815 * since we aren't using FS yet, just send the VS address to make
816 * the kernel command checker happy
817 */
818 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
819 r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
820 r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
821 r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
822 /* XXX */
823
824 if (!pbo)
825 return;
826
827 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
828
829 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
830 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
831 R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
832 R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
833 pbo,
834 r700->fs.SQ_PGM_START_FS.u32All,
835 RADEON_GEM_DOMAIN_GTT, 0, 0);
836 END_BATCH();
837
838 BEGIN_BATCH_NO_AUTOSTATE(6);
839 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
840 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
841 END_BATCH();
842
843 COMMIT_BATCH();
844
845 }
846
847 static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
848 {
849 context_t *context = R700_CONTEXT(ctx);
850 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
851 BATCH_LOCALS(&context->radeon);
852 int id = 0;
853 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
854
855 if (id > R700_MAX_VIEWPORTS)
856 return;
857
858 if (!r700->viewport[id].enabled)
859 return;
860
861 BEGIN_BATCH_NO_AUTOSTATE(16);
862 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
863 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
864 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
865 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
866 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
867 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
868 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
869 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
870 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
871 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
872 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
873 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
874 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
875 END_BATCH();
876
877 COMMIT_BATCH();
878
879 }
880
881 static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
882 {
883 context_t *context = R700_CONTEXT(ctx);
884 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
885 BATCH_LOCALS(&context->radeon);
886 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
887
888 BEGIN_BATCH_NO_AUTOSTATE(34);
889 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
890 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
891 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
892 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
893 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
894 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
895 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
896
897 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
898 R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
899 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
900 R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
901 R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
902
903 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
904 R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
905 R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
906 R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
907 R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
908 R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
909 R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
910 R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
911 R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
912 R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
913 END_BATCH();
914
915 COMMIT_BATCH();
916 }
917
918 static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
919 {
920 context_t *context = R700_CONTEXT(ctx);
921 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
922 BATCH_LOCALS(&context->radeon);
923 int i;
924 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
925
926 for (i = 0; i < R700_MAX_UCP; i++) {
927 if (r700->ucp[i].enabled) {
928 BEGIN_BATCH_NO_AUTOSTATE(6);
929 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
930 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
931 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
932 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
933 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
934 END_BATCH();
935 COMMIT_BATCH();
936 }
937 }
938 }
939
940 static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
941 {
942 context_t *context = R700_CONTEXT(ctx);
943 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
944 BATCH_LOCALS(&context->radeon);
945 unsigned int ui;
946 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
947
948 BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
949
950 R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
951 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
952 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
953 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
954 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
955 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
956 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
957 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
958 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
959 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
960 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
961 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
962 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
963 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
964 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
965 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
966 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
967 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
968 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
969 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
970 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
971 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
972 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
973 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
974 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
975 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
976 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
977 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
978 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
979 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
980 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
981 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
982 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
983
984 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
985 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
986 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
987 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
988 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
989 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
990 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
991 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
992 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
993 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
994 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
995
996 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
997 R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
998 R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
999 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
1000 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
1001 R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
1002 R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
1003 R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
1004 R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
1005 R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
1006
1007 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
1008 for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
1009 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
1010
1011 END_BATCH();
1012 COMMIT_BATCH();
1013 }
1014
1015 static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
1016 {
1017 context_t *context = R700_CONTEXT(ctx);
1018 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1019 BATCH_LOCALS(&context->radeon);
1020 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1021
1022 BEGIN_BATCH_NO_AUTOSTATE(41);
1023
1024 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1025 R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
1026 R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
1027 R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
1028 R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
1029
1030 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1031 R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
1032 R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
1033 R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
1034 R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
1035 R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
1036 R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
1037 R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
1038 R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
1039 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
1040 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
1041 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
1042 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
1043 R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
1044
1045 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
1046 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
1047 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
1048 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
1049
1050 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1051 R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
1052 R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
1053 R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
1054
1055 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
1056
1057 END_BATCH();
1058 COMMIT_BATCH();
1059 }
1060
1061 static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
1062 {
1063 context_t *context = R700_CONTEXT(ctx);
1064 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1065 BATCH_LOCALS(&context->radeon);
1066 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1067
1068 BEGIN_BATCH_NO_AUTOSTATE(9);
1069 R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
1070 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
1071 R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
1072 END_BATCH();
1073 COMMIT_BATCH();
1074 }
1075
1076 static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
1077 {
1078 context_t *context = R700_CONTEXT(ctx);
1079 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1080 BATCH_LOCALS(&context->radeon);
1081 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1082
1083 BEGIN_BATCH_NO_AUTOSTATE(17);
1084
1085 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
1086 R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
1087 R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
1088
1089 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
1090 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
1091
1092 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
1093 R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
1094 R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
1095
1096 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
1097
1098 END_BATCH();
1099 COMMIT_BATCH();
1100 }
1101
1102 static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
1103 {
1104 context_t *context = R700_CONTEXT(ctx);
1105 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1106 BATCH_LOCALS(&context->radeon);
1107
1108 BEGIN_BATCH_NO_AUTOSTATE(4);
1109 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
1110 R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
1111 R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
1112 END_BATCH();
1113 COMMIT_BATCH();
1114 }
1115
1116 static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
1117 {
1118 context_t *context = R700_CONTEXT(ctx);
1119 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1120 BATCH_LOCALS(&context->radeon);
1121 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1122
1123 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1124 BEGIN_BATCH_NO_AUTOSTATE(11);
1125 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
1126 R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
1127 R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
1128 R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
1129 R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
1130 R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
1131 R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
1132 R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
1133 R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
1134 END_BATCH();
1135 }
1136
1137 BEGIN_BATCH_NO_AUTOSTATE(7);
1138 R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
1139 R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
1140 R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
1141 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
1142 END_BATCH();
1143 COMMIT_BATCH();
1144 }
1145
1146 static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
1147 {
1148 context_t *context = R700_CONTEXT(ctx);
1149 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1150 BATCH_LOCALS(&context->radeon);
1151
1152 BEGIN_BATCH_NO_AUTOSTATE(6);
1153 R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
1154 R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
1155 R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
1156 R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
1157 R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
1158 END_BATCH();
1159 COMMIT_BATCH();
1160 }
1161
1162 static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
1163 {
1164 context_t *context = R700_CONTEXT(ctx);
1165 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1166 BATCH_LOCALS(&context->radeon);
1167 unsigned int ui;
1168 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1169
1170 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1171 BEGIN_BATCH_NO_AUTOSTATE(3);
1172 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
1173 END_BATCH();
1174 }
1175
1176 BEGIN_BATCH_NO_AUTOSTATE(3);
1177 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
1178 END_BATCH();
1179
1180 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1181 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
1182 if (r700->render_target[ui].enabled) {
1183 BEGIN_BATCH_NO_AUTOSTATE(3);
1184 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
1185 r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
1186 END_BATCH();
1187 }
1188 }
1189 }
1190
1191 COMMIT_BATCH();
1192 }
1193
1194 static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
1195 {
1196 context_t *context = R700_CONTEXT(ctx);
1197 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1198 BATCH_LOCALS(&context->radeon);
1199 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1200
1201 BEGIN_BATCH_NO_AUTOSTATE(6);
1202 R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
1203 R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
1204 R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
1205 R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
1206 R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
1207 END_BATCH();
1208 COMMIT_BATCH();
1209 }
1210
1211 static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
1212 {
1213 context_t *context = R700_CONTEXT(ctx);
1214 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1215 BATCH_LOCALS(&context->radeon);
1216
1217 BEGIN_BATCH_NO_AUTOSTATE(9);
1218 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
1219 R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
1220 R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
1221 R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
1222 R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
1223 R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
1224 END_BATCH();
1225 COMMIT_BATCH();
1226
1227 }
1228
1229 static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
1230 {
1231 context_t *context = R700_CONTEXT(ctx);
1232 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1233 BATCH_LOCALS(&context->radeon);
1234
1235 BEGIN_BATCH_NO_AUTOSTATE(10);
1236 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
1237 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
1238 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
1239 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1240 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
1241 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
1242 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
1243 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
1244 END_BATCH();
1245 COMMIT_BATCH();
1246
1247 }
1248
1249 static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
1250 {
1251 context_t *context = R700_CONTEXT(ctx);
1252 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1253 BATCH_LOCALS(&context->radeon);
1254 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1255
1256 BEGIN_BATCH_NO_AUTOSTATE(12);
1257 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
1258 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
1259 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
1260 R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
1261 END_BATCH();
1262 COMMIT_BATCH();
1263 }
1264
1265 static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
1266 {
1267 context_t *context = R700_CONTEXT(ctx);
1268 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1269 BATCH_LOCALS(&context->radeon);
1270
1271 BEGIN_BATCH_NO_AUTOSTATE(6);
1272 R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
1273 R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
1274 R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
1275 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
1276 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
1277 END_BATCH();
1278 COMMIT_BATCH();
1279 }
1280
1281 static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
1282 {
1283 context_t *context = R700_CONTEXT(ctx);
1284 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1285 BATCH_LOCALS(&context->radeon);
1286 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1287
1288 BEGIN_BATCH_NO_AUTOSTATE(22);
1289 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1290 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
1291 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
1292
1293 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
1294 R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
1295 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
1296 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
1297 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
1298 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
1299 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
1300 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
1301 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
1302 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
1303 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
1304 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
1305 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
1306
1307 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1308 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
1309 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
1310 END_BATCH();
1311 COMMIT_BATCH();
1312 }
1313
1314 static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
1315 {
1316 context_t *context = R700_CONTEXT(ctx);
1317 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1318 BATCH_LOCALS(&context->radeon);
1319 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1320
1321 BEGIN_BATCH_NO_AUTOSTATE(15);
1322 R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
1323 R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
1324 R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
1325 R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
1326 R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
1327 END_BATCH();
1328 COMMIT_BATCH();
1329 }
1330
1331 static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
1332 {
1333 context_t *context = R700_CONTEXT(ctx);
1334 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1335 BATCH_LOCALS(&context->radeon);
1336
1337 BEGIN_BATCH_NO_AUTOSTATE(12);
1338 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
1339 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
1340 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
1341 R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
1342 END_BATCH();
1343 COMMIT_BATCH();
1344 }
1345
1346 static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1347 {
1348 context_t *context = R700_CONTEXT(ctx);
1349 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1350 int i;
1351 BATCH_LOCALS(&context->radeon);
1352
1353 if (r700->ps.num_consts == 0)
1354 return;
1355
1356 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
1357 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
1358 /* assembler map const from very beginning. */
1359 R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
1360 for (i = 0; i < r700->ps.num_consts; i++) {
1361 R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
1362 R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
1363 R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
1364 R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
1365 }
1366 END_BATCH();
1367 COMMIT_BATCH();
1368 }
1369
1370 static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1371 {
1372 context_t *context = R700_CONTEXT(ctx);
1373 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1374 int i;
1375 BATCH_LOCALS(&context->radeon);
1376 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1377
1378 if (r700->vs.num_consts == 0)
1379 return;
1380
1381 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
1382 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
1383 /* assembler map const from very beginning. */
1384 R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
1385 for (i = 0; i < r700->vs.num_consts; i++) {
1386 R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
1387 R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
1388 R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
1389 R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
1390 }
1391 END_BATCH();
1392 COMMIT_BATCH();
1393 }
1394
1395 static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
1396 {
1397 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1398 struct radeon_query_object *query = radeon->query.current;
1399 BATCH_LOCALS(radeon);
1400 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1401
1402 /* clear the buffer */
1403 radeon_bo_map(query->bo, GL_FALSE);
1404 memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
1405 radeon_bo_unmap(query->bo);
1406
1407 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
1408 query->bo,
1409 0, RADEON_GEM_DOMAIN_GTT);
1410
1411 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
1412 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
1413 R600_OUT_BATCH(ZPASS_DONE);
1414 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
1415 R600_OUT_BATCH(0x00000000);
1416 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
1417 END_BATCH();
1418 query->emitted_begin = GL_TRUE;
1419 }
1420
1421 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
1422 {
1423 return atom->cmd_size;
1424 }
1425
1426 static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
1427 {
1428 context_t *context = R700_CONTEXT(ctx);
1429 int count = 7;
1430
1431 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1432 count += 11;
1433 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1434
1435 return count;
1436 }
1437
1438 static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
1439 {
1440 context_t *context = R700_CONTEXT(ctx);
1441 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1442 unsigned int ui;
1443 int count = 3;
1444
1445 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1446 count += 3;
1447
1448 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1449 /* targets are enabled in r700SetRenderTarget but state
1450 size is calculated before that. Until MRT's are done
1451 hardcode target0 as enabled. */
1452 count += 3;
1453 for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) {
1454 if (r700->render_target[ui].enabled)
1455 count += 3;
1456 }
1457 }
1458 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1459
1460 return count;
1461 }
1462
1463 static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
1464 {
1465 context_t *context = R700_CONTEXT(ctx);
1466 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1467 int i;
1468 int count = 0;
1469
1470 for (i = 0; i < R700_MAX_UCP; i++) {
1471 if (r700->ucp[i].enabled)
1472 count += 6;
1473 }
1474 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1475 return count;
1476 }
1477
1478 static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
1479 {
1480 context_t *context = R700_CONTEXT(ctx);
1481 int count = context->radeon.tcl.aos_count * 18;
1482
1483 if (count)
1484 count += 6;
1485
1486 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1487 return count;
1488 }
1489
1490 static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
1491 {
1492 context_t *context = R700_CONTEXT(ctx);
1493 unsigned int i, count = 0;
1494 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1495
1496 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
1497 if (ctx->Texture.Unit[i]._ReallyEnabled) {
1498 radeonTexObj *t = r700->textures[i];
1499 if (t)
1500 count++;
1501 }
1502 }
1503 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1504 return count * 31;
1505 }
1506
1507 static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1508 {
1509 context_t *context = R700_CONTEXT(ctx);
1510 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1511 int count = r700->ps.num_consts * 4;
1512
1513 if (count)
1514 count += 2;
1515 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1516
1517 return count;
1518 }
1519
1520 static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1521 {
1522 context_t *context = R700_CONTEXT(ctx);
1523 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1524 int count = r700->vs.num_consts * 4;
1525
1526 if (count)
1527 count += 2;
1528 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1529
1530 return count;
1531 }
1532
1533 static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
1534 {
1535 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1536 struct radeon_query_object *query = radeon->query.current;
1537 int count;
1538
1539 if (!query || query->emitted_begin)
1540 count = 0;
1541 else
1542 count = atom->cmd_size;
1543 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1544 return count;
1545 }
1546
1547 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
1548 do { \
1549 context->atoms.ATOM.cmd_size = (SZ); \
1550 context->atoms.ATOM.cmd = NULL; \
1551 context->atoms.ATOM.name = #ATOM; \
1552 context->atoms.ATOM.idx = 0; \
1553 context->atoms.ATOM.check = check_##CHK; \
1554 context->atoms.ATOM.dirty = GL_FALSE; \
1555 context->atoms.ATOM.emit = (EMIT); \
1556 context->radeon.hw.max_state_size += (SZ); \
1557 insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1558 } while (0)
1559
1560 static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
1561 {
1562 radeon->query.queryobj.cmd_size = (SZ);
1563 radeon->query.queryobj.cmd = NULL;
1564 radeon->query.queryobj.name = "queryobj";
1565 radeon->query.queryobj.idx = 0;
1566 radeon->query.queryobj.check = check_queryobj;
1567 radeon->query.queryobj.dirty = GL_FALSE;
1568 radeon->query.queryobj.emit = r700SendQueryBegin;
1569 radeon->hw.max_state_size += (SZ);
1570 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
1571 }
1572
1573 void r600InitAtoms(context_t *context)
1574 {
1575 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1576 context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1577
1578 /* Setup the atom linked list */
1579 make_empty_list(&context->radeon.hw.atomlist);
1580 context->radeon.hw.atomlist.name = "atom-list";
1581
1582 ALLOC_STATE(sq, always, 34, r700SendSQConfig);
1583 ALLOC_STATE(db, always, 17, r700SendDBState);
1584 ALLOC_STATE(stencil, always, 4, r700SendStencilState);
1585 ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState);
1586 ALLOC_STATE(sc, always, 15, r700SendSCState);
1587 ALLOC_STATE(scissor, always, 22, r700SendScissorState);
1588 ALLOC_STATE(aa, always, 12, r700SendAAState);
1589 ALLOC_STATE(cl, always, 12, r700SendCLState);
1590 ALLOC_STATE(gb, always, 6, r700SendGBState);
1591 ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
1592 ALLOC_STATE(su, always, 9, r700SendSUState);
1593 ALLOC_STATE(poly, always, 10, r700SendPolyState);
1594 ALLOC_STATE(cb, cb, 18, r700SendCBState);
1595 ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
1596 ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState);
1597 ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
1598 ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
1599 ALLOC_STATE(sx, always, 9, r700SendSXState);
1600 ALLOC_STATE(vgt, always, 41, r700SendVGTState);
1601 ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
1602 ALLOC_STATE(vpt, always, 16, r700SendViewportState);
1603 ALLOC_STATE(fs, always, 18, r700SendFSState);
1604 ALLOC_STATE(vs, always, 21, r700SendVSState);
1605 ALLOC_STATE(ps, always, 24, r700SendPSState);
1606 ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
1607 ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
1608 ALLOC_STATE(vtx, vtx, (6 + (VERT_ATTRIB_MAX * 18)), r700SendVTXState);
1609 ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
1610 ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
1611 ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
1612 r600_init_query_stateobj(&context->radeon, 6 * 2);
1613
1614 context->radeon.hw.is_dirty = GL_TRUE;
1615 context->radeon.hw.all_dirty = GL_TRUE;
1616 }