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r600: proper fix for 15601835361e2fdd34b38b265cfc3007749ee24d
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30 #include "main/simple_list.h"
31
32 #include "r600_context.h"
33 #include "r600_cmdbuf.h"
34
35 #include "r600_tex.h"
36 #include "r700_oglprog.h"
37 #include "r700_fragprog.h"
38 #include "r700_vertprog.h"
39
40 #include "radeon_mipmap_tree.h"
41
42 static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
43 {
44 context_t *context = R700_CONTEXT(ctx);
45 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
46
47 struct r700_vertex_program *vp = context->selected_vp;
48
49 struct radeon_bo *bo = NULL;
50 unsigned int i;
51 BATCH_LOCALS(&context->radeon);
52
53 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
54
55 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
56 if (ctx->Texture.Unit[i]._ReallyEnabled) {
57 radeonTexObj *t = r700->textures[i];
58 if (t) {
59 if (!t->image_override) {
60 bo = t->mt->bo;
61 } else {
62 bo = t->bo;
63 }
64 if (bo) {
65
66 r700SyncSurf(context, bo,
67 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
68 0, TC_ACTION_ENA_bit);
69
70 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
71 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
72
73 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
74 { /* vs texture */
75 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
76 }
77 else
78 {
79 R600_OUT_BATCH(i * 7);
80 }
81
82 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
83 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
84 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
85 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
86 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
87 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
88 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
89 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
90 bo,
91 r700->textures[i]->SQ_TEX_RESOURCE2,
92 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
93 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
94 bo,
95 r700->textures[i]->SQ_TEX_RESOURCE3,
96 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
97 END_BATCH();
98 COMMIT_BATCH();
99 }
100 }
101 }
102 }
103 }
104
105 #define SAMPLER_STRIDE 3
106
107 static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
108 {
109 context_t *context = R700_CONTEXT(ctx);
110 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
111 unsigned int i;
112
113 struct r700_vertex_program *vp = context->selected_vp;
114
115 BATCH_LOCALS(&context->radeon);
116 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
117
118 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
119 if (ctx->Texture.Unit[i]._ReallyEnabled) {
120 radeonTexObj *t = r700->textures[i];
121 if (t) {
122 BEGIN_BATCH_NO_AUTOSTATE(5);
123 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
124
125 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
126 { /* vs texture */
127 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * SAMPLER_STRIDE); //work 1
128 }
129 else
130 {
131 R600_OUT_BATCH(i * 3);
132 }
133
134 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
135 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
136 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
137 END_BATCH();
138 COMMIT_BATCH();
139 }
140 }
141 }
142 }
143
144 static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
145 {
146 context_t *context = R700_CONTEXT(ctx);
147 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
148 unsigned int i;
149 BATCH_LOCALS(&context->radeon);
150 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
151
152 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
153 if (ctx->Texture.Unit[i]._ReallyEnabled) {
154 radeonTexObj *t = r700->textures[i];
155 if (t) {
156 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
157 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
158 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
159 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
160 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
161 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
162 END_BATCH();
163 COMMIT_BATCH();
164 }
165 }
166 }
167 }
168
169 extern int getTypeSize(GLenum type);
170 static void r700SetupVTXConstants(GLcontext * ctx,
171 void * pAos,
172 StreamDesc * pStreamDesc)
173 {
174 context_t *context = R700_CONTEXT(ctx);
175 struct radeon_aos * paos = (struct radeon_aos *)pAos;
176 unsigned int nVBsize;
177 BATCH_LOCALS(&context->radeon);
178
179 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
180 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
181 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
182 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
183 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
184
185 if (!paos->bo)
186 return;
187
188 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
189 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
190 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
191 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
192 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
193 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
194 else
195 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
196
197 if(0 == pStreamDesc->stride)
198 {
199 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
200 }
201 else
202 {
203 nVBsize = (paos->count - 1) * pStreamDesc->stride
204 + pStreamDesc->size * getTypeSize(pStreamDesc->type);
205 }
206
207 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
208 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize - 1;
209
210 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
211 SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
212 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
213 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
214 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
215 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
216
217 if(GL_TRUE == pStreamDesc->normalize)
218 {
219 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
220 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
221 }
222 else
223 {
224 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
225 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
226 }
227
228 if(1 == pStreamDesc->_signed)
229 {
230 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
231 }
232
233 SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
234 SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
235 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
236
237 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
238
239 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
240 R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
241 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
242 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
243 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
244 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
245 R600_OUT_BATCH(0);
246 R600_OUT_BATCH(0);
247 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
248 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
249 paos->bo,
250 uSQ_VTX_CONSTANT_WORD0_0,
251 RADEON_GEM_DOMAIN_GTT, 0, 0);
252 END_BATCH();
253 COMMIT_BATCH();
254
255 }
256
257 static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
258 {
259 context_t *context = R700_CONTEXT(ctx);
260 struct r700_vertex_program *vp = context->selected_vp;
261 unsigned int i, j = 0;
262 BATCH_LOCALS(&context->radeon);
263 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
264
265 if (context->radeon.tcl.aos_count == 0)
266 return;
267
268 BEGIN_BATCH_NO_AUTOSTATE(6);
269 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
270 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
271 R600_OUT_BATCH(0);
272
273 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
274 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
275 R600_OUT_BATCH(0);
276 END_BATCH();
277 COMMIT_BATCH();
278
279 for(i=0; i<VERT_ATTRIB_MAX; i++) {
280 if(vp->mesa_program->Base.InputsRead & (1 << i))
281 {
282 r700SetupVTXConstants(ctx,
283 (void*)(&context->radeon.tcl.aos[j]),
284 &(context->stream_desc[j]));
285 j++;
286 }
287 }
288 }
289
290 static void r700SetRenderTarget(context_t *context, int id)
291 {
292 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
293
294 struct radeon_renderbuffer *rrb;
295 unsigned int nPitchInPixel;
296
297 rrb = radeon_get_colorbuffer(&context->radeon);
298 if (!rrb || !rrb->bo) {
299 return;
300 }
301
302 R600_STATECHANGE(context, cb_target);
303
304 /* color buffer */
305 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
306
307 nPitchInPixel = rrb->pitch/rrb->cpp;
308 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
309 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
310 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
311 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
312 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
313 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
314 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
315 if(4 == rrb->cpp)
316 {
317 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
318 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
319 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
320 }
321 else
322 {
323 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
324 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
325 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
326 COMP_SWAP_shift, COMP_SWAP_mask);
327 }
328 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
329 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
330 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
331
332 r700->render_target[id].enabled = GL_TRUE;
333 }
334
335 static void r700SetDepthTarget(context_t *context)
336 {
337 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
338
339 struct radeon_renderbuffer *rrb;
340 unsigned int nPitchInPixel;
341
342 rrb = radeon_get_depthbuffer(&context->radeon);
343 if (!rrb)
344 return;
345
346 R600_STATECHANGE(context, db_target);
347
348 /* depth buf */
349 r700->DB_DEPTH_SIZE.u32All = 0;
350 r700->DB_DEPTH_BASE.u32All = 0;
351 r700->DB_DEPTH_INFO.u32All = 0;
352 r700->DB_DEPTH_VIEW.u32All = 0;
353
354 nPitchInPixel = rrb->pitch/rrb->cpp;
355
356 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
357 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
358 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
359 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
360
361 if(4 == rrb->cpp)
362 {
363 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
364 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
365 }
366 else
367 {
368 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
369 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
370 }
371 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
372 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
373 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
374 }
375
376 static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
377 {
378 context_t *context = R700_CONTEXT(ctx);
379 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
380 struct radeon_renderbuffer *rrb;
381 BATCH_LOCALS(&context->radeon);
382 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
383
384 rrb = radeon_get_depthbuffer(&context->radeon);
385 if (!rrb || !rrb->bo) {
386 return;
387 }
388
389 r700SetDepthTarget(context);
390
391 BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
392 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
393 R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
394 R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
395 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
396 R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
397 R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
398 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
399 rrb->bo,
400 r700->DB_DEPTH_BASE.u32All,
401 0, RADEON_GEM_DOMAIN_VRAM, 0);
402 END_BATCH();
403
404 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
405 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
406 BEGIN_BATCH_NO_AUTOSTATE(2);
407 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
408 R600_OUT_BATCH(1 << 0);
409 END_BATCH();
410 }
411
412 COMMIT_BATCH();
413
414 }
415
416 static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
417 {
418 context_t *context = R700_CONTEXT(ctx);
419 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
420 struct radeon_renderbuffer *rrb;
421 BATCH_LOCALS(&context->radeon);
422 int id = 0;
423 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
424
425 rrb = radeon_get_colorbuffer(&context->radeon);
426 if (!rrb || !rrb->bo) {
427 return;
428 }
429
430 r700SetRenderTarget(context, 0);
431
432 if (id > R700_MAX_RENDER_TARGETS)
433 return;
434
435 if (!r700->render_target[id].enabled)
436 return;
437
438 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
439 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
440 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
441 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
442 rrb->bo,
443 r700->render_target[id].CB_COLOR0_BASE.u32All,
444 0, RADEON_GEM_DOMAIN_VRAM, 0);
445 END_BATCH();
446
447 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
448 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
449 BEGIN_BATCH_NO_AUTOSTATE(2);
450 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
451 R600_OUT_BATCH((2 << id));
452 END_BATCH();
453 }
454 /* Set CMASK & TILE buffer to the offset of color buffer as
455 * we don't use those this shouldn't cause any issue and we
456 * then have a valid cmd stream
457 */
458 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
459 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
460 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
461 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
462 rrb->bo,
463 r700->render_target[id].CB_COLOR0_BASE.u32All,
464 0, RADEON_GEM_DOMAIN_VRAM, 0);
465 END_BATCH();
466 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
467 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
468 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All);
469 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
470 rrb->bo,
471 r700->render_target[id].CB_COLOR0_BASE.u32All,
472 0, RADEON_GEM_DOMAIN_VRAM, 0);
473 END_BATCH();
474
475 BEGIN_BATCH_NO_AUTOSTATE(12);
476 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
477 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
478 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
479 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
480 END_BATCH();
481
482 COMMIT_BATCH();
483
484 }
485
486 static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
487 {
488 context_t *context = R700_CONTEXT(ctx);
489 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
490 struct radeon_bo * pbo;
491 BATCH_LOCALS(&context->radeon);
492 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
493
494 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
495
496 if (!pbo)
497 return;
498
499 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
500
501 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
502 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
503 R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
504 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
505 pbo,
506 r700->ps.SQ_PGM_START_PS.u32All,
507 RADEON_GEM_DOMAIN_GTT, 0, 0);
508 END_BATCH();
509
510 BEGIN_BATCH_NO_AUTOSTATE(9);
511 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
512 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
513 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
514 END_BATCH();
515
516 BEGIN_BATCH_NO_AUTOSTATE(3);
517 R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
518 END_BATCH();
519
520 COMMIT_BATCH();
521
522 }
523
524 static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
525 {
526 context_t *context = R700_CONTEXT(ctx);
527 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
528 struct radeon_bo * pbo;
529 BATCH_LOCALS(&context->radeon);
530 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
531
532 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
533
534 if (!pbo)
535 return;
536
537 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
538
539 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
540 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
541 R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
542 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
543 pbo,
544 r700->vs.SQ_PGM_START_VS.u32All,
545 RADEON_GEM_DOMAIN_GTT, 0, 0);
546 END_BATCH();
547
548 BEGIN_BATCH_NO_AUTOSTATE(6);
549 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
550 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
551 END_BATCH();
552
553 BEGIN_BATCH_NO_AUTOSTATE(3);
554 R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
555 //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
556 END_BATCH();
557
558 COMMIT_BATCH();
559 }
560
561 static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
562 {
563 context_t *context = R700_CONTEXT(ctx);
564 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
565 struct radeon_bo * pbo;
566 BATCH_LOCALS(&context->radeon);
567 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
568
569 /* XXX fixme
570 * R6xx chips require a FS be emitted, even if it's not used.
571 * since we aren't using FS yet, just send the VS address to make
572 * the kernel command checker happy
573 */
574 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
575 r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
576 r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
577 r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
578 /* XXX */
579
580 if (!pbo)
581 return;
582
583 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
584
585 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
586 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
587 R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
588 R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
589 pbo,
590 r700->fs.SQ_PGM_START_FS.u32All,
591 RADEON_GEM_DOMAIN_GTT, 0, 0);
592 END_BATCH();
593
594 BEGIN_BATCH_NO_AUTOSTATE(6);
595 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
596 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
597 END_BATCH();
598
599 COMMIT_BATCH();
600
601 }
602
603 static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
604 {
605 context_t *context = R700_CONTEXT(ctx);
606 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
607 BATCH_LOCALS(&context->radeon);
608 int id = 0;
609 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
610
611 if (id > R700_MAX_VIEWPORTS)
612 return;
613
614 if (!r700->viewport[id].enabled)
615 return;
616
617 BEGIN_BATCH_NO_AUTOSTATE(16);
618 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
619 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
620 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
621 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
622 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
623 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
624 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
625 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
626 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
627 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
628 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
629 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
630 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
631 END_BATCH();
632
633 COMMIT_BATCH();
634
635 }
636
637 static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
638 {
639 context_t *context = R700_CONTEXT(ctx);
640 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
641 BATCH_LOCALS(&context->radeon);
642 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
643
644 BEGIN_BATCH_NO_AUTOSTATE(34);
645 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
646 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
647 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
648 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
649 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
650 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
651 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
652
653 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
654 R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
655 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
656 R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
657 R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
658
659 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
660 R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
661 R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
662 R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
663 R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
664 R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
665 R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
666 R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
667 R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
668 R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
669 END_BATCH();
670
671 COMMIT_BATCH();
672 }
673
674 static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
675 {
676 context_t *context = R700_CONTEXT(ctx);
677 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
678 BATCH_LOCALS(&context->radeon);
679 int i;
680 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
681
682 for (i = 0; i < R700_MAX_UCP; i++) {
683 if (r700->ucp[i].enabled) {
684 BEGIN_BATCH_NO_AUTOSTATE(6);
685 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
686 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
687 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
688 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
689 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
690 END_BATCH();
691 COMMIT_BATCH();
692 }
693 }
694 }
695
696 static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
697 {
698 context_t *context = R700_CONTEXT(ctx);
699 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
700 BATCH_LOCALS(&context->radeon);
701 unsigned int ui;
702 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
703
704 BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
705
706 R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
707 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
708 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
709 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
710 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
711 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
712 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
713 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
714 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
715 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
716 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
717 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
718 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
719 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
720 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
721 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
722 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
723 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
724 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
725 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
726 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
727 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
728 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
729 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
730 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
731 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
732 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
733 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
734 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
735 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
736 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
737 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
738 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
739
740 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
741 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
742 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
743 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
744 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
745 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
746 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
747 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
748 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
749 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
750 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
751
752 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
753 R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
754 R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
755 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
756 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
757 R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
758 R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
759 R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
760 R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
761 R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
762
763 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
764 for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
765 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
766
767 END_BATCH();
768 COMMIT_BATCH();
769 }
770
771 static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
772 {
773 context_t *context = R700_CONTEXT(ctx);
774 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
775 BATCH_LOCALS(&context->radeon);
776 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
777
778 BEGIN_BATCH_NO_AUTOSTATE(41);
779
780 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
781 R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
782 R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
783 R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
784 R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
785
786 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
787 R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
788 R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
789 R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
790 R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
791 R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
792 R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
793 R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
794 R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
795 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
796 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
797 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
798 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
799 R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
800
801 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
802 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
803 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
804 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
805
806 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
807 R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
808 R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
809 R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
810
811 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
812
813 END_BATCH();
814 COMMIT_BATCH();
815 }
816
817 static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
818 {
819 context_t *context = R700_CONTEXT(ctx);
820 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
821 BATCH_LOCALS(&context->radeon);
822 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
823
824 BEGIN_BATCH_NO_AUTOSTATE(9);
825 R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
826 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
827 R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
828 END_BATCH();
829 COMMIT_BATCH();
830 }
831
832 static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
833 {
834 context_t *context = R700_CONTEXT(ctx);
835 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
836 BATCH_LOCALS(&context->radeon);
837 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
838
839 BEGIN_BATCH_NO_AUTOSTATE(17);
840
841 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
842 R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
843 R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
844
845 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
846 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
847
848 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
849 R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
850 R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
851
852 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
853
854 END_BATCH();
855 COMMIT_BATCH();
856 }
857
858 static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
859 {
860 context_t *context = R700_CONTEXT(ctx);
861 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
862 BATCH_LOCALS(&context->radeon);
863
864 BEGIN_BATCH_NO_AUTOSTATE(4);
865 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
866 R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
867 R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
868 END_BATCH();
869 COMMIT_BATCH();
870 }
871
872 static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
873 {
874 context_t *context = R700_CONTEXT(ctx);
875 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
876 BATCH_LOCALS(&context->radeon);
877 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
878
879 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
880 BEGIN_BATCH_NO_AUTOSTATE(11);
881 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
882 R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
883 R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
884 R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
885 R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
886 R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
887 R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
888 R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
889 R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
890 END_BATCH();
891 }
892
893 BEGIN_BATCH_NO_AUTOSTATE(7);
894 R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
895 R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
896 R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
897 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
898 END_BATCH();
899 COMMIT_BATCH();
900 }
901
902 static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
903 {
904 context_t *context = R700_CONTEXT(ctx);
905 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
906 BATCH_LOCALS(&context->radeon);
907
908 BEGIN_BATCH_NO_AUTOSTATE(6);
909 R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
910 R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
911 R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
912 R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
913 R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
914 END_BATCH();
915 COMMIT_BATCH();
916 }
917
918 static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
919 {
920 context_t *context = R700_CONTEXT(ctx);
921 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
922 BATCH_LOCALS(&context->radeon);
923 unsigned int ui;
924 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
925
926 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
927 BEGIN_BATCH_NO_AUTOSTATE(3);
928 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
929 END_BATCH();
930 }
931
932 BEGIN_BATCH_NO_AUTOSTATE(3);
933 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
934 END_BATCH();
935
936 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
937 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
938 if (r700->render_target[ui].enabled) {
939 BEGIN_BATCH_NO_AUTOSTATE(3);
940 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
941 r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
942 END_BATCH();
943 }
944 }
945 }
946
947 COMMIT_BATCH();
948 }
949
950 static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
951 {
952 context_t *context = R700_CONTEXT(ctx);
953 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
954 BATCH_LOCALS(&context->radeon);
955 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
956
957 BEGIN_BATCH_NO_AUTOSTATE(6);
958 R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
959 R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
960 R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
961 R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
962 R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
963 END_BATCH();
964 COMMIT_BATCH();
965 }
966
967 static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
968 {
969 context_t *context = R700_CONTEXT(ctx);
970 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
971 BATCH_LOCALS(&context->radeon);
972
973 BEGIN_BATCH_NO_AUTOSTATE(9);
974 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
975 R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
976 R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
977 R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
978 R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
979 R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
980 END_BATCH();
981 COMMIT_BATCH();
982
983 }
984
985 static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
986 {
987 context_t *context = R700_CONTEXT(ctx);
988 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
989 BATCH_LOCALS(&context->radeon);
990
991 BEGIN_BATCH_NO_AUTOSTATE(10);
992 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
993 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
994 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
995 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
996 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
997 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
998 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
999 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
1000 END_BATCH();
1001 COMMIT_BATCH();
1002
1003 }
1004
1005 static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
1006 {
1007 context_t *context = R700_CONTEXT(ctx);
1008 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1009 BATCH_LOCALS(&context->radeon);
1010 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1011
1012 BEGIN_BATCH_NO_AUTOSTATE(12);
1013 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
1014 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
1015 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
1016 R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
1017 END_BATCH();
1018 COMMIT_BATCH();
1019 }
1020
1021 static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
1022 {
1023 context_t *context = R700_CONTEXT(ctx);
1024 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1025 BATCH_LOCALS(&context->radeon);
1026
1027 BEGIN_BATCH_NO_AUTOSTATE(6);
1028 R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
1029 R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
1030 R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
1031 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
1032 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
1033 END_BATCH();
1034 COMMIT_BATCH();
1035 }
1036
1037 static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
1038 {
1039 context_t *context = R700_CONTEXT(ctx);
1040 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1041 BATCH_LOCALS(&context->radeon);
1042 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1043
1044 BEGIN_BATCH_NO_AUTOSTATE(22);
1045 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1046 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
1047 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
1048
1049 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
1050 R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
1051 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
1052 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
1053 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
1054 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
1055 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
1056 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
1057 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
1058 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
1059 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
1060 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
1061 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
1062
1063 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1064 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
1065 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
1066 END_BATCH();
1067 COMMIT_BATCH();
1068 }
1069
1070 static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
1071 {
1072 context_t *context = R700_CONTEXT(ctx);
1073 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1074 BATCH_LOCALS(&context->radeon);
1075 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1076
1077 BEGIN_BATCH_NO_AUTOSTATE(15);
1078 R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
1079 R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
1080 R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
1081 R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
1082 R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
1083 END_BATCH();
1084 COMMIT_BATCH();
1085 }
1086
1087 static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
1088 {
1089 context_t *context = R700_CONTEXT(ctx);
1090 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1091 BATCH_LOCALS(&context->radeon);
1092
1093 BEGIN_BATCH_NO_AUTOSTATE(12);
1094 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
1095 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
1096 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
1097 R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
1098 END_BATCH();
1099 COMMIT_BATCH();
1100 }
1101
1102 static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1103 {
1104 context_t *context = R700_CONTEXT(ctx);
1105 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1106 int i;
1107 BATCH_LOCALS(&context->radeon);
1108
1109 if (r700->ps.num_consts == 0)
1110 return;
1111
1112 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
1113 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
1114 /* assembler map const from very beginning. */
1115 R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
1116 for (i = 0; i < r700->ps.num_consts; i++) {
1117 R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
1118 R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
1119 R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
1120 R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
1121 }
1122 END_BATCH();
1123 COMMIT_BATCH();
1124 }
1125
1126 static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1127 {
1128 context_t *context = R700_CONTEXT(ctx);
1129 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1130 int i;
1131 BATCH_LOCALS(&context->radeon);
1132 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1133
1134 if (r700->vs.num_consts == 0)
1135 return;
1136
1137 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
1138 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
1139 /* assembler map const from very beginning. */
1140 R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
1141 for (i = 0; i < r700->vs.num_consts; i++) {
1142 R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
1143 R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
1144 R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
1145 R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
1146 }
1147 END_BATCH();
1148 COMMIT_BATCH();
1149 }
1150
1151 static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
1152 {
1153 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1154 struct radeon_query_object *query = radeon->query.current;
1155 BATCH_LOCALS(radeon);
1156 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1157
1158 /* clear the buffer */
1159 radeon_bo_map(query->bo, GL_FALSE);
1160 memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
1161 radeon_bo_unmap(query->bo);
1162
1163 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
1164 query->bo,
1165 0, RADEON_GEM_DOMAIN_GTT);
1166
1167 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
1168 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
1169 R600_OUT_BATCH(ZPASS_DONE);
1170 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
1171 R600_OUT_BATCH(0x00000000);
1172 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
1173 END_BATCH();
1174 query->emitted_begin = GL_TRUE;
1175 }
1176
1177 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
1178 {
1179 return atom->cmd_size;
1180 }
1181
1182 static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
1183 {
1184 context_t *context = R700_CONTEXT(ctx);
1185 int count = 7;
1186
1187 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1188 count += 11;
1189 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1190
1191 return count;
1192 }
1193
1194 static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
1195 {
1196 context_t *context = R700_CONTEXT(ctx);
1197 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1198 unsigned int ui;
1199 int count = 3;
1200
1201 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1202 count += 3;
1203
1204 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1205 /* targets are enabled in r700SetRenderTarget but state
1206 size is calculated before that. Until MRT's are done
1207 hardcode target0 as enabled. */
1208 count += 3;
1209 for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) {
1210 if (r700->render_target[ui].enabled)
1211 count += 3;
1212 }
1213 }
1214 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1215
1216 return count;
1217 }
1218
1219 static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
1220 {
1221 context_t *context = R700_CONTEXT(ctx);
1222 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1223 int i;
1224 int count = 0;
1225
1226 for (i = 0; i < R700_MAX_UCP; i++) {
1227 if (r700->ucp[i].enabled)
1228 count += 6;
1229 }
1230 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1231 return count;
1232 }
1233
1234 static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
1235 {
1236 context_t *context = R700_CONTEXT(ctx);
1237 int count = context->radeon.tcl.aos_count * 18;
1238
1239 if (count)
1240 count += 6;
1241
1242 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1243 return count;
1244 }
1245
1246 static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
1247 {
1248 context_t *context = R700_CONTEXT(ctx);
1249 unsigned int i, count = 0;
1250 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1251
1252 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
1253 if (ctx->Texture.Unit[i]._ReallyEnabled) {
1254 radeonTexObj *t = r700->textures[i];
1255 if (t)
1256 count++;
1257 }
1258 }
1259 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1260 return count * 31;
1261 }
1262
1263 static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1264 {
1265 context_t *context = R700_CONTEXT(ctx);
1266 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1267 int count = r700->ps.num_consts * 4;
1268
1269 if (count)
1270 count += 2;
1271 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1272
1273 return count;
1274 }
1275
1276 static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1277 {
1278 context_t *context = R700_CONTEXT(ctx);
1279 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1280 int count = r700->vs.num_consts * 4;
1281
1282 if (count)
1283 count += 2;
1284 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1285
1286 return count;
1287 }
1288
1289 static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
1290 {
1291 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1292 struct radeon_query_object *query = radeon->query.current;
1293 int count;
1294
1295 if (!query || query->emitted_begin)
1296 count = 0;
1297 else
1298 count = atom->cmd_size;
1299 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1300 return count;
1301 }
1302
1303 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
1304 do { \
1305 context->atoms.ATOM.cmd_size = (SZ); \
1306 context->atoms.ATOM.cmd = NULL; \
1307 context->atoms.ATOM.name = #ATOM; \
1308 context->atoms.ATOM.idx = 0; \
1309 context->atoms.ATOM.check = check_##CHK; \
1310 context->atoms.ATOM.dirty = GL_FALSE; \
1311 context->atoms.ATOM.emit = (EMIT); \
1312 context->radeon.hw.max_state_size += (SZ); \
1313 insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1314 } while (0)
1315
1316 static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
1317 {
1318 radeon->query.queryobj.cmd_size = (SZ);
1319 radeon->query.queryobj.cmd = NULL;
1320 radeon->query.queryobj.name = "queryobj";
1321 radeon->query.queryobj.idx = 0;
1322 radeon->query.queryobj.check = check_queryobj;
1323 radeon->query.queryobj.dirty = GL_FALSE;
1324 radeon->query.queryobj.emit = r700SendQueryBegin;
1325 radeon->hw.max_state_size += (SZ);
1326 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
1327 }
1328
1329 void r600InitAtoms(context_t *context)
1330 {
1331 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1332 context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1333
1334 /* Setup the atom linked list */
1335 make_empty_list(&context->radeon.hw.atomlist);
1336 context->radeon.hw.atomlist.name = "atom-list";
1337
1338 ALLOC_STATE(sq, always, 34, r700SendSQConfig);
1339 ALLOC_STATE(db, always, 17, r700SendDBState);
1340 ALLOC_STATE(stencil, always, 4, r700SendStencilState);
1341 ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
1342 ALLOC_STATE(sc, always, 15, r700SendSCState);
1343 ALLOC_STATE(scissor, always, 22, r700SendScissorState);
1344 ALLOC_STATE(aa, always, 12, r700SendAAState);
1345 ALLOC_STATE(cl, always, 12, r700SendCLState);
1346 ALLOC_STATE(gb, always, 6, r700SendGBState);
1347 ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
1348 ALLOC_STATE(su, always, 9, r700SendSUState);
1349 ALLOC_STATE(poly, always, 10, r700SendPolyState);
1350 ALLOC_STATE(cb, cb, 18, r700SendCBState);
1351 ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
1352 ALLOC_STATE(cb_target, always, 29, r700SendRenderTargetState);
1353 ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
1354 ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
1355 ALLOC_STATE(sx, always, 9, r700SendSXState);
1356 ALLOC_STATE(vgt, always, 41, r700SendVGTState);
1357 ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
1358 ALLOC_STATE(vpt, always, 16, r700SendViewportState);
1359 ALLOC_STATE(fs, always, 18, r700SendFSState);
1360 ALLOC_STATE(vs, always, 21, r700SendVSState);
1361 ALLOC_STATE(ps, always, 24, r700SendPSState);
1362 ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
1363 ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
1364 ALLOC_STATE(vtx, vtx, (6 + (VERT_ATTRIB_MAX * 18)), r700SendVTXState);
1365 ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
1366 ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
1367 ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
1368 r600_init_query_stateobj(&context->radeon, 6 * 2);
1369
1370 context->radeon.hw.is_dirty = GL_TRUE;
1371 context->radeon.hw.all_dirty = GL_TRUE;
1372 }