2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
28 #include "main/imports.h"
29 #include "main/glheader.h"
30 #include "main/simple_list.h"
32 #include "r600_context.h"
33 #include "r600_cmdbuf.h"
36 #include "r700_oglprog.h"
37 #include "r700_fragprog.h"
38 #include "r700_vertprog.h"
40 #include "radeon_mipmap_tree.h"
42 static void r700SendTexState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
44 context_t
*context
= R700_CONTEXT(ctx
);
45 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
47 struct r700_vertex_program
*vp
= context
->selected_vp
;
49 struct radeon_bo
*bo
= NULL
;
51 BATCH_LOCALS(&context
->radeon
);
53 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
55 for (i
= 0; i
< R700_TEXTURE_NUMBERUNITS
; i
++) {
56 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
57 radeonTexObj
*t
= r700
->textures
[i
];
59 if (!t
->image_override
) {
66 r700SyncSurf(context
, bo
,
67 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
,
68 0, TC_ACTION_ENA_bit
);
70 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
71 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE
, 7));
73 if( (1<<i
) & vp
->r700AsmCode
.unVetTexBits
)
75 R600_OUT_BATCH((i
+ VERT_ATTRIB_MAX
+ SQ_FETCH_RESOURCE_VS_OFFSET
) * FETCH_RESOURCE_STRIDE
);
79 R600_OUT_BATCH(i
* 7);
82 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_RESOURCE0
);
83 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_RESOURCE1
);
84 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_RESOURCE2
);
85 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_RESOURCE3
);
86 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_RESOURCE4
);
87 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_RESOURCE5
);
88 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_RESOURCE6
);
89 R600_OUT_BATCH_RELOC(r700
->textures
[i
]->SQ_TEX_RESOURCE2
,
91 r700
->textures
[i
]->SQ_TEX_RESOURCE2
,
92 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
93 R600_OUT_BATCH_RELOC(r700
->textures
[i
]->SQ_TEX_RESOURCE3
,
95 r700
->textures
[i
]->SQ_TEX_RESOURCE3
,
96 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
105 #define SAMPLER_STRIDE 3
107 static void r700SendTexSamplerState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
109 context_t
*context
= R700_CONTEXT(ctx
);
110 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
113 struct r700_vertex_program
*vp
= context
->selected_vp
;
115 BATCH_LOCALS(&context
->radeon
);
116 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
118 for (i
= 0; i
< R700_TEXTURE_NUMBERUNITS
; i
++) {
119 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
120 radeonTexObj
*t
= r700
->textures
[i
];
122 BEGIN_BATCH_NO_AUTOSTATE(5);
123 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER
, 3));
125 if( (1<<i
) & vp
->r700AsmCode
.unVetTexBits
)
127 R600_OUT_BATCH((i
+SQ_TEX_SAMPLER_VS_OFFSET
) * SAMPLER_STRIDE
); //work 1
131 R600_OUT_BATCH(i
* 3);
134 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_SAMPLER0
);
135 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_SAMPLER1
);
136 R600_OUT_BATCH(r700
->textures
[i
]->SQ_TEX_SAMPLER2
);
144 static void r700SendTexBorderColorState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
146 context_t
*context
= R700_CONTEXT(ctx
);
147 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
149 BATCH_LOCALS(&context
->radeon
);
150 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
152 for (i
= 0; i
< R700_TEXTURE_NUMBERUNITS
; i
++) {
153 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
154 radeonTexObj
*t
= r700
->textures
[i
];
156 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
157 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED
+ (i
* 16)), 4);
158 R600_OUT_BATCH(r700
->textures
[i
]->TD_PS_SAMPLER0_BORDER_RED
);
159 R600_OUT_BATCH(r700
->textures
[i
]->TD_PS_SAMPLER0_BORDER_GREEN
);
160 R600_OUT_BATCH(r700
->textures
[i
]->TD_PS_SAMPLER0_BORDER_BLUE
);
161 R600_OUT_BATCH(r700
->textures
[i
]->TD_PS_SAMPLER0_BORDER_ALPHA
);
169 extern int getTypeSize(GLenum type
);
170 static void r700SetupVTXConstants(GLcontext
* ctx
,
172 StreamDesc
* pStreamDesc
)
174 context_t
*context
= R700_CONTEXT(ctx
);
175 struct radeon_aos
* paos
= (struct radeon_aos
*)pAos
;
176 unsigned int nVBsize
;
177 BATCH_LOCALS(&context
->radeon
);
179 unsigned int uSQ_VTX_CONSTANT_WORD0_0
;
180 unsigned int uSQ_VTX_CONSTANT_WORD1_0
;
181 unsigned int uSQ_VTX_CONSTANT_WORD2_0
= 0;
182 unsigned int uSQ_VTX_CONSTANT_WORD3_0
= 0;
183 unsigned int uSQ_VTX_CONSTANT_WORD6_0
= 0;
188 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
189 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
190 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
191 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
192 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
193 r700SyncSurf(context
, paos
->bo
, RADEON_GEM_DOMAIN_GTT
, 0, TC_ACTION_ENA_bit
);
195 r700SyncSurf(context
, paos
->bo
, RADEON_GEM_DOMAIN_GTT
, 0, VC_ACTION_ENA_bit
);
197 if(0 == pStreamDesc
->stride
)
199 nVBsize
= paos
->count
* pStreamDesc
->size
* getTypeSize(pStreamDesc
->type
);
203 nVBsize
= paos
->count
* pStreamDesc
->stride
;
206 uSQ_VTX_CONSTANT_WORD0_0
= paos
->offset
;
207 uSQ_VTX_CONSTANT_WORD1_0
= nVBsize
- 1;
209 SETfield(uSQ_VTX_CONSTANT_WORD2_0
, 0, BASE_ADDRESS_HI_shift
, BASE_ADDRESS_HI_mask
); /* TODO */
210 SETfield(uSQ_VTX_CONSTANT_WORD2_0
, pStreamDesc
->stride
, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift
,
211 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask
);
212 SETfield(uSQ_VTX_CONSTANT_WORD2_0
, GetSurfaceFormat(pStreamDesc
->type
, pStreamDesc
->size
, NULL
),
213 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift
,
214 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask
); /* TODO : trace back api for initial data type, not only GL_FLOAT */
216 if(GL_TRUE
== pStreamDesc
->normalize
)
218 SETfield(uSQ_VTX_CONSTANT_WORD2_0
, SQ_NUM_FORMAT_NORM
,
219 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift
, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask
);
223 // SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_INT,
224 // SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
227 if(1 == pStreamDesc
->_signed
)
229 SETbit(uSQ_VTX_CONSTANT_WORD2_0
, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit
);
232 SETfield(uSQ_VTX_CONSTANT_WORD3_0
, 1, MEM_REQUEST_SIZE_shift
, MEM_REQUEST_SIZE_mask
);
233 SETfield(uSQ_VTX_CONSTANT_WORD6_0
, SQ_TEX_VTX_VALID_BUFFER
,
234 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift
, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask
);
236 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
238 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE
, 7));
239 R600_OUT_BATCH((pStreamDesc
->element
+ SQ_FETCH_RESOURCE_VS_OFFSET
) * FETCH_RESOURCE_STRIDE
);
240 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0
);
241 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0
);
242 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0
);
243 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0
);
246 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0
);
247 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0
,
249 uSQ_VTX_CONSTANT_WORD0_0
,
250 RADEON_GEM_DOMAIN_GTT
, 0, 0);
256 static void r700SendVTXState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
258 context_t
*context
= R700_CONTEXT(ctx
);
259 struct r700_vertex_program
*vp
= context
->selected_vp
;
260 unsigned int i
, j
= 0;
261 BATCH_LOCALS(&context
->radeon
);
262 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
264 if (context
->radeon
.tcl
.aos_count
== 0)
267 BEGIN_BATCH_NO_AUTOSTATE(6);
268 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 1));
269 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
272 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 1));
273 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
278 for(i
=0; i
<VERT_ATTRIB_MAX
; i
++) {
279 if(vp
->mesa_program
->Base
.InputsRead
& (1 << i
))
281 r700SetupVTXConstants(ctx
,
282 (void*)(&context
->radeon
.tcl
.aos
[j
]),
283 &(context
->stream_desc
[j
]));
289 static void r700SetRenderTarget(context_t
*context
, int id
)
291 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
293 struct radeon_renderbuffer
*rrb
;
294 unsigned int nPitchInPixel
;
296 rrb
= radeon_get_colorbuffer(&context
->radeon
);
297 if (!rrb
|| !rrb
->bo
) {
301 R600_STATECHANGE(context
, cb_target
);
304 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= context
->radeon
.state
.color
.draw_offset
/ 256;
306 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
307 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, (nPitchInPixel
/8)-1,
308 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
309 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
310 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
);
311 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ENDIAN_NONE
, ENDIAN_shift
, ENDIAN_mask
);
312 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ARRAY_LINEAR_GENERAL
,
313 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
316 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_8_8_8_8
,
317 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
318 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT
, COMP_SWAP_shift
, COMP_SWAP_mask
);
322 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_5_6_5
,
323 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
324 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT_REV
,
325 COMP_SWAP_shift
, COMP_SWAP_mask
);
327 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SOURCE_FORMAT_bit
);
328 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, BLEND_CLAMP_bit
);
329 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
331 r700
->render_target
[id
].enabled
= GL_TRUE
;
334 static void r700SetDepthTarget(context_t
*context
)
336 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
338 struct radeon_renderbuffer
*rrb
;
339 unsigned int nPitchInPixel
;
341 rrb
= radeon_get_depthbuffer(&context
->radeon
);
345 R600_STATECHANGE(context
, db_target
);
348 r700
->DB_DEPTH_SIZE
.u32All
= 0;
349 r700
->DB_DEPTH_BASE
.u32All
= 0;
350 r700
->DB_DEPTH_INFO
.u32All
= 0;
351 r700
->DB_DEPTH_VIEW
.u32All
= 0;
353 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
355 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, (nPitchInPixel
/8)-1,
356 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
357 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
358 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
); /* size in pixel / 64 - 1 */
362 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_8_24
,
363 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
367 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_16
,
368 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
370 SETfield(r700
->DB_DEPTH_INFO
.u32All
, ARRAY_1D_TILED_THIN1
,
371 DB_DEPTH_INFO__ARRAY_MODE_shift
, DB_DEPTH_INFO__ARRAY_MODE_mask
);
372 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
375 static void r700SendDepthTargetState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
377 context_t
*context
= R700_CONTEXT(ctx
);
378 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
379 struct radeon_renderbuffer
*rrb
;
380 BATCH_LOCALS(&context
->radeon
);
381 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
383 rrb
= radeon_get_depthbuffer(&context
->radeon
);
384 if (!rrb
|| !rrb
->bo
) {
388 r700SetDepthTarget(context
);
390 BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
391 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE
, 2);
392 R600_OUT_BATCH(r700
->DB_DEPTH_SIZE
.u32All
);
393 R600_OUT_BATCH(r700
->DB_DEPTH_VIEW
.u32All
);
394 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE
, 2);
395 R600_OUT_BATCH(r700
->DB_DEPTH_BASE
.u32All
);
396 R600_OUT_BATCH(r700
->DB_DEPTH_INFO
.u32All
);
397 R600_OUT_BATCH_RELOC(r700
->DB_DEPTH_BASE
.u32All
,
399 r700
->DB_DEPTH_BASE
.u32All
,
400 0, RADEON_GEM_DOMAIN_VRAM
, 0);
403 if ((context
->radeon
.radeonScreen
->chip_family
> CHIP_FAMILY_R600
) &&
404 (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)) {
405 BEGIN_BATCH_NO_AUTOSTATE(2);
406 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE
, 0));
407 R600_OUT_BATCH(1 << 0);
415 static void r700SendRenderTargetState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
417 context_t
*context
= R700_CONTEXT(ctx
);
418 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
419 struct radeon_renderbuffer
*rrb
;
420 BATCH_LOCALS(&context
->radeon
);
422 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
424 rrb
= radeon_get_colorbuffer(&context
->radeon
);
425 if (!rrb
|| !rrb
->bo
) {
429 r700SetRenderTarget(context
, 0);
431 if (id
> R700_MAX_RENDER_TARGETS
)
434 if (!r700
->render_target
[id
].enabled
)
437 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
438 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE
+ (4 * id
), 1);
439 R600_OUT_BATCH(r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
);
440 R600_OUT_BATCH_RELOC(r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
,
442 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
,
443 0, RADEON_GEM_DOMAIN_VRAM
, 0);
446 if ((context
->radeon
.radeonScreen
->chip_family
> CHIP_FAMILY_R600
) &&
447 (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)) {
448 BEGIN_BATCH_NO_AUTOSTATE(2);
449 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE
, 0));
450 R600_OUT_BATCH((2 << id
));
453 /* Set CMASK & TILE buffer to the offset of color buffer as
454 * we don't use those this shouldn't cause any issue and we
455 * then have a valid cmd stream
457 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
458 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE
+ (4 * id
), 1);
459 R600_OUT_BATCH(r700
->render_target
[id
].CB_COLOR0_TILE
.u32All
);
460 R600_OUT_BATCH_RELOC(r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
,
462 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
,
463 0, RADEON_GEM_DOMAIN_VRAM
, 0);
465 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
466 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG
+ (4 * id
), 1);
467 R600_OUT_BATCH(r700
->render_target
[id
].CB_COLOR0_FRAG
.u32All
);
468 R600_OUT_BATCH_RELOC(r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
,
470 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
,
471 0, RADEON_GEM_DOMAIN_VRAM
, 0);
474 BEGIN_BATCH_NO_AUTOSTATE(12);
475 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE
+ (4 * id
), r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
);
476 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW
+ (4 * id
), r700
->render_target
[id
].CB_COLOR0_VIEW
.u32All
);
477 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO
+ (4 * id
), r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
);
478 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK
+ (4 * id
), r700
->render_target
[id
].CB_COLOR0_MASK
.u32All
);
485 static void r700SendPSState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
487 context_t
*context
= R700_CONTEXT(ctx
);
488 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
489 struct radeon_bo
* pbo
;
490 BATCH_LOCALS(&context
->radeon
);
491 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
493 pbo
= (struct radeon_bo
*)r700GetActiveFpShaderBo(GL_CONTEXT(context
));
498 r700SyncSurf(context
, pbo
, RADEON_GEM_DOMAIN_GTT
, 0, SH_ACTION_ENA_bit
);
500 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
501 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS
, 1);
502 R600_OUT_BATCH(r700
->ps
.SQ_PGM_START_PS
.u32All
);
503 R600_OUT_BATCH_RELOC(r700
->ps
.SQ_PGM_START_PS
.u32All
,
505 r700
->ps
.SQ_PGM_START_PS
.u32All
,
506 RADEON_GEM_DOMAIN_GTT
, 0, 0);
509 BEGIN_BATCH_NO_AUTOSTATE(9);
510 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS
, r700
->ps
.SQ_PGM_RESOURCES_PS
.u32All
);
511 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS
, r700
->ps
.SQ_PGM_EXPORTS_PS
.u32All
);
512 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS
, r700
->ps
.SQ_PGM_CF_OFFSET_PS
.u32All
);
515 BEGIN_BATCH_NO_AUTOSTATE(3);
516 R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0
, 0x01000FFF);
523 static void r700SendVSState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
525 context_t
*context
= R700_CONTEXT(ctx
);
526 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
527 struct radeon_bo
* pbo
;
528 BATCH_LOCALS(&context
->radeon
);
529 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
531 pbo
= (struct radeon_bo
*)r700GetActiveVpShaderBo(GL_CONTEXT(context
));
536 r700SyncSurf(context
, pbo
, RADEON_GEM_DOMAIN_GTT
, 0, SH_ACTION_ENA_bit
);
538 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
539 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS
, 1);
540 R600_OUT_BATCH(r700
->vs
.SQ_PGM_START_VS
.u32All
);
541 R600_OUT_BATCH_RELOC(r700
->vs
.SQ_PGM_START_VS
.u32All
,
543 r700
->vs
.SQ_PGM_START_VS
.u32All
,
544 RADEON_GEM_DOMAIN_GTT
, 0, 0);
547 BEGIN_BATCH_NO_AUTOSTATE(6);
548 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS
, r700
->vs
.SQ_PGM_RESOURCES_VS
.u32All
);
549 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS
, r700
->vs
.SQ_PGM_CF_OFFSET_VS
.u32All
);
552 BEGIN_BATCH_NO_AUTOSTATE(3);
553 R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0
+ 32*4), 0x0100000F);
554 //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
560 static void r700SendFSState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
562 context_t
*context
= R700_CONTEXT(ctx
);
563 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
564 struct radeon_bo
* pbo
;
565 BATCH_LOCALS(&context
->radeon
);
566 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
569 * R6xx chips require a FS be emitted, even if it's not used.
570 * since we aren't using FS yet, just send the VS address to make
571 * the kernel command checker happy
573 pbo
= (struct radeon_bo
*)r700GetActiveVpShaderBo(GL_CONTEXT(context
));
574 r700
->fs
.SQ_PGM_START_FS
.u32All
= r700
->vs
.SQ_PGM_START_VS
.u32All
;
575 r700
->fs
.SQ_PGM_RESOURCES_FS
.u32All
= 0;
576 r700
->fs
.SQ_PGM_CF_OFFSET_FS
.u32All
= 0;
582 r700SyncSurf(context
, pbo
, RADEON_GEM_DOMAIN_GTT
, 0, SH_ACTION_ENA_bit
);
584 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
585 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS
, 1);
586 R600_OUT_BATCH(r700
->fs
.SQ_PGM_START_FS
.u32All
);
587 R600_OUT_BATCH_RELOC(r700
->fs
.SQ_PGM_START_FS
.u32All
,
589 r700
->fs
.SQ_PGM_START_FS
.u32All
,
590 RADEON_GEM_DOMAIN_GTT
, 0, 0);
593 BEGIN_BATCH_NO_AUTOSTATE(6);
594 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS
, r700
->fs
.SQ_PGM_RESOURCES_FS
.u32All
);
595 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS
, r700
->fs
.SQ_PGM_CF_OFFSET_FS
.u32All
);
602 static void r700SendViewportState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
604 context_t
*context
= R700_CONTEXT(ctx
);
605 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
606 BATCH_LOCALS(&context
->radeon
);
608 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
610 if (id
> R700_MAX_VIEWPORTS
)
613 if (!r700
->viewport
[id
].enabled
)
616 BEGIN_BATCH_NO_AUTOSTATE(16);
617 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL
+ (8 * id
), 2);
618 R600_OUT_BATCH(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
);
619 R600_OUT_BATCH(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
);
620 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0
+ (8 * id
), 2);
621 R600_OUT_BATCH(r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
);
622 R600_OUT_BATCH(r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
);
623 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0
+ (24 * id
), 6);
624 R600_OUT_BATCH(r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.u32All
);
625 R600_OUT_BATCH(r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.u32All
);
626 R600_OUT_BATCH(r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.u32All
);
627 R600_OUT_BATCH(r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.u32All
);
628 R600_OUT_BATCH(r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.u32All
);
629 R600_OUT_BATCH(r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.u32All
);
636 static void r700SendSQConfig(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
638 context_t
*context
= R700_CONTEXT(ctx
);
639 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
640 BATCH_LOCALS(&context
->radeon
);
641 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
643 BEGIN_BATCH_NO_AUTOSTATE(34);
644 R600_OUT_BATCH_REGSEQ(SQ_CONFIG
, 6);
645 R600_OUT_BATCH(r700
->sq_config
.SQ_CONFIG
.u32All
);
646 R600_OUT_BATCH(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
);
647 R600_OUT_BATCH(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
);
648 R600_OUT_BATCH(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
);
649 R600_OUT_BATCH(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
);
650 R600_OUT_BATCH(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
);
652 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX
, r700
->TA_CNTL_AUX
.u32All
);
653 R600_OUT_BATCH_REGVAL(VC_ENHANCE
, r700
->VC_ENHANCE
.u32All
);
654 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
);
655 R600_OUT_BATCH_REGVAL(DB_DEBUG
, r700
->DB_DEBUG
.u32All
);
656 R600_OUT_BATCH_REGVAL(DB_WATERMARKS
, r700
->DB_WATERMARKS
.u32All
);
658 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE
, 9);
659 R600_OUT_BATCH(r700
->SQ_ESGS_RING_ITEMSIZE
.u32All
);
660 R600_OUT_BATCH(r700
->SQ_GSVS_RING_ITEMSIZE
.u32All
);
661 R600_OUT_BATCH(r700
->SQ_ESTMP_RING_ITEMSIZE
.u32All
);
662 R600_OUT_BATCH(r700
->SQ_GSTMP_RING_ITEMSIZE
.u32All
);
663 R600_OUT_BATCH(r700
->SQ_VSTMP_RING_ITEMSIZE
.u32All
);
664 R600_OUT_BATCH(r700
->SQ_PSTMP_RING_ITEMSIZE
.u32All
);
665 R600_OUT_BATCH(r700
->SQ_FBUF_RING_ITEMSIZE
.u32All
);
666 R600_OUT_BATCH(r700
->SQ_REDUC_RING_ITEMSIZE
.u32All
);
667 R600_OUT_BATCH(r700
->SQ_GS_VERT_ITEMSIZE
.u32All
);
673 static void r700SendUCPState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
675 context_t
*context
= R700_CONTEXT(ctx
);
676 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
677 BATCH_LOCALS(&context
->radeon
);
679 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
681 for (i
= 0; i
< R700_MAX_UCP
; i
++) {
682 if (r700
->ucp
[i
].enabled
) {
683 BEGIN_BATCH_NO_AUTOSTATE(6);
684 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X
+ (16 * i
), 4);
685 R600_OUT_BATCH(r700
->ucp
[i
].PA_CL_UCP_0_X
.u32All
);
686 R600_OUT_BATCH(r700
->ucp
[i
].PA_CL_UCP_0_Y
.u32All
);
687 R600_OUT_BATCH(r700
->ucp
[i
].PA_CL_UCP_0_Z
.u32All
);
688 R600_OUT_BATCH(r700
->ucp
[i
].PA_CL_UCP_0_W
.u32All
);
695 static void r700SendSPIState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
697 context_t
*context
= R700_CONTEXT(ctx
);
698 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
699 BATCH_LOCALS(&context
->radeon
);
701 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
703 BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS
);
705 R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0
, 32);
706 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_0
.u32All
);
707 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_1
.u32All
);
708 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_2
.u32All
);
709 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_3
.u32All
);
710 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_4
.u32All
);
711 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_5
.u32All
);
712 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_6
.u32All
);
713 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_7
.u32All
);
714 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_8
.u32All
);
715 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_9
.u32All
);
716 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_10
.u32All
);
717 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_11
.u32All
);
718 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_12
.u32All
);
719 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_13
.u32All
);
720 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_14
.u32All
);
721 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_15
.u32All
);
722 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_16
.u32All
);
723 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_17
.u32All
);
724 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_18
.u32All
);
725 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_19
.u32All
);
726 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_20
.u32All
);
727 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_21
.u32All
);
728 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_22
.u32All
);
729 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_23
.u32All
);
730 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_24
.u32All
);
731 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_25
.u32All
);
732 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_26
.u32All
);
733 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_27
.u32All
);
734 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_28
.u32All
);
735 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_29
.u32All
);
736 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_30
.u32All
);
737 R600_OUT_BATCH(r700
->SQ_VTX_SEMANTIC_31
.u32All
);
739 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0
, 10);
740 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_0
.u32All
);
741 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_1
.u32All
);
742 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_2
.u32All
);
743 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_3
.u32All
);
744 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_4
.u32All
);
745 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_5
.u32All
);
746 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_6
.u32All
);
747 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_7
.u32All
);
748 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_8
.u32All
);
749 R600_OUT_BATCH(r700
->SPI_VS_OUT_ID_9
.u32All
);
751 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG
, 9);
752 R600_OUT_BATCH(r700
->SPI_VS_OUT_CONFIG
.u32All
);
753 R600_OUT_BATCH(r700
->SPI_THREAD_GROUPING
.u32All
);
754 R600_OUT_BATCH(r700
->SPI_PS_IN_CONTROL_0
.u32All
);
755 R600_OUT_BATCH(r700
->SPI_PS_IN_CONTROL_1
.u32All
);
756 R600_OUT_BATCH(r700
->SPI_INTERP_CONTROL_0
.u32All
);
757 R600_OUT_BATCH(r700
->SPI_INPUT_Z
.u32All
);
758 R600_OUT_BATCH(r700
->SPI_FOG_CNTL
.u32All
);
759 R600_OUT_BATCH(r700
->SPI_FOG_FUNC_SCALE
.u32All
);
760 R600_OUT_BATCH(r700
->SPI_FOG_FUNC_BIAS
.u32All
);
762 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0
, R700_MAX_SHADER_EXPORTS
);
763 for(ui
= 0; ui
< R700_MAX_SHADER_EXPORTS
; ui
++)
764 R600_OUT_BATCH(r700
->SPI_PS_INPUT_CNTL
[ui
].u32All
);
770 static void r700SendVGTState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
772 context_t
*context
= R700_CONTEXT(ctx
);
773 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
774 BATCH_LOCALS(&context
->radeon
);
775 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
777 BEGIN_BATCH_NO_AUTOSTATE(41);
779 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX
, 4);
780 R600_OUT_BATCH(r700
->VGT_MAX_VTX_INDX
.u32All
);
781 R600_OUT_BATCH(r700
->VGT_MIN_VTX_INDX
.u32All
);
782 R600_OUT_BATCH(r700
->VGT_INDX_OFFSET
.u32All
);
783 R600_OUT_BATCH(r700
->VGT_MULTI_PRIM_IB_RESET_INDX
.u32All
);
785 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL
, 13);
786 R600_OUT_BATCH(r700
->VGT_OUTPUT_PATH_CNTL
.u32All
);
787 R600_OUT_BATCH(r700
->VGT_HOS_CNTL
.u32All
);
788 R600_OUT_BATCH(r700
->VGT_HOS_MAX_TESS_LEVEL
.u32All
);
789 R600_OUT_BATCH(r700
->VGT_HOS_MIN_TESS_LEVEL
.u32All
);
790 R600_OUT_BATCH(r700
->VGT_HOS_REUSE_DEPTH
.u32All
);
791 R600_OUT_BATCH(r700
->VGT_GROUP_PRIM_TYPE
.u32All
);
792 R600_OUT_BATCH(r700
->VGT_GROUP_FIRST_DECR
.u32All
);
793 R600_OUT_BATCH(r700
->VGT_GROUP_DECR
.u32All
);
794 R600_OUT_BATCH(r700
->VGT_GROUP_VECT_0_CNTL
.u32All
);
795 R600_OUT_BATCH(r700
->VGT_GROUP_VECT_1_CNTL
.u32All
);
796 R600_OUT_BATCH(r700
->VGT_GROUP_VECT_0_FMT_CNTL
.u32All
);
797 R600_OUT_BATCH(r700
->VGT_GROUP_VECT_1_FMT_CNTL
.u32All
);
798 R600_OUT_BATCH(r700
->VGT_GS_MODE
.u32All
);
800 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN
, r700
->VGT_PRIMITIVEID_EN
.u32All
);
801 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN
, r700
->VGT_MULTI_PRIM_IB_RESET_EN
.u32All
);
802 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0
, r700
->VGT_INSTANCE_STEP_RATE_0
.u32All
);
803 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1
, r700
->VGT_INSTANCE_STEP_RATE_1
.u32All
);
805 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN
, 3);
806 R600_OUT_BATCH(r700
->VGT_STRMOUT_EN
.u32All
);
807 R600_OUT_BATCH(r700
->VGT_REUSE_OFF
.u32All
);
808 R600_OUT_BATCH(r700
->VGT_VTX_CNT_EN
.u32All
);
810 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN
, r700
->VGT_STRMOUT_BUFFER_EN
.u32All
);
816 static void r700SendSXState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
818 context_t
*context
= R700_CONTEXT(ctx
);
819 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
820 BATCH_LOCALS(&context
->radeon
);
821 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
823 BEGIN_BATCH_NO_AUTOSTATE(9);
824 R600_OUT_BATCH_REGVAL(SX_MISC
, r700
->SX_MISC
.u32All
);
825 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL
, r700
->SX_ALPHA_TEST_CONTROL
.u32All
);
826 R600_OUT_BATCH_REGVAL(SX_ALPHA_REF
, r700
->SX_ALPHA_REF
.u32All
);
831 static void r700SendDBState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
833 context_t
*context
= R700_CONTEXT(ctx
);
834 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
835 BATCH_LOCALS(&context
->radeon
);
836 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
838 BEGIN_BATCH_NO_AUTOSTATE(17);
840 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR
, 2);
841 R600_OUT_BATCH(r700
->DB_STENCIL_CLEAR
.u32All
);
842 R600_OUT_BATCH(r700
->DB_DEPTH_CLEAR
.u32All
);
844 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL
, r700
->DB_DEPTH_CONTROL
.u32All
);
845 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL
, r700
->DB_SHADER_CONTROL
.u32All
);
847 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL
, 2);
848 R600_OUT_BATCH(r700
->DB_RENDER_CONTROL
.u32All
);
849 R600_OUT_BATCH(r700
->DB_RENDER_OVERRIDE
.u32All
);
851 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK
, r700
->DB_ALPHA_TO_MASK
.u32All
);
857 static void r700SendStencilState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
859 context_t
*context
= R700_CONTEXT(ctx
);
860 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
861 BATCH_LOCALS(&context
->radeon
);
863 BEGIN_BATCH_NO_AUTOSTATE(4);
864 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK
, 2);
865 R600_OUT_BATCH(r700
->DB_STENCILREFMASK
.u32All
);
866 R600_OUT_BATCH(r700
->DB_STENCILREFMASK_BF
.u32All
);
871 static void r700SendCBState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
873 context_t
*context
= R700_CONTEXT(ctx
);
874 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
875 BATCH_LOCALS(&context
->radeon
);
876 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
878 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
879 BEGIN_BATCH_NO_AUTOSTATE(11);
880 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED
, 4);
881 R600_OUT_BATCH(r700
->CB_CLEAR_RED_R6XX
.u32All
);
882 R600_OUT_BATCH(r700
->CB_CLEAR_GREEN_R6XX
.u32All
);
883 R600_OUT_BATCH(r700
->CB_CLEAR_BLUE_R6XX
.u32All
);
884 R600_OUT_BATCH(r700
->CB_CLEAR_ALPHA_R6XX
.u32All
);
885 R600_OUT_BATCH_REGSEQ(CB_FOG_RED
, 3);
886 R600_OUT_BATCH(r700
->CB_FOG_RED_R6XX
.u32All
);
887 R600_OUT_BATCH(r700
->CB_FOG_GREEN_R6XX
.u32All
);
888 R600_OUT_BATCH(r700
->CB_FOG_BLUE_R6XX
.u32All
);
892 BEGIN_BATCH_NO_AUTOSTATE(7);
893 R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK
, 2);
894 R600_OUT_BATCH(r700
->CB_TARGET_MASK
.u32All
);
895 R600_OUT_BATCH(r700
->CB_SHADER_MASK
.u32All
);
896 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL
, r700
->CB_SHADER_CONTROL
.u32All
);
901 static void r700SendCBCLRCMPState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
903 context_t
*context
= R700_CONTEXT(ctx
);
904 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
905 BATCH_LOCALS(&context
->radeon
);
907 BEGIN_BATCH_NO_AUTOSTATE(6);
908 R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL
, 4);
909 R600_OUT_BATCH(r700
->CB_CLRCMP_CONTROL
.u32All
);
910 R600_OUT_BATCH(r700
->CB_CLRCMP_SRC
.u32All
);
911 R600_OUT_BATCH(r700
->CB_CLRCMP_DST
.u32All
);
912 R600_OUT_BATCH(r700
->CB_CLRCMP_MSK
.u32All
);
917 static void r700SendCBBlendState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
919 context_t
*context
= R700_CONTEXT(ctx
);
920 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
921 BATCH_LOCALS(&context
->radeon
);
923 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
925 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
926 BEGIN_BATCH_NO_AUTOSTATE(3);
927 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL
, r700
->CB_BLEND_CONTROL
.u32All
);
931 BEGIN_BATCH_NO_AUTOSTATE(3);
932 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL
, r700
->CB_COLOR_CONTROL
.u32All
);
935 if (context
->radeon
.radeonScreen
->chip_family
> CHIP_FAMILY_R600
) {
936 for (ui
= 0; ui
< R700_MAX_RENDER_TARGETS
; ui
++) {
937 if (r700
->render_target
[ui
].enabled
) {
938 BEGIN_BATCH_NO_AUTOSTATE(3);
939 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL
+ (4 * ui
),
940 r700
->render_target
[ui
].CB_BLEND0_CONTROL
.u32All
);
949 static void r700SendCBBlendColorState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
951 context_t
*context
= R700_CONTEXT(ctx
);
952 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
953 BATCH_LOCALS(&context
->radeon
);
954 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
956 BEGIN_BATCH_NO_AUTOSTATE(6);
957 R600_OUT_BATCH_REGSEQ(CB_BLEND_RED
, 4);
958 R600_OUT_BATCH(r700
->CB_BLEND_RED
.u32All
);
959 R600_OUT_BATCH(r700
->CB_BLEND_GREEN
.u32All
);
960 R600_OUT_BATCH(r700
->CB_BLEND_BLUE
.u32All
);
961 R600_OUT_BATCH(r700
->CB_BLEND_ALPHA
.u32All
);
966 static void r700SendSUState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
968 context_t
*context
= R700_CONTEXT(ctx
);
969 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
970 BATCH_LOCALS(&context
->radeon
);
972 BEGIN_BATCH_NO_AUTOSTATE(9);
973 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL
, r700
->PA_SU_SC_MODE_CNTL
.u32All
);
974 R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE
, 4);
975 R600_OUT_BATCH(r700
->PA_SU_POINT_SIZE
.u32All
);
976 R600_OUT_BATCH(r700
->PA_SU_POINT_MINMAX
.u32All
);
977 R600_OUT_BATCH(r700
->PA_SU_LINE_CNTL
.u32All
);
978 R600_OUT_BATCH(r700
->PA_SU_VTX_CNTL
.u32All
);
984 static void r700SendPolyState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
986 context_t
*context
= R700_CONTEXT(ctx
);
987 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
988 BATCH_LOCALS(&context
->radeon
);
990 BEGIN_BATCH_NO_AUTOSTATE(10);
991 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL
, 2);
992 R600_OUT_BATCH(r700
->PA_SU_POLY_OFFSET_DB_FMT_CNTL
.u32All
);
993 R600_OUT_BATCH(r700
->PA_SU_POLY_OFFSET_CLAMP
.u32All
);
994 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
995 R600_OUT_BATCH(r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.u32All
);
996 R600_OUT_BATCH(r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.u32All
);
997 R600_OUT_BATCH(r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.u32All
);
998 R600_OUT_BATCH(r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.u32All
);
1004 static void r700SendCLState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1006 context_t
*context
= R700_CONTEXT(ctx
);
1007 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
1008 BATCH_LOCALS(&context
->radeon
);
1009 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
1011 BEGIN_BATCH_NO_AUTOSTATE(12);
1012 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL
, r700
->PA_CL_CLIP_CNTL
.u32All
);
1013 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL
, r700
->PA_CL_VTE_CNTL
.u32All
);
1014 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL
, r700
->PA_CL_VS_OUT_CNTL
.u32All
);
1015 R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL
, r700
->PA_CL_NANINF_CNTL
.u32All
);
1020 static void r700SendGBState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1022 context_t
*context
= R700_CONTEXT(ctx
);
1023 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
1024 BATCH_LOCALS(&context
->radeon
);
1026 BEGIN_BATCH_NO_AUTOSTATE(6);
1027 R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ
, 4);
1028 R600_OUT_BATCH(r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
);
1029 R600_OUT_BATCH(r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
);
1030 R600_OUT_BATCH(r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
);
1031 R600_OUT_BATCH(r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
);
1036 static void r700SendScissorState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1038 context_t
*context
= R700_CONTEXT(ctx
);
1039 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
1040 BATCH_LOCALS(&context
->radeon
);
1041 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
1043 BEGIN_BATCH_NO_AUTOSTATE(22);
1044 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL
, 2);
1045 R600_OUT_BATCH(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
);
1046 R600_OUT_BATCH(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
);
1048 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET
, 12);
1049 R600_OUT_BATCH(r700
->PA_SC_WINDOW_OFFSET
.u32All
);
1050 R600_OUT_BATCH(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
);
1051 R600_OUT_BATCH(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
);
1052 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_RULE
.u32All
);
1053 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_0_TL
.u32All
);
1054 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_0_BR
.u32All
);
1055 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_1_TL
.u32All
);
1056 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_1_BR
.u32All
);
1057 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_2_TL
.u32All
);
1058 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_2_BR
.u32All
);
1059 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_3_TL
.u32All
);
1060 R600_OUT_BATCH(r700
->PA_SC_CLIPRECT_3_BR
.u32All
);
1062 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL
, 2);
1063 R600_OUT_BATCH(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
);
1064 R600_OUT_BATCH(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
);
1069 static void r700SendSCState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1071 context_t
*context
= R700_CONTEXT(ctx
);
1072 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
1073 BATCH_LOCALS(&context
->radeon
);
1074 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
1076 BEGIN_BATCH_NO_AUTOSTATE(15);
1077 R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE
, r700
->PA_SC_EDGERULE
.u32All
);
1078 R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE
, r700
->PA_SC_LINE_STIPPLE
.u32All
);
1079 R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL
, r700
->PA_SC_MPASS_PS_CNTL
.u32All
);
1080 R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL
, r700
->PA_SC_MODE_CNTL
.u32All
);
1081 R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL
, r700
->PA_SC_LINE_CNTL
.u32All
);
1086 static void r700SendAAState(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1088 context_t
*context
= R700_CONTEXT(ctx
);
1089 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
1090 BATCH_LOCALS(&context
->radeon
);
1092 BEGIN_BATCH_NO_AUTOSTATE(12);
1093 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG
, r700
->PA_SC_AA_CONFIG
.u32All
);
1094 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX
, r700
->PA_SC_AA_SAMPLE_LOCS_MCTX
.u32All
);
1095 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
, r700
->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
.u32All
);
1096 R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK
, r700
->PA_SC_AA_MASK
.u32All
);
1101 static void r700SendPSConsts(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1103 context_t
*context
= R700_CONTEXT(ctx
);
1104 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
1106 BATCH_LOCALS(&context
->radeon
);
1108 if (r700
->ps
.num_consts
== 0)
1111 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700
->ps
.num_consts
* 4));
1112 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST
, (r700
->ps
.num_consts
* 4)));
1113 /* assembler map const from very beginning. */
1114 R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET
* 4);
1115 for (i
= 0; i
< r700
->ps
.num_consts
; i
++) {
1116 R600_OUT_BATCH(r700
->ps
.consts
[i
][0].u32All
);
1117 R600_OUT_BATCH(r700
->ps
.consts
[i
][1].u32All
);
1118 R600_OUT_BATCH(r700
->ps
.consts
[i
][2].u32All
);
1119 R600_OUT_BATCH(r700
->ps
.consts
[i
][3].u32All
);
1125 static void r700SendVSConsts(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1127 context_t
*context
= R700_CONTEXT(ctx
);
1128 R700_CHIP_CONTEXT
*r700
= R700_CONTEXT_STATES(context
);
1130 BATCH_LOCALS(&context
->radeon
);
1131 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
1133 if (r700
->vs
.num_consts
== 0)
1136 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700
->vs
.num_consts
* 4));
1137 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST
, (r700
->vs
.num_consts
* 4)));
1138 /* assembler map const from very beginning. */
1139 R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET
* 4);
1140 for (i
= 0; i
< r700
->vs
.num_consts
; i
++) {
1141 R600_OUT_BATCH(r700
->vs
.consts
[i
][0].u32All
);
1142 R600_OUT_BATCH(r700
->vs
.consts
[i
][1].u32All
);
1143 R600_OUT_BATCH(r700
->vs
.consts
[i
][2].u32All
);
1144 R600_OUT_BATCH(r700
->vs
.consts
[i
][3].u32All
);
1150 static void r700SendQueryBegin(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1152 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
1153 struct radeon_query_object
*query
= radeon
->query
.current
;
1154 BATCH_LOCALS(radeon
);
1155 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, "%s\n", __func__
);
1157 /* clear the buffer */
1158 radeon_bo_map(query
->bo
, GL_FALSE
);
1159 memset(query
->bo
->ptr
, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
1160 radeon_bo_unmap(query
->bo
);
1162 radeon_cs_space_check_with_bo(radeon
->cmdbuf
.cs
,
1164 0, RADEON_GEM_DOMAIN_GTT
);
1166 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
1167 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE
, 2));
1168 R600_OUT_BATCH(ZPASS_DONE
);
1169 R600_OUT_BATCH(query
->curr_offset
); /* hw writes qwords */
1170 R600_OUT_BATCH(0x00000000);
1171 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR
, query
->bo
, 0, 0, RADEON_GEM_DOMAIN_GTT
, 0);
1173 query
->emitted_begin
= GL_TRUE
;
1176 static int check_always(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1178 return atom
->cmd_size
;
1181 static int check_cb(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1183 context_t
*context
= R700_CONTEXT(ctx
);
1186 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1188 radeon_print(RADEON_STATE
, RADEON_TRACE
, "%s %d\n", __func__
, count
);
1193 static int check_blnd(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1195 context_t
*context
= R700_CONTEXT(ctx
);
1196 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1200 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1203 if (context
->radeon
.radeonScreen
->chip_family
> CHIP_FAMILY_R600
) {
1204 /* targets are enabled in r700SetRenderTarget but state
1205 size is calculated before that. Until MRT's are done
1206 hardcode target0 as enabled. */
1208 for (ui
= 1; ui
< R700_MAX_RENDER_TARGETS
; ui
++) {
1209 if (r700
->render_target
[ui
].enabled
)
1213 radeon_print(RADEON_STATE
, RADEON_TRACE
, "%s %d\n", __func__
, count
);
1218 static int check_ucp(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1220 context_t
*context
= R700_CONTEXT(ctx
);
1221 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1225 for (i
= 0; i
< R700_MAX_UCP
; i
++) {
1226 if (r700
->ucp
[i
].enabled
)
1229 radeon_print(RADEON_STATE
, RADEON_TRACE
, "%s %d\n", __func__
, count
);
1233 static int check_vtx(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1235 context_t
*context
= R700_CONTEXT(ctx
);
1236 int count
= context
->radeon
.tcl
.aos_count
* 18;
1241 radeon_print(RADEON_STATE
, RADEON_TRACE
, "%s %d\n", __func__
, count
);
1245 static int check_tx(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1247 context_t
*context
= R700_CONTEXT(ctx
);
1248 unsigned int i
, count
= 0;
1249 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1251 for (i
= 0; i
< R700_TEXTURE_NUMBERUNITS
; i
++) {
1252 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
1253 radeonTexObj
*t
= r700
->textures
[i
];
1258 radeon_print(RADEON_STATE
, RADEON_TRACE
, "%s %d\n", __func__
, count
);
1262 static int check_ps_consts(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1264 context_t
*context
= R700_CONTEXT(ctx
);
1265 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1266 int count
= r700
->ps
.num_consts
* 4;
1270 radeon_print(RADEON_STATE
, RADEON_TRACE
, "%s %d\n", __func__
, count
);
1275 static int check_vs_consts(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1277 context_t
*context
= R700_CONTEXT(ctx
);
1278 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1279 int count
= r700
->vs
.num_consts
* 4;
1283 radeon_print(RADEON_STATE
, RADEON_TRACE
, "%s %d\n", __func__
, count
);
1288 static int check_queryobj(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
1290 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
1291 struct radeon_query_object
*query
= radeon
->query
.current
;
1294 if (!query
|| query
->emitted_begin
)
1297 count
= atom
->cmd_size
;
1298 radeon_print(RADEON_STATE
, RADEON_TRACE
, "%s %d\n", __func__
, count
);
1302 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
1304 context->atoms.ATOM.cmd_size = (SZ); \
1305 context->atoms.ATOM.cmd = NULL; \
1306 context->atoms.ATOM.name = #ATOM; \
1307 context->atoms.ATOM.idx = 0; \
1308 context->atoms.ATOM.check = check_##CHK; \
1309 context->atoms.ATOM.dirty = GL_FALSE; \
1310 context->atoms.ATOM.emit = (EMIT); \
1311 context->radeon.hw.max_state_size += (SZ); \
1312 insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1315 static void r600_init_query_stateobj(radeonContextPtr radeon
, int SZ
)
1317 radeon
->query
.queryobj
.cmd_size
= (SZ
);
1318 radeon
->query
.queryobj
.cmd
= NULL
;
1319 radeon
->query
.queryobj
.name
= "queryobj";
1320 radeon
->query
.queryobj
.idx
= 0;
1321 radeon
->query
.queryobj
.check
= check_queryobj
;
1322 radeon
->query
.queryobj
.dirty
= GL_FALSE
;
1323 radeon
->query
.queryobj
.emit
= r700SendQueryBegin
;
1324 radeon
->hw
.max_state_size
+= (SZ
);
1325 insert_at_tail(&radeon
->hw
.atomlist
, &radeon
->query
.queryobj
);
1328 void r600InitAtoms(context_t
*context
)
1330 radeon_print(RADEON_STATE
, RADEON_NORMAL
, "%s %p\n", __func__
, context
);
1331 context
->radeon
.hw
.max_state_size
= 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1333 /* Setup the atom linked list */
1334 make_empty_list(&context
->radeon
.hw
.atomlist
);
1335 context
->radeon
.hw
.atomlist
.name
= "atom-list";
1337 ALLOC_STATE(sq
, always
, 34, r700SendSQConfig
);
1338 ALLOC_STATE(db
, always
, 17, r700SendDBState
);
1339 ALLOC_STATE(stencil
, always
, 4, r700SendStencilState
);
1340 ALLOC_STATE(db_target
, always
, 12, r700SendDepthTargetState
);
1341 ALLOC_STATE(sc
, always
, 15, r700SendSCState
);
1342 ALLOC_STATE(scissor
, always
, 22, r700SendScissorState
);
1343 ALLOC_STATE(aa
, always
, 12, r700SendAAState
);
1344 ALLOC_STATE(cl
, always
, 12, r700SendCLState
);
1345 ALLOC_STATE(gb
, always
, 6, r700SendGBState
);
1346 ALLOC_STATE(ucp
, ucp
, (R700_MAX_UCP
* 6), r700SendUCPState
);
1347 ALLOC_STATE(su
, always
, 9, r700SendSUState
);
1348 ALLOC_STATE(poly
, always
, 10, r700SendPolyState
);
1349 ALLOC_STATE(cb
, cb
, 18, r700SendCBState
);
1350 ALLOC_STATE(clrcmp
, always
, 6, r700SendCBCLRCMPState
);
1351 ALLOC_STATE(cb_target
, always
, 25, r700SendRenderTargetState
);
1352 ALLOC_STATE(blnd
, blnd
, (6 + (R700_MAX_RENDER_TARGETS
* 3)), r700SendCBBlendState
);
1353 ALLOC_STATE(blnd_clr
, always
, 6, r700SendCBBlendColorState
);
1354 ALLOC_STATE(sx
, always
, 9, r700SendSXState
);
1355 ALLOC_STATE(vgt
, always
, 41, r700SendVGTState
);
1356 ALLOC_STATE(spi
, always
, (59 + R700_MAX_SHADER_EXPORTS
), r700SendSPIState
);
1357 ALLOC_STATE(vpt
, always
, 16, r700SendViewportState
);
1358 ALLOC_STATE(fs
, always
, 18, r700SendFSState
);
1359 ALLOC_STATE(vs
, always
, 21, r700SendVSState
);
1360 ALLOC_STATE(ps
, always
, 24, r700SendPSState
);
1361 ALLOC_STATE(vs_consts
, vs_consts
, (2 + (R700_MAX_DX9_CONSTS
* 4)), r700SendVSConsts
);
1362 ALLOC_STATE(ps_consts
, ps_consts
, (2 + (R700_MAX_DX9_CONSTS
* 4)), r700SendPSConsts
);
1363 ALLOC_STATE(vtx
, vtx
, (6 + (VERT_ATTRIB_MAX
* 18)), r700SendVTXState
);
1364 ALLOC_STATE(tx
, tx
, (R700_TEXTURE_NUMBERUNITS
* 20), r700SendTexState
);
1365 ALLOC_STATE(tx_smplr
, tx
, (R700_TEXTURE_NUMBERUNITS
* 5), r700SendTexSamplerState
);
1366 ALLOC_STATE(tx_brdr_clr
, tx
, (R700_TEXTURE_NUMBERUNITS
* 6), r700SendTexBorderColorState
);
1367 r600_init_query_stateobj(&context
->radeon
, 6 * 2);
1369 context
->radeon
.hw
.is_dirty
= GL_TRUE
;
1370 context
->radeon
.hw
.all_dirty
= GL_TRUE
;