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[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "r700_state.h"
35 #include "r700_tex.h"
36 #include "r700_oglprog.h"
37 #include "r700_fragprog.h"
38 #include "r700_vertprog.h"
39 #include "r700_ioctl.h"
40
41 #define LINK_STATES(reg) \
42 do \
43 { \
44 pStateListWork->puiValue = (unsigned int*)&(r700->reg); \
45 pStateListWork->unOffset = mm##reg - ASIC_CONTEXT_BASE_INDEX; \
46 pStateListWork->pNext = pStateListWork + 1; \
47 pStateListWork++; \
48 }while(0)
49
50 GLboolean r700InitChipObject(context_t *context)
51 {
52 ContextState * pStateListWork;
53
54 R700_CHIP_CONTEXT *r700 = &context->hw;
55
56 /* init state list */
57 r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int));
58 pStateListWork = r700->pStateList;
59
60 LINK_STATES(DB_DEPTH_SIZE);
61 LINK_STATES(DB_DEPTH_VIEW);
62
63 LINK_STATES(DB_DEPTH_BASE);
64 LINK_STATES(DB_DEPTH_INFO);
65 LINK_STATES(DB_HTILE_DATA_BASE);
66
67 LINK_STATES(DB_STENCIL_CLEAR);
68 LINK_STATES(DB_DEPTH_CLEAR);
69
70 LINK_STATES(PA_SC_SCREEN_SCISSOR_TL);
71 LINK_STATES(PA_SC_SCREEN_SCISSOR_BR);
72
73 LINK_STATES(CB_COLOR0_BASE);
74
75 LINK_STATES(CB_COLOR0_SIZE);
76
77 LINK_STATES(CB_COLOR0_VIEW);
78
79 LINK_STATES(CB_COLOR0_INFO);
80 LINK_STATES(CB_COLOR1_INFO);
81 LINK_STATES(CB_COLOR2_INFO);
82 LINK_STATES(CB_COLOR3_INFO);
83 LINK_STATES(CB_COLOR4_INFO);
84 LINK_STATES(CB_COLOR5_INFO);
85 LINK_STATES(CB_COLOR6_INFO);
86 LINK_STATES(CB_COLOR7_INFO);
87
88 LINK_STATES(CB_COLOR0_TILE);
89
90 LINK_STATES(CB_COLOR0_FRAG);
91
92 LINK_STATES(CB_COLOR0_MASK);
93
94 LINK_STATES(PA_SC_WINDOW_OFFSET);
95 LINK_STATES(PA_SC_WINDOW_SCISSOR_TL);
96 LINK_STATES(PA_SC_WINDOW_SCISSOR_BR);
97 LINK_STATES(PA_SC_CLIPRECT_RULE);
98 LINK_STATES(PA_SC_CLIPRECT_0_TL);
99 LINK_STATES(PA_SC_CLIPRECT_0_BR);
100 LINK_STATES(PA_SC_CLIPRECT_1_TL);
101 LINK_STATES(PA_SC_CLIPRECT_1_BR);
102 LINK_STATES(PA_SC_CLIPRECT_2_TL);
103 LINK_STATES(PA_SC_CLIPRECT_2_BR);
104 LINK_STATES(PA_SC_CLIPRECT_3_TL);
105 LINK_STATES(PA_SC_CLIPRECT_3_BR);
106
107 LINK_STATES(PA_SC_EDGERULE);
108
109 LINK_STATES(CB_TARGET_MASK);
110 LINK_STATES(CB_SHADER_MASK);
111 LINK_STATES(PA_SC_GENERIC_SCISSOR_TL);
112 LINK_STATES(PA_SC_GENERIC_SCISSOR_BR);
113
114 LINK_STATES(PA_SC_VPORT_SCISSOR_0_TL);
115 LINK_STATES(PA_SC_VPORT_SCISSOR_0_BR);
116 LINK_STATES(PA_SC_VPORT_SCISSOR_1_TL);
117 LINK_STATES(PA_SC_VPORT_SCISSOR_1_BR);
118
119 LINK_STATES(PA_SC_VPORT_ZMIN_0);
120 LINK_STATES(PA_SC_VPORT_ZMAX_0);
121
122 LINK_STATES(SX_MISC);
123
124 LINK_STATES(SQ_VTX_SEMANTIC_0);
125 LINK_STATES(SQ_VTX_SEMANTIC_1);
126 LINK_STATES(SQ_VTX_SEMANTIC_2);
127 LINK_STATES(SQ_VTX_SEMANTIC_3);
128 LINK_STATES(SQ_VTX_SEMANTIC_4);
129 LINK_STATES(SQ_VTX_SEMANTIC_5);
130 LINK_STATES(SQ_VTX_SEMANTIC_6);
131 LINK_STATES(SQ_VTX_SEMANTIC_7);
132 LINK_STATES(SQ_VTX_SEMANTIC_8);
133 LINK_STATES(SQ_VTX_SEMANTIC_9);
134 LINK_STATES(SQ_VTX_SEMANTIC_10);
135 LINK_STATES(SQ_VTX_SEMANTIC_11);
136 LINK_STATES(SQ_VTX_SEMANTIC_12);
137 LINK_STATES(SQ_VTX_SEMANTIC_13);
138 LINK_STATES(SQ_VTX_SEMANTIC_14);
139 LINK_STATES(SQ_VTX_SEMANTIC_15);
140 LINK_STATES(SQ_VTX_SEMANTIC_16);
141 LINK_STATES(SQ_VTX_SEMANTIC_17);
142 LINK_STATES(SQ_VTX_SEMANTIC_18);
143 LINK_STATES(SQ_VTX_SEMANTIC_19);
144 LINK_STATES(SQ_VTX_SEMANTIC_20);
145 LINK_STATES(SQ_VTX_SEMANTIC_21);
146 LINK_STATES(SQ_VTX_SEMANTIC_22);
147 LINK_STATES(SQ_VTX_SEMANTIC_23);
148 LINK_STATES(SQ_VTX_SEMANTIC_24);
149 LINK_STATES(SQ_VTX_SEMANTIC_25);
150 LINK_STATES(SQ_VTX_SEMANTIC_26);
151 LINK_STATES(SQ_VTX_SEMANTIC_27);
152 LINK_STATES(SQ_VTX_SEMANTIC_28);
153 LINK_STATES(SQ_VTX_SEMANTIC_29);
154 LINK_STATES(SQ_VTX_SEMANTIC_30);
155 LINK_STATES(SQ_VTX_SEMANTIC_31);
156
157 LINK_STATES(VGT_MAX_VTX_INDX);
158 LINK_STATES(VGT_MIN_VTX_INDX);
159 LINK_STATES(VGT_INDX_OFFSET);
160 LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX);
161 LINK_STATES(SX_ALPHA_TEST_CONTROL);
162
163 LINK_STATES(CB_BLEND_RED);
164 LINK_STATES(CB_BLEND_GREEN);
165 LINK_STATES(CB_BLEND_BLUE);
166 LINK_STATES(CB_BLEND_ALPHA);
167
168 LINK_STATES(PA_CL_VPORT_XSCALE);
169 LINK_STATES(PA_CL_VPORT_XOFFSET);
170 LINK_STATES(PA_CL_VPORT_YSCALE);
171 LINK_STATES(PA_CL_VPORT_YOFFSET);
172 LINK_STATES(PA_CL_VPORT_ZSCALE);
173 LINK_STATES(PA_CL_VPORT_ZOFFSET);
174
175 LINK_STATES(SPI_VS_OUT_ID_0);
176 LINK_STATES(SPI_VS_OUT_ID_1);
177 LINK_STATES(SPI_VS_OUT_ID_2);
178 LINK_STATES(SPI_VS_OUT_ID_3);
179 LINK_STATES(SPI_VS_OUT_ID_4);
180 LINK_STATES(SPI_VS_OUT_ID_5);
181 LINK_STATES(SPI_VS_OUT_ID_6);
182 LINK_STATES(SPI_VS_OUT_ID_7);
183 LINK_STATES(SPI_VS_OUT_ID_8);
184 LINK_STATES(SPI_VS_OUT_ID_9);
185
186 LINK_STATES(SPI_PS_INPUT_CNTL_0);
187 LINK_STATES(SPI_PS_INPUT_CNTL_1);
188 LINK_STATES(SPI_PS_INPUT_CNTL_2);
189 LINK_STATES(SPI_PS_INPUT_CNTL_3);
190 LINK_STATES(SPI_PS_INPUT_CNTL_4);
191 LINK_STATES(SPI_PS_INPUT_CNTL_5);
192 LINK_STATES(SPI_PS_INPUT_CNTL_6);
193 LINK_STATES(SPI_PS_INPUT_CNTL_7);
194 LINK_STATES(SPI_PS_INPUT_CNTL_8);
195 LINK_STATES(SPI_PS_INPUT_CNTL_9);
196 LINK_STATES(SPI_PS_INPUT_CNTL_10);
197 LINK_STATES(SPI_PS_INPUT_CNTL_11);
198 LINK_STATES(SPI_PS_INPUT_CNTL_12);
199 LINK_STATES(SPI_PS_INPUT_CNTL_13);
200 LINK_STATES(SPI_PS_INPUT_CNTL_14);
201 LINK_STATES(SPI_PS_INPUT_CNTL_15);
202 LINK_STATES(SPI_PS_INPUT_CNTL_16);
203 LINK_STATES(SPI_PS_INPUT_CNTL_17);
204 LINK_STATES(SPI_PS_INPUT_CNTL_18);
205 LINK_STATES(SPI_PS_INPUT_CNTL_19);
206 LINK_STATES(SPI_PS_INPUT_CNTL_20);
207 LINK_STATES(SPI_PS_INPUT_CNTL_21);
208 LINK_STATES(SPI_PS_INPUT_CNTL_22);
209 LINK_STATES(SPI_PS_INPUT_CNTL_23);
210 LINK_STATES(SPI_PS_INPUT_CNTL_24);
211 LINK_STATES(SPI_PS_INPUT_CNTL_25);
212 LINK_STATES(SPI_PS_INPUT_CNTL_26);
213 LINK_STATES(SPI_PS_INPUT_CNTL_27);
214 LINK_STATES(SPI_PS_INPUT_CNTL_28);
215 LINK_STATES(SPI_PS_INPUT_CNTL_29);
216 LINK_STATES(SPI_PS_INPUT_CNTL_30);
217 LINK_STATES(SPI_PS_INPUT_CNTL_31);
218 LINK_STATES(SPI_VS_OUT_CONFIG);
219 LINK_STATES(SPI_THREAD_GROUPING);
220 LINK_STATES(SPI_PS_IN_CONTROL_0);
221 LINK_STATES(SPI_PS_IN_CONTROL_1);
222 LINK_STATES(SPI_INTERP_CONTROL_0);
223
224 LINK_STATES(SPI_INPUT_Z);
225 LINK_STATES(SPI_FOG_CNTL);
226
227 LINK_STATES(CB_BLEND0_CONTROL);
228
229 LINK_STATES(CB_SHADER_CONTROL);
230
231 /*LINK_STATES(VGT_DRAW_INITIATOR); */
232
233 LINK_STATES(DB_DEPTH_CONTROL);
234
235 LINK_STATES(CB_COLOR_CONTROL);
236 LINK_STATES(DB_SHADER_CONTROL);
237 LINK_STATES(PA_CL_CLIP_CNTL);
238 LINK_STATES(PA_SU_SC_MODE_CNTL);
239 LINK_STATES(PA_CL_VTE_CNTL);
240 LINK_STATES(PA_CL_VS_OUT_CNTL);
241 LINK_STATES(PA_CL_NANINF_CNTL);
242
243 LINK_STATES(SQ_PGM_START_PS);
244 LINK_STATES(SQ_PGM_RESOURCES_PS);
245 LINK_STATES(SQ_PGM_EXPORTS_PS);
246 LINK_STATES(SQ_PGM_START_VS);
247 LINK_STATES(SQ_PGM_RESOURCES_VS);
248 LINK_STATES(SQ_PGM_START_GS);
249 LINK_STATES(SQ_PGM_RESOURCES_GS);
250 LINK_STATES(SQ_PGM_START_ES);
251 LINK_STATES(SQ_PGM_RESOURCES_ES);
252 LINK_STATES(SQ_PGM_START_FS);
253 LINK_STATES(SQ_PGM_RESOURCES_FS);
254 LINK_STATES(SQ_ESGS_RING_ITEMSIZE);
255 LINK_STATES(SQ_GSVS_RING_ITEMSIZE);
256 LINK_STATES(SQ_ESTMP_RING_ITEMSIZE);
257 LINK_STATES(SQ_GSTMP_RING_ITEMSIZE);
258 LINK_STATES(SQ_VSTMP_RING_ITEMSIZE);
259 LINK_STATES(SQ_PSTMP_RING_ITEMSIZE);
260 LINK_STATES(SQ_FBUF_RING_ITEMSIZE);
261 LINK_STATES(SQ_REDUC_RING_ITEMSIZE);
262 LINK_STATES(SQ_GS_VERT_ITEMSIZE);
263 LINK_STATES(SQ_PGM_CF_OFFSET_PS);
264 LINK_STATES(SQ_PGM_CF_OFFSET_VS);
265 LINK_STATES(SQ_PGM_CF_OFFSET_GS);
266 LINK_STATES(SQ_PGM_CF_OFFSET_ES);
267 LINK_STATES(SQ_PGM_CF_OFFSET_FS);
268
269 LINK_STATES(PA_SU_POINT_SIZE);
270 LINK_STATES(PA_SU_POINT_MINMAX);
271 LINK_STATES(PA_SU_LINE_CNTL);
272 LINK_STATES(PA_SC_LINE_STIPPLE);
273 LINK_STATES(VGT_OUTPUT_PATH_CNTL);
274
275 LINK_STATES(VGT_GS_MODE);
276
277 LINK_STATES(PA_SC_MPASS_PS_CNTL);
278 LINK_STATES(PA_SC_MODE_CNTL);
279
280 LINK_STATES(VGT_PRIMITIVEID_EN);
281 LINK_STATES(VGT_DMA_NUM_INSTANCES);
282
283 LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN);
284
285 LINK_STATES(VGT_INSTANCE_STEP_RATE_0);
286 LINK_STATES(VGT_INSTANCE_STEP_RATE_1);
287
288 LINK_STATES(VGT_STRMOUT_EN);
289 LINK_STATES(VGT_REUSE_OFF);
290
291 LINK_STATES(PA_SC_LINE_CNTL);
292 LINK_STATES(PA_SC_AA_CONFIG);
293 LINK_STATES(PA_SU_VTX_CNTL);
294 LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ);
295 LINK_STATES(PA_CL_GB_VERT_DISC_ADJ);
296 LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ);
297 LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ);
298 LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX);
299 LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX);
300
301 LINK_STATES(CB_CLRCMP_CONTROL);
302 LINK_STATES(CB_CLRCMP_SRC);
303 LINK_STATES(CB_CLRCMP_DST);
304 LINK_STATES(CB_CLRCMP_MSK);
305
306 LINK_STATES(PA_SC_AA_MASK);
307
308 LINK_STATES(VGT_VERTEX_REUSE_BLOCK_CNTL);
309 LINK_STATES(VGT_OUT_DEALLOC_CNTL);
310
311 LINK_STATES(DB_RENDER_CONTROL);
312 LINK_STATES(DB_RENDER_OVERRIDE);
313
314 LINK_STATES(DB_HTILE_SURFACE);
315
316 LINK_STATES(DB_ALPHA_TO_MASK);
317
318 LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL);
319 LINK_STATES(PA_SU_POLY_OFFSET_CLAMP);
320 LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE);
321 LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET);
322 LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE);
323
324 pStateListWork->puiValue = (unsigned int*)&(r700->PA_SU_POLY_OFFSET_BACK_OFFSET);
325 pStateListWork->unOffset = mmPA_SU_POLY_OFFSET_BACK_OFFSET - ASIC_CONTEXT_BASE_INDEX;
326 pStateListWork->pNext = NULL; /* END OF STATE LIST */
327
328 /* TODO : may need order sorting in case someone break the order of states in R700_CHIP_CONTEXT. */
329
330 return GL_TRUE;
331 }
332
333 void r700SetupVTXConstants(GLcontext * ctx,
334 unsigned int nStreamID,
335 void * pAos,
336 unsigned int size, /* number of elements in vector */
337 unsigned int stride,
338 unsigned int count) /* number of vectors in stream */
339 {
340 context_t *context = R700_CONTEXT(ctx);
341 uint32_t *dest;
342 struct radeon_aos * paos = (struct radeon_aos *)pAos;
343 offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF};
344
345 BATCH_LOCALS(&context->radeon);
346
347 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
348 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
349 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
350 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
351 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
352
353 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
354 uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1;
355
356 uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */
357 |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift
358 |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */
359 |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift
360 |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit;
361
362 uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift;
363
364 uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift;
365
366 BEGIN_BATCH_NO_AUTOSTATE(9);
367
368 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
369 R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
370
371 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
372 paos->bo,
373 uSQ_VTX_CONSTANT_WORD0_0,
374 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
375 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
376 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
377 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
378 R600_OUT_BATCH(0);
379 R600_OUT_BATCH(0);
380 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
381
382 END_BATCH();
383 COMMIT_BATCH();
384
385 }
386
387 int r700SetupStreams(GLcontext * ctx)
388 {
389 context_t *context = R700_CONTEXT(ctx);
390
391 BATCH_LOCALS(&context->radeon);
392
393 struct r700_vertex_program *vpc
394 = (struct r700_vertex_program *)ctx->VertexProgram._Current;
395
396 TNLcontext *tnl = TNL_CONTEXT(ctx);
397 struct vertex_buffer *vb = &tnl->vb;
398
399 unsigned int unBit;
400 unsigned int i;
401
402 BEGIN_BATCH_NO_AUTOSTATE(6);
403 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
404 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
405 R600_OUT_BATCH(0);
406
407 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
408 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
409 R600_OUT_BATCH(0);
410 END_BATCH();
411 COMMIT_BATCH();
412
413 //context->aos_count = 0;
414 for(i=0; i<VERT_ATTRIB_MAX; i++)
415 {
416 unBit = 1 << i;
417 if(vpc->mesa_program.Base.InputsRead & unBit)
418 {
419 rcommon_emit_vector(ctx,
420 &context->radeon.tcl.aos[i],
421 vb->AttribPtr[i]->data,
422 vb->AttribPtr[i]->size,
423 vb->AttribPtr[i]->stride,
424 vb->Count);
425
426 /* currently aos are packed */
427 r700SetupVTXConstants(ctx,
428 i,
429 (void*)(&context->radeon.tcl.aos[i]),
430 (unsigned int)vb->AttribPtr[i]->size,
431 (unsigned int)(vb->AttribPtr[i]->size * 4),
432 (unsigned int)vb->Count);
433 }
434 }
435
436 return R600_FALLBACK_NONE;
437 }
438
439 inline GLboolean needRelocReg(context_t *context, unsigned int reg)
440 {
441 switch (reg + ASIC_CONTEXT_BASE_INDEX)
442 {
443 case mmCB_COLOR0_BASE:
444 case mmCB_COLOR1_BASE:
445 case mmCB_COLOR2_BASE:
446 case mmCB_COLOR3_BASE:
447 case mmCB_COLOR4_BASE:
448 case mmCB_COLOR5_BASE:
449 case mmCB_COLOR6_BASE:
450 case mmCB_COLOR7_BASE:
451 case mmDB_DEPTH_BASE:
452 case mmSQ_PGM_START_VS:
453 case mmSQ_PGM_START_FS:
454 case mmSQ_PGM_START_ES:
455 case mmSQ_PGM_START_GS:
456 case mmSQ_PGM_START_PS:
457 return GL_TRUE;
458 break;
459 }
460
461 return GL_FALSE;
462 }
463
464 inline GLboolean setRelocReg(context_t *context, unsigned int reg)
465 {
466 BATCH_LOCALS(&context->radeon);
467 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
468
469 struct radeon_bo * pbo;
470 uint32_t voffset;
471 offset_modifiers offset_mod;
472
473 switch (reg + ASIC_CONTEXT_BASE_INDEX)
474 {
475 case mmCB_COLOR0_BASE:
476 case mmCB_COLOR1_BASE:
477 case mmCB_COLOR2_BASE:
478 case mmCB_COLOR3_BASE:
479 case mmCB_COLOR4_BASE:
480 case mmCB_COLOR5_BASE:
481 case mmCB_COLOR6_BASE:
482 case mmCB_COLOR7_BASE:
483 {
484 GLcontext *ctx = GL_CONTEXT(context);
485 struct radeon_renderbuffer *rrb;
486
487 rrb = radeon_get_colorbuffer(&context->radeon);
488 if (!rrb || !rrb->bo)
489 {
490 fprintf(stderr, "no rrb\n");
491 return GL_FALSE;
492 }
493
494 /* refer to radeonCreateScreen : screen->fbLocation = (temp & 0xffff) << 16; */
495 offset_mod.shift = NO_SHIFT;
496 offset_mod.shiftbits = 0;
497 offset_mod.mask = 0xFFFFFFFF;
498
499 R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All,
500 rrb->bo,
501 r700->CB_COLOR0_BASE.u32All,
502 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
503 return GL_TRUE;
504 }
505 break;
506 case mmDB_DEPTH_BASE:
507 {
508 GLcontext *ctx = GL_CONTEXT(context);
509 struct radeon_renderbuffer *rrb;
510 rrb = radeon_get_depthbuffer(&context->radeon);
511
512 offset_mod.shift = NO_SHIFT;
513 offset_mod.shiftbits = 0;
514 offset_mod.mask = 0xFFFFFFFF;
515
516 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
517 rrb->bo,
518 r700->DB_DEPTH_BASE.u32All,
519 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
520
521 return GL_TRUE;
522 }
523 break;
524 case mmSQ_PGM_START_VS:
525 {
526 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
527
528 offset_mod.shift = NO_SHIFT;
529 offset_mod.shiftbits = 0;
530 offset_mod.mask = 0xFFFFFFFF;
531
532 R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All,
533 pbo,
534 r700->SQ_PGM_START_VS.u32All,
535 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
536 return GL_TRUE;
537 }
538 break;
539 case mmSQ_PGM_START_FS:
540 case mmSQ_PGM_START_ES:
541 case mmSQ_PGM_START_GS:
542 case mmSQ_PGM_START_PS:
543 {
544 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
545
546 offset_mod.shift = NO_SHIFT;
547 offset_mod.shiftbits = 0;
548 offset_mod.mask = 0xFFFFFFFF;
549
550 voffset = 0;
551 R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All,
552 pbo,
553 r700->SQ_PGM_START_PS.u32All,
554 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
555 return GL_TRUE;
556 }
557 break;
558 }
559
560 return GL_FALSE;
561 }
562
563 GLboolean r700SendContextStates(context_t *context)
564 {
565 BATCH_LOCALS(&context->radeon);
566
567 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
568
569 ContextState * pState = r700->pStateList;
570 ContextState * pInit;
571 unsigned int toSend;
572 unsigned int ui;
573
574 while(NULL != pState)
575 {
576 toSend = 1;
577
578 pInit = pState;
579
580 if(GL_FALSE == needRelocReg(context, pState->unOffset))
581 {
582 while(NULL != pState->pNext)
583 {
584 if( ((pState->pNext->unOffset - pState->unOffset) > 1)
585 || (GL_TRUE == needRelocReg(context, pState->pNext->unOffset)) )
586 {
587 break;
588 }
589 else
590 {
591 pState = pState->pNext;
592 toSend++;
593 }
594 };
595 }
596
597 pState = pState->pNext;
598
599 BEGIN_BATCH_NO_AUTOSTATE(toSend + 2);
600 R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend);
601 for(ui=0; ui<toSend; ui++)
602 {
603 if( GL_FALSE == setRelocReg(context, pInit->unOffset) )
604 {
605 /* for not reloc reg. */
606 R600_OUT_BATCH(*(pInit->puiValue));
607 }
608 pInit = pInit->pNext;
609 };
610 END_BATCH();
611 };
612 COMMIT_BATCH();
613
614 return GL_TRUE;
615 }
616
617
618
619