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Merge branch 'mesa_7_7_branch'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30 #include "main/simple_list.h"
31
32 #include "r600_context.h"
33 #include "r600_cmdbuf.h"
34
35 #include "r700_state.h"
36 #include "r600_tex.h"
37 #include "r700_oglprog.h"
38 #include "r700_fragprog.h"
39 #include "r700_vertprog.h"
40 #include "r700_ioctl.h"
41
42 #include "radeon_mipmap_tree.h"
43
44 static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
45 {
46 context_t *context = R700_CONTEXT(ctx);
47 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
48
49 struct r700_vertex_program *vp = context->selected_vp;
50
51 struct radeon_bo *bo = NULL;
52 unsigned int i;
53 BATCH_LOCALS(&context->radeon);
54
55 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
56
57 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
58 if (ctx->Texture.Unit[i]._ReallyEnabled) {
59 radeonTexObj *t = r700->textures[i];
60 if (t) {
61 if (!t->image_override) {
62 bo = t->mt->bo;
63 } else {
64 bo = t->bo;
65 }
66 if (bo) {
67
68 r700SyncSurf(context, bo,
69 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
70 0, TC_ACTION_ENA_bit);
71
72 BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
73 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
74
75 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
76 { /* vs texture */
77 R600_OUT_BATCH((i + VERT_ATTRIB_MAX + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
78 }
79 else
80 {
81 R600_OUT_BATCH(i * 7);
82 }
83
84 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
85 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
86 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
87 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
88 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
89 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
90 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
91 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
92 bo,
93 r700->textures[i]->SQ_TEX_RESOURCE2,
94 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
95 R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
96 bo,
97 r700->textures[i]->SQ_TEX_RESOURCE3,
98 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
99 END_BATCH();
100 COMMIT_BATCH();
101 }
102 }
103 }
104 }
105 }
106
107 #define SAMPLER_STRIDE 3
108
109 static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *atom)
110 {
111 context_t *context = R700_CONTEXT(ctx);
112 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
113 unsigned int i;
114
115 struct r700_vertex_program *vp = context->selected_vp;
116
117 BATCH_LOCALS(&context->radeon);
118 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
119
120 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
121 if (ctx->Texture.Unit[i]._ReallyEnabled) {
122 radeonTexObj *t = r700->textures[i];
123 if (t) {
124 BEGIN_BATCH_NO_AUTOSTATE(5);
125 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
126
127 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
128 { /* vs texture */
129 R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * SAMPLER_STRIDE); //work 1
130 }
131 else
132 {
133 R600_OUT_BATCH(i * 3);
134 }
135
136 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
137 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
138 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
139 END_BATCH();
140 COMMIT_BATCH();
141 }
142 }
143 }
144 }
145
146 static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom *atom)
147 {
148 context_t *context = R700_CONTEXT(ctx);
149 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
150 unsigned int i;
151 BATCH_LOCALS(&context->radeon);
152 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
153
154 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
155 if (ctx->Texture.Unit[i]._ReallyEnabled) {
156 radeonTexObj *t = r700->textures[i];
157 if (t) {
158 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
159 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
160 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
161 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
162 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
163 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
164 END_BATCH();
165 COMMIT_BATCH();
166 }
167 }
168 }
169 }
170
171 extern int getTypeSize(GLenum type);
172 static void r700SetupVTXConstants(GLcontext * ctx,
173 void * pAos,
174 StreamDesc * pStreamDesc)
175 {
176 context_t *context = R700_CONTEXT(ctx);
177 struct radeon_aos * paos = (struct radeon_aos *)pAos;
178 unsigned int nVBsize;
179 BATCH_LOCALS(&context->radeon);
180
181 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
182 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
183 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
184 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
185 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
186
187 if (!paos->bo)
188 return;
189
190 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
191 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
192 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
193 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
194 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
195 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
196 else
197 r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
198
199 if(0 == pStreamDesc->stride)
200 {
201 nVBsize = paos->count * pStreamDesc->size * getTypeSize(pStreamDesc->type);
202 }
203 else
204 {
205 nVBsize = paos->count * pStreamDesc->stride;
206 }
207
208 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
209 uSQ_VTX_CONSTANT_WORD1_0 = nVBsize - 1;
210
211 SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
212 SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
213 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
214 SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
215 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
216 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
217
218 if(GL_TRUE == pStreamDesc->normalize)
219 {
220 SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
221 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
222 }
223 //else
224 //{
225 // SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_INT,
226 // SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
227 //}
228
229 if(1 == pStreamDesc->_signed)
230 {
231 SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
232 }
233
234 SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
235 SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
236 SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
237
238 BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
239
240 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
241 R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
242 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
243 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
244 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
245 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
246 R600_OUT_BATCH(0);
247 R600_OUT_BATCH(0);
248 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
249 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
250 paos->bo,
251 uSQ_VTX_CONSTANT_WORD0_0,
252 RADEON_GEM_DOMAIN_GTT, 0, 0);
253 END_BATCH();
254 COMMIT_BATCH();
255
256 }
257
258 static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
259 {
260 context_t *context = R700_CONTEXT(ctx);
261 struct r700_vertex_program *vp = context->selected_vp;
262 unsigned int i, j = 0;
263 BATCH_LOCALS(&context->radeon);
264 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
265
266 if (context->radeon.tcl.aos_count == 0)
267 return;
268
269 BEGIN_BATCH_NO_AUTOSTATE(6);
270 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
271 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
272 R600_OUT_BATCH(0);
273
274 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
275 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
276 R600_OUT_BATCH(0);
277 END_BATCH();
278 COMMIT_BATCH();
279
280 for(i=0; i<VERT_ATTRIB_MAX; i++) {
281 if(vp->mesa_program->Base.InputsRead & (1 << i))
282 {
283 r700SetupVTXConstants(ctx,
284 (void*)(&context->radeon.tcl.aos[j]),
285 &(context->stream_desc[j]));
286 j++;
287 }
288 }
289 }
290
291 static void r700SetRenderTarget(context_t *context, int id)
292 {
293 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
294
295 struct radeon_renderbuffer *rrb;
296 unsigned int nPitchInPixel;
297
298 rrb = radeon_get_colorbuffer(&context->radeon);
299 if (!rrb || !rrb->bo) {
300 return;
301 }
302
303 R600_STATECHANGE(context, cb_target);
304
305 /* color buffer */
306 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
307
308 nPitchInPixel = rrb->pitch/rrb->cpp;
309 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
310 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
311 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
312 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
313 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
314 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
315 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
316 if(4 == rrb->cpp)
317 {
318 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
319 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
320 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
321 }
322 else
323 {
324 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
325 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
326 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
327 COMP_SWAP_shift, COMP_SWAP_mask);
328 }
329 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
330 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
331 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
332
333 r700->render_target[id].enabled = GL_TRUE;
334 }
335
336 static void r700SetDepthTarget(context_t *context)
337 {
338 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
339
340 struct radeon_renderbuffer *rrb;
341 unsigned int nPitchInPixel;
342
343 rrb = radeon_get_depthbuffer(&context->radeon);
344 if (!rrb)
345 return;
346
347 R600_STATECHANGE(context, db_target);
348
349 /* depth buf */
350 r700->DB_DEPTH_SIZE.u32All = 0;
351 r700->DB_DEPTH_BASE.u32All = 0;
352 r700->DB_DEPTH_INFO.u32All = 0;
353 r700->DB_DEPTH_VIEW.u32All = 0;
354
355 nPitchInPixel = rrb->pitch/rrb->cpp;
356
357 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
358 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
359 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
360 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
361
362 if(4 == rrb->cpp)
363 {
364 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
365 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
366 }
367 else
368 {
369 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
370 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
371 }
372 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
373 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
374 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
375 }
376
377 static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
378 {
379 context_t *context = R700_CONTEXT(ctx);
380 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
381 struct radeon_renderbuffer *rrb;
382 BATCH_LOCALS(&context->radeon);
383 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
384
385 rrb = radeon_get_depthbuffer(&context->radeon);
386 if (!rrb || !rrb->bo) {
387 return;
388 }
389
390 r700SetDepthTarget(context);
391
392 BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
393 R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
394 R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
395 R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
396 R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
397 R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
398 R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
399 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
400 rrb->bo,
401 r700->DB_DEPTH_BASE.u32All,
402 0, RADEON_GEM_DOMAIN_VRAM, 0);
403 END_BATCH();
404
405 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
406 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
407 BEGIN_BATCH_NO_AUTOSTATE(2);
408 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
409 R600_OUT_BATCH(1 << 0);
410 END_BATCH();
411 }
412
413 COMMIT_BATCH();
414
415 }
416
417 static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
418 {
419 context_t *context = R700_CONTEXT(ctx);
420 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
421 struct radeon_renderbuffer *rrb;
422 BATCH_LOCALS(&context->radeon);
423 int id = 0;
424 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
425
426 rrb = radeon_get_colorbuffer(&context->radeon);
427 if (!rrb || !rrb->bo) {
428 return;
429 }
430
431 r700SetRenderTarget(context, 0);
432
433 if (id > R700_MAX_RENDER_TARGETS)
434 return;
435
436 if (!r700->render_target[id].enabled)
437 return;
438
439 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
440 R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
441 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
442 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
443 rrb->bo,
444 r700->render_target[id].CB_COLOR0_BASE.u32All,
445 0, RADEON_GEM_DOMAIN_VRAM, 0);
446 END_BATCH();
447
448 if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
449 (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
450 BEGIN_BATCH_NO_AUTOSTATE(2);
451 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
452 R600_OUT_BATCH((2 << id));
453 END_BATCH();
454 }
455 /* Set CMASK & TILE buffer to the offset of color buffer as
456 * we don't use those this shouldn't cause any issue and we
457 * then have a valid cmd stream
458 */
459 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
460 R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
461 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
462 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
463 rrb->bo,
464 r700->render_target[id].CB_COLOR0_BASE.u32All,
465 0, RADEON_GEM_DOMAIN_VRAM, 0);
466 END_BATCH();
467 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
468 R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
469 R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All);
470 R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
471 rrb->bo,
472 r700->render_target[id].CB_COLOR0_BASE.u32All,
473 0, RADEON_GEM_DOMAIN_VRAM, 0);
474 END_BATCH();
475
476 BEGIN_BATCH_NO_AUTOSTATE(12);
477 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
478 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
479 R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
480 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
481 END_BATCH();
482
483 COMMIT_BATCH();
484
485 }
486
487 static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom)
488 {
489 context_t *context = R700_CONTEXT(ctx);
490 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
491 struct radeon_bo * pbo;
492 BATCH_LOCALS(&context->radeon);
493 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
494
495 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
496
497 if (!pbo)
498 return;
499
500 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
501
502 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
503 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
504 R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
505 R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
506 pbo,
507 r700->ps.SQ_PGM_START_PS.u32All,
508 RADEON_GEM_DOMAIN_GTT, 0, 0);
509 END_BATCH();
510
511 BEGIN_BATCH_NO_AUTOSTATE(9);
512 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
513 R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
514 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
515 END_BATCH();
516
517 BEGIN_BATCH_NO_AUTOSTATE(3);
518 R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
519 END_BATCH();
520
521 COMMIT_BATCH();
522
523 }
524
525 static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom)
526 {
527 context_t *context = R700_CONTEXT(ctx);
528 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
529 struct radeon_bo * pbo;
530 BATCH_LOCALS(&context->radeon);
531 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
532
533 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
534
535 if (!pbo)
536 return;
537
538 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
539
540 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
541 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
542 R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
543 R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
544 pbo,
545 r700->vs.SQ_PGM_START_VS.u32All,
546 RADEON_GEM_DOMAIN_GTT, 0, 0);
547 END_BATCH();
548
549 BEGIN_BATCH_NO_AUTOSTATE(6);
550 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
551 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
552 END_BATCH();
553
554 BEGIN_BATCH_NO_AUTOSTATE(3);
555 R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
556 //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
557 END_BATCH();
558
559 COMMIT_BATCH();
560 }
561
562 static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom)
563 {
564 context_t *context = R700_CONTEXT(ctx);
565 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
566 struct radeon_bo * pbo;
567 BATCH_LOCALS(&context->radeon);
568 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
569
570 /* XXX fixme
571 * R6xx chips require a FS be emitted, even if it's not used.
572 * since we aren't using FS yet, just send the VS address to make
573 * the kernel command checker happy
574 */
575 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
576 r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
577 r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
578 r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
579 /* XXX */
580
581 if (!pbo)
582 return;
583
584 r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
585
586 BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
587 R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
588 R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
589 R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
590 pbo,
591 r700->fs.SQ_PGM_START_FS.u32All,
592 RADEON_GEM_DOMAIN_GTT, 0, 0);
593 END_BATCH();
594
595 BEGIN_BATCH_NO_AUTOSTATE(6);
596 R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
597 R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
598 END_BATCH();
599
600 COMMIT_BATCH();
601
602 }
603
604 static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom)
605 {
606 context_t *context = R700_CONTEXT(ctx);
607 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
608 BATCH_LOCALS(&context->radeon);
609 int id = 0;
610 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
611
612 if (id > R700_MAX_VIEWPORTS)
613 return;
614
615 if (!r700->viewport[id].enabled)
616 return;
617
618 BEGIN_BATCH_NO_AUTOSTATE(16);
619 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
620 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
621 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
622 R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
623 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
624 R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
625 R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
626 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
627 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
628 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
629 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
630 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
631 R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
632 END_BATCH();
633
634 COMMIT_BATCH();
635
636 }
637
638 static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom)
639 {
640 context_t *context = R700_CONTEXT(ctx);
641 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
642 BATCH_LOCALS(&context->radeon);
643 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
644
645 BEGIN_BATCH_NO_AUTOSTATE(34);
646 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
647 R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
648 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
649 R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
650 R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
651 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
652 R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
653
654 R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
655 R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
656 R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
657 R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
658 R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
659
660 R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
661 R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
662 R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
663 R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
664 R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
665 R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
666 R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
667 R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
668 R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
669 R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
670 END_BATCH();
671
672 COMMIT_BATCH();
673 }
674
675 static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom)
676 {
677 context_t *context = R700_CONTEXT(ctx);
678 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
679 BATCH_LOCALS(&context->radeon);
680 int i;
681 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
682
683 for (i = 0; i < R700_MAX_UCP; i++) {
684 if (r700->ucp[i].enabled) {
685 BEGIN_BATCH_NO_AUTOSTATE(6);
686 R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
687 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
688 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
689 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
690 R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
691 END_BATCH();
692 COMMIT_BATCH();
693 }
694 }
695 }
696
697 static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom)
698 {
699 context_t *context = R700_CONTEXT(ctx);
700 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
701 BATCH_LOCALS(&context->radeon);
702 unsigned int ui;
703 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
704
705 BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
706
707 R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
708 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
709 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
710 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
711 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
712 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
713 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
714 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
715 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
716 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
717 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
718 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
719 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
720 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
721 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
722 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
723 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
724 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
725 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
726 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
727 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
728 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
729 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
730 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
731 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
732 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
733 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
734 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
735 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
736 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
737 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
738 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
739 R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
740
741 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
742 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
743 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
744 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
745 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
746 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
747 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
748 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
749 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
750 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
751 R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
752
753 R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
754 R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
755 R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
756 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
757 R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
758 R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
759 R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
760 R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
761 R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
762 R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
763
764 R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
765 for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
766 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
767
768 END_BATCH();
769 COMMIT_BATCH();
770 }
771
772 static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom)
773 {
774 context_t *context = R700_CONTEXT(ctx);
775 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
776 BATCH_LOCALS(&context->radeon);
777 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
778
779 BEGIN_BATCH_NO_AUTOSTATE(41);
780
781 R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
782 R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
783 R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
784 R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
785 R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
786
787 R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
788 R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
789 R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
790 R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
791 R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
792 R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
793 R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
794 R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
795 R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
796 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
797 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
798 R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
799 R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
800 R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
801
802 R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
803 R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
804 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
805 R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
806
807 R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
808 R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
809 R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
810 R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
811
812 R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
813
814 END_BATCH();
815 COMMIT_BATCH();
816 }
817
818 static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom)
819 {
820 context_t *context = R700_CONTEXT(ctx);
821 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
822 BATCH_LOCALS(&context->radeon);
823 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
824
825 BEGIN_BATCH_NO_AUTOSTATE(9);
826 R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
827 R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
828 R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
829 END_BATCH();
830 COMMIT_BATCH();
831 }
832
833 static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom)
834 {
835 context_t *context = R700_CONTEXT(ctx);
836 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
837 BATCH_LOCALS(&context->radeon);
838 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
839
840 BEGIN_BATCH_NO_AUTOSTATE(17);
841
842 R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
843 R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
844 R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
845
846 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
847 R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
848
849 R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
850 R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
851 R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
852
853 R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
854
855 END_BATCH();
856 COMMIT_BATCH();
857 }
858
859 static void r700SendStencilState(GLcontext *ctx, struct radeon_state_atom *atom)
860 {
861 context_t *context = R700_CONTEXT(ctx);
862 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
863 BATCH_LOCALS(&context->radeon);
864
865 BEGIN_BATCH_NO_AUTOSTATE(4);
866 R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
867 R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
868 R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
869 END_BATCH();
870 COMMIT_BATCH();
871 }
872
873 static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom)
874 {
875 context_t *context = R700_CONTEXT(ctx);
876 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
877 BATCH_LOCALS(&context->radeon);
878 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
879
880 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
881 BEGIN_BATCH_NO_AUTOSTATE(11);
882 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
883 R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
884 R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
885 R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
886 R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
887 R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
888 R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
889 R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
890 R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
891 END_BATCH();
892 }
893
894 BEGIN_BATCH_NO_AUTOSTATE(7);
895 R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
896 R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
897 R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
898 R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
899 END_BATCH();
900 COMMIT_BATCH();
901 }
902
903 static void r700SendCBCLRCMPState(GLcontext *ctx, struct radeon_state_atom *atom)
904 {
905 context_t *context = R700_CONTEXT(ctx);
906 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
907 BATCH_LOCALS(&context->radeon);
908
909 BEGIN_BATCH_NO_AUTOSTATE(6);
910 R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
911 R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
912 R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
913 R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
914 R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
915 END_BATCH();
916 COMMIT_BATCH();
917 }
918
919 static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom)
920 {
921 context_t *context = R700_CONTEXT(ctx);
922 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
923 BATCH_LOCALS(&context->radeon);
924 unsigned int ui;
925 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
926
927 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
928 BEGIN_BATCH_NO_AUTOSTATE(3);
929 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
930 END_BATCH();
931 }
932
933 BEGIN_BATCH_NO_AUTOSTATE(3);
934 R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
935 END_BATCH();
936
937 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
938 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
939 if (r700->render_target[ui].enabled) {
940 BEGIN_BATCH_NO_AUTOSTATE(3);
941 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
942 r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
943 END_BATCH();
944 }
945 }
946 }
947
948 COMMIT_BATCH();
949 }
950
951 static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom *atom)
952 {
953 context_t *context = R700_CONTEXT(ctx);
954 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
955 BATCH_LOCALS(&context->radeon);
956 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
957
958 BEGIN_BATCH_NO_AUTOSTATE(6);
959 R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
960 R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
961 R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
962 R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
963 R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
964 END_BATCH();
965 COMMIT_BATCH();
966 }
967
968 static void r700SendSUState(GLcontext *ctx, struct radeon_state_atom *atom)
969 {
970 context_t *context = R700_CONTEXT(ctx);
971 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
972 BATCH_LOCALS(&context->radeon);
973
974 BEGIN_BATCH_NO_AUTOSTATE(9);
975 R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
976 R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
977 R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
978 R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
979 R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
980 R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
981 END_BATCH();
982 COMMIT_BATCH();
983
984 }
985
986 static void r700SendPolyState(GLcontext *ctx, struct radeon_state_atom *atom)
987 {
988 context_t *context = R700_CONTEXT(ctx);
989 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
990 BATCH_LOCALS(&context->radeon);
991
992 BEGIN_BATCH_NO_AUTOSTATE(10);
993 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
994 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
995 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
996 R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
997 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
998 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
999 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
1000 R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
1001 END_BATCH();
1002 COMMIT_BATCH();
1003
1004 }
1005
1006 static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom)
1007 {
1008 context_t *context = R700_CONTEXT(ctx);
1009 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1010 BATCH_LOCALS(&context->radeon);
1011 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1012
1013 BEGIN_BATCH_NO_AUTOSTATE(12);
1014 R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
1015 R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
1016 R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
1017 R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
1018 END_BATCH();
1019 COMMIT_BATCH();
1020 }
1021
1022 static void r700SendGBState(GLcontext *ctx, struct radeon_state_atom *atom)
1023 {
1024 context_t *context = R700_CONTEXT(ctx);
1025 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1026 BATCH_LOCALS(&context->radeon);
1027
1028 BEGIN_BATCH_NO_AUTOSTATE(6);
1029 R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
1030 R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
1031 R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
1032 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
1033 R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
1034 END_BATCH();
1035 COMMIT_BATCH();
1036 }
1037
1038 static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom)
1039 {
1040 context_t *context = R700_CONTEXT(ctx);
1041 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1042 BATCH_LOCALS(&context->radeon);
1043 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1044
1045 BEGIN_BATCH_NO_AUTOSTATE(22);
1046 R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1047 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
1048 R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
1049
1050 R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
1051 R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
1052 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
1053 R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
1054 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
1055 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
1056 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
1057 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
1058 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
1059 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
1060 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
1061 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
1062 R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
1063
1064 R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1065 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
1066 R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
1067 END_BATCH();
1068 COMMIT_BATCH();
1069 }
1070
1071 static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom)
1072 {
1073 context_t *context = R700_CONTEXT(ctx);
1074 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1075 BATCH_LOCALS(&context->radeon);
1076 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1077
1078 BEGIN_BATCH_NO_AUTOSTATE(15);
1079 R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
1080 R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
1081 R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
1082 R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
1083 R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
1084 END_BATCH();
1085 COMMIT_BATCH();
1086 }
1087
1088 static void r700SendAAState(GLcontext *ctx, struct radeon_state_atom *atom)
1089 {
1090 context_t *context = R700_CONTEXT(ctx);
1091 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1092 BATCH_LOCALS(&context->radeon);
1093
1094 BEGIN_BATCH_NO_AUTOSTATE(12);
1095 R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
1096 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
1097 R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
1098 R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
1099 END_BATCH();
1100 COMMIT_BATCH();
1101 }
1102
1103 static void r700SendPSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1104 {
1105 context_t *context = R700_CONTEXT(ctx);
1106 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1107 int i;
1108 BATCH_LOCALS(&context->radeon);
1109
1110 if (r700->ps.num_consts == 0)
1111 return;
1112
1113 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
1114 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
1115 /* assembler map const from very beginning. */
1116 R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
1117 for (i = 0; i < r700->ps.num_consts; i++) {
1118 R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
1119 R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
1120 R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
1121 R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
1122 }
1123 END_BATCH();
1124 COMMIT_BATCH();
1125 }
1126
1127 static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom)
1128 {
1129 context_t *context = R700_CONTEXT(ctx);
1130 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1131 int i;
1132 BATCH_LOCALS(&context->radeon);
1133 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1134
1135 if (r700->vs.num_consts == 0)
1136 return;
1137
1138 BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
1139 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
1140 /* assembler map const from very beginning. */
1141 R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
1142 for (i = 0; i < r700->vs.num_consts; i++) {
1143 R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
1144 R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
1145 R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
1146 R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
1147 }
1148 END_BATCH();
1149 COMMIT_BATCH();
1150 }
1151
1152 static void r700SendQueryBegin(GLcontext *ctx, struct radeon_state_atom *atom)
1153 {
1154 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1155 struct radeon_query_object *query = radeon->query.current;
1156 BATCH_LOCALS(radeon);
1157 radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1158
1159 /* clear the buffer */
1160 radeon_bo_map(query->bo, GL_FALSE);
1161 memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
1162 radeon_bo_unmap(query->bo);
1163
1164 radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
1165 query->bo,
1166 0, RADEON_GEM_DOMAIN_GTT);
1167
1168 BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
1169 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
1170 R600_OUT_BATCH(ZPASS_DONE);
1171 R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
1172 R600_OUT_BATCH(0x00000000);
1173 R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
1174 END_BATCH();
1175 query->emitted_begin = GL_TRUE;
1176 }
1177
1178 static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
1179 {
1180 return atom->cmd_size;
1181 }
1182
1183 static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom)
1184 {
1185 context_t *context = R700_CONTEXT(ctx);
1186 int count = 7;
1187
1188 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1189 count += 11;
1190 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1191
1192 return count;
1193 }
1194
1195 static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom)
1196 {
1197 context_t *context = R700_CONTEXT(ctx);
1198 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1199 unsigned int ui;
1200 int count = 3;
1201
1202 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1203 count += 3;
1204
1205 if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1206 /* targets are enabled in r700SetRenderTarget but state
1207 size is calculated before that. Until MRT's are done
1208 hardcode target0 as enabled. */
1209 count += 3;
1210 for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) {
1211 if (r700->render_target[ui].enabled)
1212 count += 3;
1213 }
1214 }
1215 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1216
1217 return count;
1218 }
1219
1220 static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom)
1221 {
1222 context_t *context = R700_CONTEXT(ctx);
1223 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1224 int i;
1225 int count = 0;
1226
1227 for (i = 0; i < R700_MAX_UCP; i++) {
1228 if (r700->ucp[i].enabled)
1229 count += 6;
1230 }
1231 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1232 return count;
1233 }
1234
1235 static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom)
1236 {
1237 context_t *context = R700_CONTEXT(ctx);
1238 int count = context->radeon.tcl.aos_count * 18;
1239
1240 if (count)
1241 count += 6;
1242
1243 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1244 return count;
1245 }
1246
1247 static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
1248 {
1249 context_t *context = R700_CONTEXT(ctx);
1250 unsigned int i, count = 0;
1251 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1252
1253 for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
1254 if (ctx->Texture.Unit[i]._ReallyEnabled) {
1255 radeonTexObj *t = r700->textures[i];
1256 if (t)
1257 count++;
1258 }
1259 }
1260 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1261 return count * 31;
1262 }
1263
1264 static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1265 {
1266 context_t *context = R700_CONTEXT(ctx);
1267 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1268 int count = r700->ps.num_consts * 4;
1269
1270 if (count)
1271 count += 2;
1272 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1273
1274 return count;
1275 }
1276
1277 static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom)
1278 {
1279 context_t *context = R700_CONTEXT(ctx);
1280 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1281 int count = r700->vs.num_consts * 4;
1282
1283 if (count)
1284 count += 2;
1285 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1286
1287 return count;
1288 }
1289
1290 static int check_queryobj(GLcontext *ctx, struct radeon_state_atom *atom)
1291 {
1292 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1293 struct radeon_query_object *query = radeon->query.current;
1294 int count;
1295
1296 if (!query || query->emitted_begin)
1297 count = 0;
1298 else
1299 count = atom->cmd_size;
1300 radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1301 return count;
1302 }
1303
1304 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT ) \
1305 do { \
1306 context->atoms.ATOM.cmd_size = (SZ); \
1307 context->atoms.ATOM.cmd = NULL; \
1308 context->atoms.ATOM.name = #ATOM; \
1309 context->atoms.ATOM.idx = 0; \
1310 context->atoms.ATOM.check = check_##CHK; \
1311 context->atoms.ATOM.dirty = GL_FALSE; \
1312 context->atoms.ATOM.emit = (EMIT); \
1313 context->radeon.hw.max_state_size += (SZ); \
1314 insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1315 } while (0)
1316
1317 static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
1318 {
1319 radeon->query.queryobj.cmd_size = (SZ);
1320 radeon->query.queryobj.cmd = NULL;
1321 radeon->query.queryobj.name = "queryobj";
1322 radeon->query.queryobj.idx = 0;
1323 radeon->query.queryobj.check = check_queryobj;
1324 radeon->query.queryobj.dirty = GL_FALSE;
1325 radeon->query.queryobj.emit = r700SendQueryBegin;
1326 radeon->hw.max_state_size += (SZ);
1327 insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
1328 }
1329
1330 void r600InitAtoms(context_t *context)
1331 {
1332 radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1333 context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1334
1335 /* Setup the atom linked list */
1336 make_empty_list(&context->radeon.hw.atomlist);
1337 context->radeon.hw.atomlist.name = "atom-list";
1338
1339 ALLOC_STATE(sq, always, 34, r700SendSQConfig);
1340 ALLOC_STATE(db, always, 17, r700SendDBState);
1341 ALLOC_STATE(stencil, always, 4, r700SendStencilState);
1342 ALLOC_STATE(db_target, always, 12, r700SendDepthTargetState);
1343 ALLOC_STATE(sc, always, 15, r700SendSCState);
1344 ALLOC_STATE(scissor, always, 22, r700SendScissorState);
1345 ALLOC_STATE(aa, always, 12, r700SendAAState);
1346 ALLOC_STATE(cl, always, 12, r700SendCLState);
1347 ALLOC_STATE(gb, always, 6, r700SendGBState);
1348 ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
1349 ALLOC_STATE(su, always, 9, r700SendSUState);
1350 ALLOC_STATE(poly, always, 10, r700SendPolyState);
1351 ALLOC_STATE(cb, cb, 18, r700SendCBState);
1352 ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
1353 ALLOC_STATE(cb_target, always, 25, r700SendRenderTargetState);
1354 ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
1355 ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
1356 ALLOC_STATE(sx, always, 9, r700SendSXState);
1357 ALLOC_STATE(vgt, always, 41, r700SendVGTState);
1358 ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
1359 ALLOC_STATE(vpt, always, 16, r700SendViewportState);
1360 ALLOC_STATE(fs, always, 18, r700SendFSState);
1361 ALLOC_STATE(vs, always, 21, r700SendVSState);
1362 ALLOC_STATE(ps, always, 24, r700SendPSState);
1363 ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
1364 ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
1365 ALLOC_STATE(vtx, vtx, (6 + (VERT_ATTRIB_MAX * 18)), r700SendVTXState);
1366 ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
1367 ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
1368 ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
1369 r600_init_query_stateobj(&context->radeon, 6 * 2);
1370
1371 context->radeon.hw.is_dirty = GL_TRUE;
1372 context->radeon.hw.all_dirty = GL_TRUE;
1373 }