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[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
26 */
27
28 #include "main/imports.h"
29 #include "main/glheader.h"
30
31 #include "r600_context.h"
32 #include "r600_cmdbuf.h"
33
34 #include "r700_chip.h"
35 #include "r700_state.h"
36 #include "r700_tex.h"
37 #include "r700_oglprog.h"
38 #include "r700_fragprog.h"
39 #include "r700_vertprog.h"
40 #include "r700_ioctl.h"
41
42 extern const struct tnl_pipeline_stage *r700_pipeline[];
43
44 static GLboolean r700DestroyChipObj(GLcontext * ctx)
45 {
46 context_t * context = R700_CONTEXT(ctx);
47 R700_CHIP_CONTEXT *r700;
48
49 if(NULL == context->chipobj.pvChipObj)
50 {
51 return GL_TRUE;
52 }
53
54 r700 = (R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj);
55
56 FREE(r700->pStateList);
57
58 FREE(r700);
59
60 return GL_TRUE;
61 }
62
63 static void r700InitFuncs(struct dd_function_table *functions)
64 {
65 r700InitStateFuncs(functions);
66 r700InitTextureFuncs(functions);
67 r700InitShaderFuncs(functions);
68 r700InitIoctlFuncs(functions);
69 }
70
71 #define LINK_STATES(reg) \
72 do \
73 { \
74 pStateListWork->puiValue = (unsigned int*)&(r700->reg); \
75 pStateListWork->unOffset = mm##reg - ASIC_CONTEXT_BASE_INDEX; \
76 pStateListWork->pNext = pStateListWork + 1; \
77 pStateListWork++; \
78 }while(0)
79
80 GLboolean r700InitChipObject(context_t *context)
81 {
82 ContextState * pStateListWork;
83
84 R700_CHIP_CONTEXT *r700 = CALLOC( sizeof(R700_CHIP_CONTEXT) );
85
86 context->chipobj.pvChipObj = (void*)r700;
87
88 context->chipobj.DestroyChipObj = r700DestroyChipObj;
89
90 context->chipobj.GetTexObjSize = r700GetTexObjSize;
91
92 context->chipobj.stages = r700_pipeline;
93
94 context->chipobj.InitFuncs = r700InitFuncs;
95
96 context->chipobj.InitState = r700InitState;
97
98 /* init state list */
99 r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int));
100 pStateListWork = r700->pStateList;
101
102 LINK_STATES(DB_DEPTH_SIZE);
103 LINK_STATES(DB_DEPTH_VIEW);
104
105 LINK_STATES(DB_DEPTH_BASE);
106 LINK_STATES(DB_DEPTH_INFO);
107 LINK_STATES(DB_HTILE_DATA_BASE);
108
109 LINK_STATES(DB_STENCIL_CLEAR);
110 LINK_STATES(DB_DEPTH_CLEAR);
111
112 LINK_STATES(PA_SC_SCREEN_SCISSOR_TL);
113 LINK_STATES(PA_SC_SCREEN_SCISSOR_BR);
114
115 LINK_STATES(CB_COLOR0_BASE);
116
117 LINK_STATES(CB_COLOR0_SIZE);
118
119 LINK_STATES(CB_COLOR0_VIEW);
120
121 LINK_STATES(CB_COLOR0_INFO);
122 LINK_STATES(CB_COLOR1_INFO);
123 LINK_STATES(CB_COLOR2_INFO);
124 LINK_STATES(CB_COLOR3_INFO);
125 LINK_STATES(CB_COLOR4_INFO);
126 LINK_STATES(CB_COLOR5_INFO);
127 LINK_STATES(CB_COLOR6_INFO);
128 LINK_STATES(CB_COLOR7_INFO);
129
130 LINK_STATES(CB_COLOR0_TILE);
131
132 LINK_STATES(CB_COLOR0_FRAG);
133
134 LINK_STATES(CB_COLOR0_MASK);
135
136 LINK_STATES(PA_SC_WINDOW_OFFSET);
137 LINK_STATES(PA_SC_WINDOW_SCISSOR_TL);
138 LINK_STATES(PA_SC_WINDOW_SCISSOR_BR);
139 LINK_STATES(PA_SC_CLIPRECT_RULE);
140 LINK_STATES(PA_SC_CLIPRECT_0_TL);
141 LINK_STATES(PA_SC_CLIPRECT_0_BR);
142 LINK_STATES(PA_SC_CLIPRECT_1_TL);
143 LINK_STATES(PA_SC_CLIPRECT_1_BR);
144 LINK_STATES(PA_SC_CLIPRECT_2_TL);
145 LINK_STATES(PA_SC_CLIPRECT_2_BR);
146 LINK_STATES(PA_SC_CLIPRECT_3_TL);
147 LINK_STATES(PA_SC_CLIPRECT_3_BR);
148
149 LINK_STATES(PA_SC_EDGERULE);
150
151 LINK_STATES(CB_TARGET_MASK);
152 LINK_STATES(CB_SHADER_MASK);
153 LINK_STATES(PA_SC_GENERIC_SCISSOR_TL);
154 LINK_STATES(PA_SC_GENERIC_SCISSOR_BR);
155
156 LINK_STATES(PA_SC_VPORT_SCISSOR_0_TL);
157 LINK_STATES(PA_SC_VPORT_SCISSOR_0_BR);
158 LINK_STATES(PA_SC_VPORT_SCISSOR_1_TL);
159 LINK_STATES(PA_SC_VPORT_SCISSOR_1_BR);
160
161 LINK_STATES(PA_SC_VPORT_ZMIN_0);
162 LINK_STATES(PA_SC_VPORT_ZMAX_0);
163
164 LINK_STATES(SX_MISC);
165
166 LINK_STATES(SQ_VTX_SEMANTIC_0);
167 LINK_STATES(SQ_VTX_SEMANTIC_1);
168 LINK_STATES(SQ_VTX_SEMANTIC_2);
169 LINK_STATES(SQ_VTX_SEMANTIC_3);
170 LINK_STATES(SQ_VTX_SEMANTIC_4);
171 LINK_STATES(SQ_VTX_SEMANTIC_5);
172 LINK_STATES(SQ_VTX_SEMANTIC_6);
173 LINK_STATES(SQ_VTX_SEMANTIC_7);
174 LINK_STATES(SQ_VTX_SEMANTIC_8);
175 LINK_STATES(SQ_VTX_SEMANTIC_9);
176 LINK_STATES(SQ_VTX_SEMANTIC_10);
177 LINK_STATES(SQ_VTX_SEMANTIC_11);
178 LINK_STATES(SQ_VTX_SEMANTIC_12);
179 LINK_STATES(SQ_VTX_SEMANTIC_13);
180 LINK_STATES(SQ_VTX_SEMANTIC_14);
181 LINK_STATES(SQ_VTX_SEMANTIC_15);
182 LINK_STATES(SQ_VTX_SEMANTIC_16);
183 LINK_STATES(SQ_VTX_SEMANTIC_17);
184 LINK_STATES(SQ_VTX_SEMANTIC_18);
185 LINK_STATES(SQ_VTX_SEMANTIC_19);
186 LINK_STATES(SQ_VTX_SEMANTIC_20);
187 LINK_STATES(SQ_VTX_SEMANTIC_21);
188 LINK_STATES(SQ_VTX_SEMANTIC_22);
189 LINK_STATES(SQ_VTX_SEMANTIC_23);
190 LINK_STATES(SQ_VTX_SEMANTIC_24);
191 LINK_STATES(SQ_VTX_SEMANTIC_25);
192 LINK_STATES(SQ_VTX_SEMANTIC_26);
193 LINK_STATES(SQ_VTX_SEMANTIC_27);
194 LINK_STATES(SQ_VTX_SEMANTIC_28);
195 LINK_STATES(SQ_VTX_SEMANTIC_29);
196 LINK_STATES(SQ_VTX_SEMANTIC_30);
197 LINK_STATES(SQ_VTX_SEMANTIC_31);
198
199 LINK_STATES(VGT_MAX_VTX_INDX);
200 LINK_STATES(VGT_MIN_VTX_INDX);
201 LINK_STATES(VGT_INDX_OFFSET);
202 LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX);
203 LINK_STATES(SX_ALPHA_TEST_CONTROL);
204
205 LINK_STATES(CB_BLEND_RED);
206 LINK_STATES(CB_BLEND_GREEN);
207 LINK_STATES(CB_BLEND_BLUE);
208 LINK_STATES(CB_BLEND_ALPHA);
209
210 LINK_STATES(PA_CL_VPORT_XSCALE);
211 LINK_STATES(PA_CL_VPORT_XOFFSET);
212 LINK_STATES(PA_CL_VPORT_YSCALE);
213 LINK_STATES(PA_CL_VPORT_YOFFSET);
214 LINK_STATES(PA_CL_VPORT_ZSCALE);
215 LINK_STATES(PA_CL_VPORT_ZOFFSET);
216
217 LINK_STATES(SPI_VS_OUT_ID_0);
218 LINK_STATES(SPI_VS_OUT_ID_1);
219 LINK_STATES(SPI_VS_OUT_ID_2);
220 LINK_STATES(SPI_VS_OUT_ID_3);
221 LINK_STATES(SPI_VS_OUT_ID_4);
222 LINK_STATES(SPI_VS_OUT_ID_5);
223 LINK_STATES(SPI_VS_OUT_ID_6);
224 LINK_STATES(SPI_VS_OUT_ID_7);
225 LINK_STATES(SPI_VS_OUT_ID_8);
226 LINK_STATES(SPI_VS_OUT_ID_9);
227
228 LINK_STATES(SPI_PS_INPUT_CNTL_0);
229 LINK_STATES(SPI_PS_INPUT_CNTL_1);
230 LINK_STATES(SPI_PS_INPUT_CNTL_2);
231 LINK_STATES(SPI_PS_INPUT_CNTL_3);
232 LINK_STATES(SPI_PS_INPUT_CNTL_4);
233 LINK_STATES(SPI_PS_INPUT_CNTL_5);
234 LINK_STATES(SPI_PS_INPUT_CNTL_6);
235 LINK_STATES(SPI_PS_INPUT_CNTL_7);
236 LINK_STATES(SPI_PS_INPUT_CNTL_8);
237 LINK_STATES(SPI_PS_INPUT_CNTL_9);
238 LINK_STATES(SPI_PS_INPUT_CNTL_10);
239 LINK_STATES(SPI_PS_INPUT_CNTL_11);
240 LINK_STATES(SPI_PS_INPUT_CNTL_12);
241 LINK_STATES(SPI_PS_INPUT_CNTL_13);
242 LINK_STATES(SPI_PS_INPUT_CNTL_14);
243 LINK_STATES(SPI_PS_INPUT_CNTL_15);
244 LINK_STATES(SPI_PS_INPUT_CNTL_16);
245 LINK_STATES(SPI_PS_INPUT_CNTL_17);
246 LINK_STATES(SPI_PS_INPUT_CNTL_18);
247 LINK_STATES(SPI_PS_INPUT_CNTL_19);
248 LINK_STATES(SPI_PS_INPUT_CNTL_20);
249 LINK_STATES(SPI_PS_INPUT_CNTL_21);
250 LINK_STATES(SPI_PS_INPUT_CNTL_22);
251 LINK_STATES(SPI_PS_INPUT_CNTL_23);
252 LINK_STATES(SPI_PS_INPUT_CNTL_24);
253 LINK_STATES(SPI_PS_INPUT_CNTL_25);
254 LINK_STATES(SPI_PS_INPUT_CNTL_26);
255 LINK_STATES(SPI_PS_INPUT_CNTL_27);
256 LINK_STATES(SPI_PS_INPUT_CNTL_28);
257 LINK_STATES(SPI_PS_INPUT_CNTL_29);
258 LINK_STATES(SPI_PS_INPUT_CNTL_30);
259 LINK_STATES(SPI_PS_INPUT_CNTL_31);
260 LINK_STATES(SPI_VS_OUT_CONFIG);
261 LINK_STATES(SPI_THREAD_GROUPING);
262 LINK_STATES(SPI_PS_IN_CONTROL_0);
263 LINK_STATES(SPI_PS_IN_CONTROL_1);
264
265 LINK_STATES(SPI_INPUT_Z);
266 LINK_STATES(SPI_FOG_CNTL);
267
268 LINK_STATES(CB_BLEND0_CONTROL);
269
270 LINK_STATES(CB_SHADER_CONTROL);
271
272 /*LINK_STATES(VGT_DRAW_INITIATOR); */
273
274 LINK_STATES(DB_DEPTH_CONTROL);
275
276 LINK_STATES(CB_COLOR_CONTROL);
277 LINK_STATES(DB_SHADER_CONTROL);
278 LINK_STATES(PA_CL_CLIP_CNTL);
279 LINK_STATES(PA_SU_SC_MODE_CNTL);
280 LINK_STATES(PA_CL_VTE_CNTL);
281 LINK_STATES(PA_CL_VS_OUT_CNTL);
282 LINK_STATES(PA_CL_NANINF_CNTL);
283
284 LINK_STATES(SQ_PGM_START_PS);
285 LINK_STATES(SQ_PGM_RESOURCES_PS);
286 LINK_STATES(SQ_PGM_EXPORTS_PS);
287 LINK_STATES(SQ_PGM_START_VS);
288 LINK_STATES(SQ_PGM_RESOURCES_VS);
289 LINK_STATES(SQ_PGM_START_GS);
290 LINK_STATES(SQ_PGM_RESOURCES_GS);
291 LINK_STATES(SQ_PGM_START_ES);
292 LINK_STATES(SQ_PGM_RESOURCES_ES);
293 LINK_STATES(SQ_PGM_START_FS);
294 LINK_STATES(SQ_PGM_RESOURCES_FS);
295 LINK_STATES(SQ_ESGS_RING_ITEMSIZE);
296 LINK_STATES(SQ_GSVS_RING_ITEMSIZE);
297 LINK_STATES(SQ_ESTMP_RING_ITEMSIZE);
298 LINK_STATES(SQ_GSTMP_RING_ITEMSIZE);
299 LINK_STATES(SQ_VSTMP_RING_ITEMSIZE);
300 LINK_STATES(SQ_PSTMP_RING_ITEMSIZE);
301 LINK_STATES(SQ_FBUF_RING_ITEMSIZE);
302 LINK_STATES(SQ_REDUC_RING_ITEMSIZE);
303 LINK_STATES(SQ_GS_VERT_ITEMSIZE);
304 LINK_STATES(SQ_PGM_CF_OFFSET_PS);
305 LINK_STATES(SQ_PGM_CF_OFFSET_VS);
306 LINK_STATES(SQ_PGM_CF_OFFSET_GS);
307 LINK_STATES(SQ_PGM_CF_OFFSET_ES);
308 LINK_STATES(SQ_PGM_CF_OFFSET_FS);
309
310 LINK_STATES(PA_SU_POINT_SIZE);
311 LINK_STATES(PA_SU_POINT_MINMAX);
312 LINK_STATES(PA_SU_LINE_CNTL);
313 LINK_STATES(PA_SC_LINE_STIPPLE);
314 LINK_STATES(VGT_OUTPUT_PATH_CNTL);
315
316 LINK_STATES(VGT_GS_MODE);
317
318 LINK_STATES(PA_SC_MPASS_PS_CNTL);
319 LINK_STATES(PA_SC_MODE_CNTL);
320
321 LINK_STATES(VGT_PRIMITIVEID_EN);
322 LINK_STATES(VGT_DMA_NUM_INSTANCES);
323
324 LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN);
325
326 LINK_STATES(VGT_INSTANCE_STEP_RATE_0);
327 LINK_STATES(VGT_INSTANCE_STEP_RATE_1);
328
329 LINK_STATES(VGT_STRMOUT_EN);
330 LINK_STATES(VGT_REUSE_OFF);
331
332 LINK_STATES(PA_SC_LINE_CNTL);
333 LINK_STATES(PA_SC_AA_CONFIG);
334 LINK_STATES(PA_SU_VTX_CNTL);
335 LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ);
336 LINK_STATES(PA_CL_GB_VERT_DISC_ADJ);
337 LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ);
338 LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ);
339 LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX);
340 LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX);
341
342 LINK_STATES(CB_CLRCMP_CONTROL);
343 LINK_STATES(CB_CLRCMP_SRC);
344 LINK_STATES(CB_CLRCMP_DST);
345 LINK_STATES(CB_CLRCMP_MSK);
346
347 LINK_STATES(PA_SC_AA_MASK);
348
349 LINK_STATES(VGT_VERTEX_REUSE_BLOCK_CNTL);
350 LINK_STATES(VGT_OUT_DEALLOC_CNTL);
351
352 LINK_STATES(DB_RENDER_CONTROL);
353 LINK_STATES(DB_RENDER_OVERRIDE);
354
355 LINK_STATES(DB_HTILE_SURFACE);
356
357 LINK_STATES(DB_ALPHA_TO_MASK);
358
359 LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL);
360 LINK_STATES(PA_SU_POLY_OFFSET_CLAMP);
361 LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE);
362 LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET);
363 LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE);
364
365 pStateListWork->puiValue = (unsigned int*)&(r700->PA_SU_POLY_OFFSET_BACK_OFFSET);
366 pStateListWork->unOffset = mmPA_SU_POLY_OFFSET_BACK_OFFSET - ASIC_CONTEXT_BASE_INDEX;
367 pStateListWork->pNext = NULL; /* END OF STATE LIST */
368
369 /* TODO : may need order sorting in case someone break the order of states in R700_CHIP_CONTEXT. */
370
371 return GL_TRUE;
372 }
373
374 void r700SetupVTXConstants(GLcontext * ctx,
375 unsigned int nStreamID,
376 void * pAos,
377 unsigned int size, /* number of elements in vector */
378 unsigned int stride,
379 unsigned int count) /* number of vectors in stream */
380 {
381 context_t *context = R700_CONTEXT(ctx);
382 uint32_t *dest;
383 struct radeon_aos * paos = (struct radeon_aos *)pAos;
384 offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF};
385
386 BATCH_LOCALS(&context->radeon);
387
388 unsigned int uSQ_VTX_CONSTANT_WORD0_0;
389 unsigned int uSQ_VTX_CONSTANT_WORD1_0;
390 unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
391 unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
392 unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
393
394 uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
395 uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1;
396
397 uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */
398 |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift
399 |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */
400 |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift
401 |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit;
402
403 uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift;
404
405 uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift;
406
407 BEGIN_BATCH_NO_AUTOSTATE(9);
408
409 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
410 R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
411
412 R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
413 paos->bo,
414 uSQ_VTX_CONSTANT_WORD0_0,
415 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
416 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
417 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
418 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
419 R600_OUT_BATCH(0);
420 R600_OUT_BATCH(0);
421 R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
422
423 END_BATCH();
424 COMMIT_BATCH();
425
426 }
427
428 int r700SetupStreams(GLcontext * ctx)
429 {
430 context_t *context = R700_CONTEXT(ctx);
431
432 BATCH_LOCALS(&context->radeon);
433
434 struct r700_vertex_program *vpc
435 = (struct r700_vertex_program *)ctx->VertexProgram._Current;
436
437 TNLcontext *tnl = TNL_CONTEXT(ctx);
438 struct vertex_buffer *vb = &tnl->vb;
439
440 unsigned int unBit;
441 unsigned int i;
442
443 BEGIN_BATCH_NO_AUTOSTATE(6);
444 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
445 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
446 R600_OUT_BATCH(0);
447
448 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
449 R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
450 R600_OUT_BATCH(0);
451 END_BATCH();
452 COMMIT_BATCH();
453
454 //context->aos_count = 0;
455 for(i=0; i<VERT_ATTRIB_MAX; i++)
456 {
457 unBit = 1 << i;
458 if(vpc->mesa_program.Base.InputsRead & unBit)
459 {
460 rcommon_emit_vector(ctx,
461 &context->radeon.tcl.aos[i],
462 vb->AttribPtr[i]->data,
463 vb->AttribPtr[i]->size,
464 vb->AttribPtr[i]->stride,
465 vb->Count);
466
467 /* currently aos are packed */
468 r700SetupVTXConstants(ctx,
469 i,
470 (void*)(&context->radeon.tcl.aos[i]),
471 (unsigned int)vb->AttribPtr[i]->size,
472 (unsigned int)(vb->AttribPtr[i]->size * 4),
473 (unsigned int)vb->Count);
474 }
475 }
476
477 return R600_FALLBACK_NONE;
478 }
479
480 inline GLboolean needRelocReg(context_t *context, unsigned int reg)
481 {
482 switch (reg + ASIC_CONTEXT_BASE_INDEX)
483 {
484 case mmCB_COLOR0_BASE:
485 case mmCB_COLOR1_BASE:
486 case mmCB_COLOR2_BASE:
487 case mmCB_COLOR3_BASE:
488 case mmCB_COLOR4_BASE:
489 case mmCB_COLOR5_BASE:
490 case mmCB_COLOR6_BASE:
491 case mmCB_COLOR7_BASE:
492 case mmDB_DEPTH_BASE:
493 case mmSQ_PGM_START_VS:
494 case mmSQ_PGM_START_FS:
495 case mmSQ_PGM_START_ES:
496 case mmSQ_PGM_START_GS:
497 case mmSQ_PGM_START_PS:
498 return GL_TRUE;
499 break;
500 }
501
502 return GL_FALSE;
503 }
504
505 inline GLboolean setRelocReg(context_t *context, unsigned int reg)
506 {
507 BATCH_LOCALS(&context->radeon);
508 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
509
510 struct radeon_bo * pbo;
511 uint32_t voffset;
512 offset_modifiers offset_mod;
513
514 switch (reg + ASIC_CONTEXT_BASE_INDEX)
515 {
516 case mmCB_COLOR0_BASE:
517 case mmCB_COLOR1_BASE:
518 case mmCB_COLOR2_BASE:
519 case mmCB_COLOR3_BASE:
520 case mmCB_COLOR4_BASE:
521 case mmCB_COLOR5_BASE:
522 case mmCB_COLOR6_BASE:
523 case mmCB_COLOR7_BASE:
524 {
525 GLcontext *ctx = GL_CONTEXT(context);
526 struct radeon_renderbuffer *rrb;
527
528 rrb = radeon_get_colorbuffer(&context->radeon);
529 if (!rrb || !rrb->bo)
530 {
531 fprintf(stderr, "no rrb\n");
532 return GL_FALSE;
533 }
534
535 /* refer to radeonCreateScreen : screen->fbLocation = (temp & 0xffff) << 16; */
536 offset_mod.shift = NO_SHIFT;
537 offset_mod.shiftbits = 0;
538 offset_mod.mask = 0xFFFFFFFF;
539
540 R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All,
541 rrb->bo,
542 r700->CB_COLOR0_BASE.u32All,
543 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
544 return GL_TRUE;
545 }
546 break;
547 case mmDB_DEPTH_BASE:
548 {
549 GLcontext *ctx = GL_CONTEXT(context);
550 struct radeon_renderbuffer *rrb;
551 rrb = radeon_get_depthbuffer(&context->radeon);
552
553 offset_mod.shift = NO_SHIFT;
554 offset_mod.shiftbits = 0;
555 offset_mod.mask = 0xFFFFFFFF;
556
557 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
558 rrb->bo,
559 r700->DB_DEPTH_BASE.u32All,
560 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
561
562 return GL_TRUE;
563 }
564 break;
565 case mmSQ_PGM_START_VS:
566 {
567 pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
568
569 offset_mod.shift = NO_SHIFT;
570 offset_mod.shiftbits = 0;
571 offset_mod.mask = 0xFFFFFFFF;
572
573 R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All,
574 pbo,
575 r700->SQ_PGM_START_VS.u32All,
576 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
577 return GL_TRUE;
578 }
579 break;
580 case mmSQ_PGM_START_FS:
581 case mmSQ_PGM_START_ES:
582 case mmSQ_PGM_START_GS:
583 case mmSQ_PGM_START_PS:
584 {
585 pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
586
587 offset_mod.shift = NO_SHIFT;
588 offset_mod.shiftbits = 0;
589 offset_mod.mask = 0xFFFFFFFF;
590
591 voffset = 0;
592 R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All,
593 pbo,
594 r700->SQ_PGM_START_PS.u32All,
595 RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
596 return GL_TRUE;
597 }
598 break;
599 }
600
601 return GL_FALSE;
602 }
603
604 GLboolean r700SendContextStates(context_t *context)
605 {
606 BATCH_LOCALS(&context->radeon);
607
608 R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
609
610 ContextState * pState = r700->pStateList;
611 ContextState * pInit;
612 unsigned int toSend;
613 unsigned int ui;
614
615 while(NULL != pState)
616 {
617 toSend = 1;
618
619 pInit = pState;
620
621 if(GL_FALSE == needRelocReg(context, pState->unOffset))
622 {
623 while(NULL != pState->pNext)
624 {
625 if( ((pState->pNext->unOffset - pState->unOffset) > 1)
626 || (GL_TRUE == needRelocReg(context, pState->pNext->unOffset)) )
627 {
628 break;
629 }
630 else
631 {
632 pState = pState->pNext;
633 toSend++;
634 }
635 };
636 }
637
638 pState = pState->pNext;
639
640 BEGIN_BATCH_NO_AUTOSTATE(toSend + 2);
641 R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend);
642 for(ui=0; ui<toSend; ui++)
643 {
644 if( GL_FALSE == setRelocReg(context, pInit->unOffset) )
645 {
646 /* for not reloc reg. */
647 R600_OUT_BATCH(*(pInit->puiValue));
648 }
649 pInit = pInit->pNext;
650 };
651 END_BATCH();
652 };
653 COMMIT_BATCH();
654
655 return GL_TRUE;
656 }
657
658
659
660