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Merge branch 'glsl-to-tgsi'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.h
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #ifndef _R700_CHIP_H_
28 #define _R700_CHIP_H_
29
30 #include <GL/gl.h>
31
32 #include "radeon_common_context.h"
33
34 #include "r600_reg.h"
35 #include "r600_reg_auto_r6xx.h"
36 #include "r600_reg_r6xx.h"
37 #include "r600_reg_r7xx.h"
38
39 #include "r700_chipoffset.h"
40
41 #define SETfield(x, val, shift, mask) ( (x) = ((x) & ~(mask)) | (((val) << (shift)) & (mask)) )/* u32All */
42 #define CLEARfield(x, mask) ( (x) &= ~(mask) )
43 #define SETbit(x, bit) ( (x) |= (bit) )
44 #define CLEARbit(x, bit) ( (x) &= ~(bit) )
45
46 #define GETbits(x, shift, mask) ( ((x) & (mask)) >> (shift) )
47
48 #define R700_TEXTURE_NUMBERUNITS 16
49 #define R700_MAX_RENDER_TARGETS 8
50 #define R700_MAX_VIEWPORTS 16
51 #define R700_MAX_SHADER_EXPORTS 32
52 #define R700_MAX_UCP 6
53 #define R700_MAX_DX9_CONSTS 256
54
55 /* Enum not show in r600_*.h */
56
57 #define FETCH_RESOURCE_STRIDE 7
58
59 #define ASIC_CONFIG_BASE_INDEX 0x2000
60 #define ASIC_CONTEXT_BASE_INDEX 0xA000
61 #define ASIC_CTL_CONST_BASE_INDEX 0xF3FC
62
63
64 enum
65 {
66 SQ_ABSOLUTE = 0x00000000,
67 SQ_RELATIVE = 0x00000001,
68 };
69
70 enum
71 {
72 SQ_ALU_SCL_210 = 0x00000000,
73 SQ_ALU_SCL_122 = 0x00000001,
74 SQ_ALU_SCL_212 = 0x00000002,
75 SQ_ALU_SCL_221 = 0x00000003,
76 };
77
78 enum
79 {
80 SQ_TEX_UNNORMALIZED = 0x00000000,
81 SQ_TEX_NORMALIZED = 0x00000001,
82 };
83
84 enum
85 {
86 SQ_CF_PIXEL_MRT0 = 0x00000000,
87 SQ_CF_PIXEL_MRT1 = 0x00000001,
88 SQ_CF_PIXEL_MRT2 = 0x00000002,
89 SQ_CF_PIXEL_MRT3 = 0x00000003,
90 SQ_CF_PIXEL_MRT4 = 0x00000004,
91 SQ_CF_PIXEL_MRT5 = 0x00000005,
92 SQ_CF_PIXEL_MRT6 = 0x00000006,
93 SQ_CF_PIXEL_MRT7 = 0x00000007,
94 SQ_CF_PIXEL_Z = 0x0000003d,
95 };
96
97 typedef enum ENUM_SQ_CF_ARRAY_BASE_POS {
98 SQ_CF_POS_0 = 0x0000003c,
99 SQ_CF_POS_1 = 0x0000003d,
100 SQ_CF_POS_2 = 0x0000003e,
101 SQ_CF_POS_3 = 0x0000003f,
102 } ENUM_SQ_CF_ARRAY_BASE_POS;
103
104 enum
105 {
106 PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit = 23,
107 };
108
109 enum
110 {
111 TEX_XYFilter_Point = 0x00000000,
112 TEX_XYFilter_Linear = 0x00000001,
113 TEX_XYFilter_Cubic = 0x00000002,
114 TEX_XYFilter_Cleartype = 0x00000003,
115
116 TEX_MipFilter_None = 0x00000000,
117 TEX_MipFilter_Point = 0x00000001,
118 TEX_MipFilter_Linear = 0x00000002,
119 };
120
121 enum
122 {
123 SQ_EXPORT_WRITE = 0x00000000,
124 SQ_EXPORT_WRITE_IND = 0x00000001,
125 SQ_EXPORT_WRITE_ACK = 0x00000002,
126 SQ_EXPORT_WRITE_IND_ACK = 0x00000003,
127 };
128
129 /* --------------------------------- */
130
131 enum
132 {
133 R700_PM4_PACKET0_NOP = 0x00000000,
134 R700_PM4_PACKET1_NOP = 0x40000000,
135 R700_PM4_PACKET2_NOP = 0x80000000,
136 R700_PM4_PACKET3_NOP = 0xC0000000,
137 };
138
139 #define PM4_OPCODE_SET_INDEX_TYPE (R700_PM4_PACKET3_NOP | (IT_INDEX_TYPE << 8))
140
141 #define PM4_OPCODE_DRAW_INDEX_AUTO (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_AUTO << 8))
142 #define PM4_OPCODE_DRAW_INDEX_IMMD (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_IMMD << 8))
143 #define PM4_OPCODE_WAIT_REG_MEM (R700_PM4_PACKET3_NOP | (IT_WAIT_REG_MEM << 8))
144 #define PM4_OPCODE_SET_CONTEXT_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONTEXT_REG << 8))
145 #define PM4_OPCODE_SET_CONFIG_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONFIG_REG << 8))
146 #define PM4_OPCODE_SET_ALU_CONST (R700_PM4_PACKET3_NOP | (IT_SET_ALU_CONST << 8))
147 #define PM4_OPCODE_SET_RESOURCE (R700_PM4_PACKET3_NOP | (IT_SET_RESOURCE << 8))
148 #define PM4_OPCODE_SET_SAMPLER (R700_PM4_PACKET3_NOP | (IT_SET_SAMPLER << 8))
149 #define PM4_OPCODE_CONTEXT_CONTROL (R700_PM4_PACKET3_NOP | (IT_CONTEXT_CONTROL << 8))
150
151 union UINT_FLOAT
152 {
153 unsigned int u32All;
154 float f32All;
155 };
156
157 #if 0
158 typedef struct _TEXTURE_STATE_STRUCT
159 {
160 union UINT_FLOAT SQ_TEX_RESOURCE0;
161 union UINT_FLOAT SQ_TEX_RESOURCE1;
162 union UINT_FLOAT SQ_TEX_RESOURCE2;
163 union UINT_FLOAT SQ_TEX_RESOURCE3;
164 union UINT_FLOAT SQ_TEX_RESOURCE4;
165 union UINT_FLOAT SQ_TEX_RESOURCE5;
166 union UINT_FLOAT SQ_TEX_RESOURCE6;
167 GLboolean enabled;
168 } TEXTURE_STATE_STRUCT;
169
170 typedef struct _SAMPLER_STATE_STRUCT
171 {
172 union UINT_FLOAT SQ_TEX_SAMPLER0;
173 union UINT_FLOAT SQ_TEX_SAMPLER1;
174 union UINT_FLOAT SQ_TEX_SAMPLER2;
175 GLboolean enabled;
176 } SAMPLER_STATE_STRUCT;
177
178 typedef struct _R700_TEXTURE_STATES
179 {
180 TEXTURE_STATE_STRUCT *textures[R700_TEXTURE_NUMBERUNITS];
181 SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS];
182 } R700_TEXTURE_STATES;
183 #endif
184
185 typedef struct _RENDER_TARGET_STATE_STRUCT
186 {
187 union UINT_FLOAT CB_COLOR0_BASE; /* 0xA010 */
188 union UINT_FLOAT CB_COLOR0_SIZE; /* 0xA018 */
189 union UINT_FLOAT CB_COLOR0_VIEW; /* 0xA020 */
190 union UINT_FLOAT CB_COLOR0_INFO; /* 0xA028 */
191 union UINT_FLOAT CB_COLOR0_TILE; /* 0xA030 */
192 union UINT_FLOAT CB_COLOR0_FRAG; /* 0xA038 */
193 union UINT_FLOAT CB_COLOR0_MASK; /* 0xA040 */
194 union UINT_FLOAT CB_BLEND0_CONTROL; /* 0xA1E0 */
195 GLboolean enabled;
196 GLboolean dirty;
197 } RENDER_TARGET_STATE_STRUCT;
198
199 typedef struct _VIEWPORT_STATE_STRUCT
200 {
201 union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL; /* 0xA094 */
202 union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR; /* 0xA095 */
203 union UINT_FLOAT PA_SC_VPORT_ZMIN_0; /* 0xA0B4 */
204 union UINT_FLOAT PA_SC_VPORT_ZMAX_0; /* 0xA0B5 */
205 union UINT_FLOAT PA_CL_VPORT_XSCALE; /* 0xA10F */
206 union UINT_FLOAT PA_CL_VPORT_XOFFSET; /* 0xA110 */
207 union UINT_FLOAT PA_CL_VPORT_YSCALE; /* 0xA111 */
208 union UINT_FLOAT PA_CL_VPORT_YOFFSET; /* 0xA112 */
209 union UINT_FLOAT PA_CL_VPORT_ZSCALE; /* 0xA113 */
210 union UINT_FLOAT PA_CL_VPORT_ZOFFSET; /* 0xA114 */
211 GLboolean enabled;
212 GLboolean dirty;
213 } VIEWPORT_STATE_STRUCT;
214
215 typedef struct _UCP_STATE_STRUCT
216 {
217 union UINT_FLOAT PA_CL_UCP_0_X;
218 union UINT_FLOAT PA_CL_UCP_0_Y;
219 union UINT_FLOAT PA_CL_UCP_0_Z;
220 union UINT_FLOAT PA_CL_UCP_0_W;
221 GLboolean enabled;
222 GLboolean dirty;
223 } UCP_STATE_STRUCT;
224
225 typedef struct _PS_STATE_STRUCT
226 {
227 union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */
228 union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */
229 union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */
230 union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */
231 GLboolean dirty;
232 int num_consts;
233 union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4];
234 } PS_STATE_STRUCT;
235
236 typedef struct _VS_STATE_STRUCT
237 {
238 union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */
239 union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */
240 union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */
241 GLboolean dirty;
242 int num_consts;
243
244 union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_0;
245
246 union UINT_FLOAT consts[R700_MAX_DX9_CONSTS][4];
247 } VS_STATE_STRUCT;
248
249 typedef struct _GS_STATE_STRUCT
250 {
251 union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */
252 union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */
253 union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */
254 GLboolean dirty;
255 } GS_STATE_STRUCT;
256
257 typedef struct _ES_STATE_STRUCT
258 {
259 union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */
260 union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */
261 union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */
262 GLboolean dirty;
263 } ES_STATE_STRUCT;
264
265 typedef struct _FS_STATE_STRUCT
266 {
267 union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */
268 union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */
269 union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */
270 GLboolean dirty;
271 } FS_STATE_STRUCT;
272
273 typedef struct _SQ_CONFIG_STRUCT
274 {
275 union UINT_FLOAT SQ_CONFIG ; /* 0x2300 */
276 union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_1 ; /* 0x2301 */
277 union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_2 ; /* 0x2302 */
278 union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT ; /* 0x2303 */
279 union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_1 ; /* 0x2304 */
280 union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2 ; /* 0x2305 */
281 } SQ_CONFIG_STRUCT;
282
283 typedef struct _R700_CHIP_CONTEXT
284 {
285 // DB
286 union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */
287 union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */
288 union UINT_FLOAT DB_DEPTH_BASE ; /* 0xA003 */
289 union UINT_FLOAT DB_DEPTH_INFO ; /* 0xA004 */
290 GLboolean db_target_dirty;
291 union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */
292 union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */
293 union UINT_FLOAT DB_DEPTH_CLEAR ; /* 0xA00B */
294 union UINT_FLOAT DB_STENCILREFMASK ; /* 0xA10C */
295 union UINT_FLOAT DB_STENCILREFMASK_BF ; /* 0xA10D */
296 union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */
297 union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */
298 union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */
299 union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */
300 union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */
301 union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */
302 GLboolean db_dirty;
303
304 // SC
305 union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */
306 union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */
307 union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */
308 union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */
309 union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */
310 union UINT_FLOAT PA_SC_CLIPRECT_RULE ; /* 0xA083 */
311 union UINT_FLOAT PA_SC_CLIPRECT_0_TL ; /* 0xA084 */
312 union UINT_FLOAT PA_SC_CLIPRECT_0_BR ; /* 0xA085 */
313 union UINT_FLOAT PA_SC_CLIPRECT_1_TL ; /* 0xA086 */
314 union UINT_FLOAT PA_SC_CLIPRECT_1_BR ; /* 0xA087 */
315 union UINT_FLOAT PA_SC_CLIPRECT_2_TL ; /* 0xA088 */
316 union UINT_FLOAT PA_SC_CLIPRECT_2_BR ; /* 0xA089 */
317 union UINT_FLOAT PA_SC_CLIPRECT_3_TL ; /* 0xA08A */
318 union UINT_FLOAT PA_SC_CLIPRECT_3_BR ; /* 0xA08B */
319 union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */
320 union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */
321 union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */
322 GLboolean scissor_dirty;
323
324 union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */
325 union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */
326 union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */
327 union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */
328 union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */
329 union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */
330 union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */
331 union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */
332 GLboolean sc_dirty;
333
334 // CL
335 union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */
336 union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */
337 union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */
338 union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */
339 union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */
340 union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */
341 union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */
342 union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */
343 GLboolean cl_dirty;
344
345 // SU
346 union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */
347 union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */
348 union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */
349 union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */
350 union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */
351 union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */
352 union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */
353 union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */
354 union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */
355 union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */
356 union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */
357 GLboolean su_dirty;
358
359 VIEWPORT_STATE_STRUCT viewport[R700_MAX_VIEWPORTS];
360 UCP_STATE_STRUCT ucp[R700_MAX_UCP];
361
362 // CB
363 union UINT_FLOAT CB_CLEAR_RED_R6XX ; /* 0xA048 */
364 union UINT_FLOAT CB_CLEAR_GREEN_R6XX ; /* 0xA049 */
365 union UINT_FLOAT CB_CLEAR_BLUE_R6XX ; /* 0xA04A */
366 union UINT_FLOAT CB_CLEAR_ALPHA_R6XX ; /* 0xA04B */
367 union UINT_FLOAT CB_TARGET_MASK ; /* 0xA08E */
368 union UINT_FLOAT CB_SHADER_MASK ; /* 0xA08F */
369 union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */
370 union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */
371 union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */
372 union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */
373 union UINT_FLOAT CB_FOG_RED_R6XX ; /* 0xA109 */
374 union UINT_FLOAT CB_FOG_GREEN_R6XX ; /* 0xA10A */
375 union UINT_FLOAT CB_FOG_BLUE_R6XX ; /* 0xA10B */
376 union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */
377 union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */
378 union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */
379 union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */
380 union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */
381 union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */
382 union UINT_FLOAT CB_BLEND_CONTROL ; /* 0xABD0 */
383 GLboolean cb_dirty;
384 RENDER_TARGET_STATE_STRUCT render_target[R700_MAX_RENDER_TARGETS];
385
386 // SX
387 union UINT_FLOAT SX_MISC ; /* 0xA0D4 */
388 union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */
389 union UINT_FLOAT SX_ALPHA_REF ; /* 0xA10E */
390 GLboolean sx_dirty;
391
392 // VGT
393 union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */
394 union UINT_FLOAT VGT_MIN_VTX_INDX ; /* 0xA101 */
395 union UINT_FLOAT VGT_INDX_OFFSET ; /* 0xA102 */
396 union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */
397 union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */
398 union UINT_FLOAT VGT_HOS_CNTL ; /* 0xA285 */
399 union UINT_FLOAT VGT_HOS_MAX_TESS_LEVEL ; /* 0xA286 */
400 union UINT_FLOAT VGT_HOS_MIN_TESS_LEVEL ; /* 0xA287 */
401 union UINT_FLOAT VGT_HOS_REUSE_DEPTH ; /* 0xA288 */
402 union UINT_FLOAT VGT_GROUP_PRIM_TYPE ; /* 0xA289 */
403 union UINT_FLOAT VGT_GROUP_FIRST_DECR ; /* 0xA28A */
404 union UINT_FLOAT VGT_GROUP_DECR ; /* 0xA28B */
405 union UINT_FLOAT VGT_GROUP_VECT_0_CNTL ; /* 0xA28C */
406 union UINT_FLOAT VGT_GROUP_VECT_1_CNTL ; /* 0xA28D */
407 union UINT_FLOAT VGT_GROUP_VECT_0_FMT_CNTL ; /* 0xA28E */
408 union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL ; /* 0xA28F */
409 union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */
410 union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */
411 union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */
412 union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */
413 union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */
414 union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */
415 union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */
416 union UINT_FLOAT VGT_VTX_CNT_EN ; /* 0xA2AE */
417 union UINT_FLOAT VGT_STRMOUT_BUFFER_EN ; /* 0xA2C8 */
418 GLboolean vgt_dirty;
419
420 // SPI
421 union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */
422 union UINT_FLOAT SPI_VS_OUT_ID_1 ; /* 0xA186 */
423 union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */
424 union UINT_FLOAT SPI_VS_OUT_ID_3 ; /* 0xA188 */
425 union UINT_FLOAT SPI_VS_OUT_ID_4 ; /* 0xA189 */
426 union UINT_FLOAT SPI_VS_OUT_ID_5 ; /* 0xA18A */
427 union UINT_FLOAT SPI_VS_OUT_ID_6 ; /* 0xA18B */
428 union UINT_FLOAT SPI_VS_OUT_ID_7 ; /* 0xA18C */
429 union UINT_FLOAT SPI_VS_OUT_ID_8 ; /* 0xA18D */
430 union UINT_FLOAT SPI_VS_OUT_ID_9 ; /* 0xA18E */
431 union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */
432 union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */
433 union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */
434 union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */
435 union UINT_FLOAT SPI_INTERP_CONTROL_0 ; /* 0xA1B5 */
436 union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */
437 union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */
438 union UINT_FLOAT SPI_FOG_FUNC_SCALE ; /* 0xA1B8 */
439 union UINT_FLOAT SPI_FOG_FUNC_BIAS ; /* 0xA1B9 */
440
441 union UINT_FLOAT SQ_VTX_SEMANTIC_0 ; /* 0xA0E0 */
442 union UINT_FLOAT SQ_VTX_SEMANTIC_1 ; /* 0xA0E1 */
443 union UINT_FLOAT SQ_VTX_SEMANTIC_2 ; /* 0xA0E2 */
444 union UINT_FLOAT SQ_VTX_SEMANTIC_3 ; /* 0xA0E3 */
445 union UINT_FLOAT SQ_VTX_SEMANTIC_4 ; /* 0xA0E4 */
446 union UINT_FLOAT SQ_VTX_SEMANTIC_5 ; /* 0xA0E5 */
447 union UINT_FLOAT SQ_VTX_SEMANTIC_6 ; /* 0xA0E6 */
448 union UINT_FLOAT SQ_VTX_SEMANTIC_7 ; /* 0xA0E7 */
449 union UINT_FLOAT SQ_VTX_SEMANTIC_8 ; /* 0xA0E8 */
450 union UINT_FLOAT SQ_VTX_SEMANTIC_9 ; /* 0xA0E9 */
451 union UINT_FLOAT SQ_VTX_SEMANTIC_10 ; /* 0xA0EA */
452 union UINT_FLOAT SQ_VTX_SEMANTIC_11 ; /* 0xA0EB */
453 union UINT_FLOAT SQ_VTX_SEMANTIC_12 ; /* 0xA0EC */
454 union UINT_FLOAT SQ_VTX_SEMANTIC_13 ; /* 0xA0ED */
455 union UINT_FLOAT SQ_VTX_SEMANTIC_14 ; /* 0xA0EE */
456 union UINT_FLOAT SQ_VTX_SEMANTIC_15 ; /* 0xA0EF */
457 union UINT_FLOAT SQ_VTX_SEMANTIC_16 ; /* 0xA0F0 */
458 union UINT_FLOAT SQ_VTX_SEMANTIC_17 ; /* 0xA0F1 */
459 union UINT_FLOAT SQ_VTX_SEMANTIC_18 ; /* 0xA0F2 */
460 union UINT_FLOAT SQ_VTX_SEMANTIC_19 ; /* 0xA0F3 */
461 union UINT_FLOAT SQ_VTX_SEMANTIC_20 ; /* 0xA0F4 */
462 union UINT_FLOAT SQ_VTX_SEMANTIC_21 ; /* 0xA0F5 */
463 union UINT_FLOAT SQ_VTX_SEMANTIC_22 ; /* 0xA0F6 */
464 union UINT_FLOAT SQ_VTX_SEMANTIC_23 ; /* 0xA0F7 */
465 union UINT_FLOAT SQ_VTX_SEMANTIC_24 ; /* 0xA0F8 */
466 union UINT_FLOAT SQ_VTX_SEMANTIC_25 ; /* 0xA0F9 */
467 union UINT_FLOAT SQ_VTX_SEMANTIC_26 ; /* 0xA0FA */
468 union UINT_FLOAT SQ_VTX_SEMANTIC_27 ; /* 0xA0FB */
469 union UINT_FLOAT SQ_VTX_SEMANTIC_28 ; /* 0xA0FC */
470 union UINT_FLOAT SQ_VTX_SEMANTIC_29 ; /* 0xA0FD */
471 union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */
472 union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */
473 union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
474 GLboolean spi_dirty;
475
476 // shaders
477 PS_STATE_STRUCT ps;
478 VS_STATE_STRUCT vs;
479 GS_STATE_STRUCT gs;
480 ES_STATE_STRUCT es;
481 FS_STATE_STRUCT fs;
482
483 // SQ CONFIG
484 SQ_CONFIG_STRUCT sq_config;
485 // misc
486 union UINT_FLOAT TA_CNTL_AUX ; /* 0x2542 */
487 union UINT_FLOAT VC_ENHANCE ; /* 0x25C5 */
488 union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; /* 0x2363 */
489 union UINT_FLOAT DB_DEBUG ; /* 0x260C */
490 union UINT_FLOAT DB_WATERMARKS ; /* 0x260E */
491 // SQ
492 union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */
493 union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */
494 union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */
495 union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */
496 union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */
497 union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */
498 union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */
499 union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */
500 union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */
501 GLboolean sq_dirty;
502
503 radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS];
504
505 GLboolean bEnablePerspective;
506
507 GLboolean bShaderUseMemConstant;
508
509 } R700_CHIP_CONTEXT;
510
511 #endif /* _R700_CHIP_H_ */
512