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f08190027c430a98284d7bed5c67fb1befb59998
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.h
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #ifndef _R700_CHIP_H_
28 #define _R700_CHIP_H_
29
30 #include "r600_context.h"
31
32 #include "r600_reg.h"
33 #include "r600_reg_auto_r6xx.h"
34 #include "r600_reg_r6xx.h"
35 #include "r600_reg_r7xx.h"
36
37 #include "r700_chipoffset.h"
38
39 #define SETfield(x, val, shift, mask) ( (x) = ((x) & ~(mask)) | ((val) << (shift)) ) /* u32All */
40 #define CLEARfield(x, mask) ( (x) &= ~(mask) )
41 #define SETbit(x, bit) ( (x) |= (bit) )
42 #define CLEARbit(x, bit) ( (x) &= ~(bit) )
43
44 #define R700_TEXTURE_NUMBERUNITS 16
45
46 /* Enum not show in r600_*.h */
47
48 #define FETCH_RESOURCE_STRIDE 7
49
50 #define ASIC_CONFIG_BASE_INDEX 0x2000
51 #define ASIC_CONTEXT_BASE_INDEX 0xA000
52 #define ASIC_CTL_CONST_BASE_INDEX 0xF3FC
53
54 enum
55 {
56 SQ_ABSOLUTE = 0x00000000,
57 SQ_RELATIVE = 0x00000001,
58 };
59
60 enum
61 {
62 SQ_ALU_SCL_210 = 0x00000000,
63 SQ_ALU_SCL_122 = 0x00000001,
64 SQ_ALU_SCL_212 = 0x00000002,
65 SQ_ALU_SCL_221 = 0x00000003,
66 };
67
68 enum
69 {
70 SQ_TEX_UNNORMALIZED = 0x00000000,
71 SQ_TEX_NORMALIZED = 0x00000001,
72 };
73
74 enum
75 {
76 SQ_CF_PIXEL_MRT0 = 0x00000000,
77 SQ_CF_PIXEL_MRT1 = 0x00000001,
78 SQ_CF_PIXEL_MRT2 = 0x00000002,
79 SQ_CF_PIXEL_MRT3 = 0x00000003,
80 SQ_CF_PIXEL_MRT4 = 0x00000004,
81 SQ_CF_PIXEL_MRT5 = 0x00000005,
82 SQ_CF_PIXEL_MRT6 = 0x00000006,
83 SQ_CF_PIXEL_MRT7 = 0x00000007,
84 SQ_CF_PIXEL_Z = 0x0000003d,
85 };
86
87 typedef enum ENUM_SQ_CF_ARRAY_BASE_POS {
88 SQ_CF_POS_0 = 0x0000003c,
89 SQ_CF_POS_1 = 0x0000003d,
90 SQ_CF_POS_2 = 0x0000003e,
91 SQ_CF_POS_3 = 0x0000003f,
92 } ENUM_SQ_CF_ARRAY_BASE_POS;
93
94 enum
95 {
96 PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit = 23,
97 };
98
99 enum
100 {
101 TEX_XYFilter_Point = 0x00000000,
102 TEX_XYFilter_Linear = 0x00000001,
103 TEX_XYFilter_Cubic = 0x00000002,
104 TEX_XYFilter_Cleartype = 0x00000003,
105
106 TEX_MipFilter_None = 0x00000000,
107 TEX_MipFilter_Point = 0x00000001,
108 TEX_MipFilter_Linear = 0x00000002,
109 };
110
111 enum
112 {
113 SQ_EXPORT_WRITE = 0x00000000,
114 SQ_EXPORT_WRITE_IND = 0x00000001,
115 SQ_EXPORT_WRITE_ACK = 0x00000002,
116 SQ_EXPORT_WRITE_IND_ACK = 0x00000003,
117 };
118
119 /* --------------------------------- */
120
121 enum
122 {
123 R700_PM4_PACKET0_NOP = 0x00000000,
124 R700_PM4_PACKET1_NOP = 0x40000000,
125 R700_PM4_PACKET2_NOP = 0x80000000,
126 R700_PM4_PACKET3_NOP = 0xC0000000,
127 };
128
129 #define PM4_OPCODE_SET_INDEX_TYPE (R700_PM4_PACKET3_NOP | (IT_INDEX_TYPE << 8))
130
131 #define PM4_OPCODE_DRAW_INDEX_AUTO (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_AUTO << 8))
132 #define PM4_OPCODE_DRAW_INDEX_IMMD (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_IMMD << 8))
133 #define PM4_OPCODE_WAIT_REG_MEM (R700_PM4_PACKET3_NOP | (IT_WAIT_REG_MEM << 8))
134 #define PM4_OPCODE_SET_CONTEXT_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONTEXT_REG << 8))
135 #define PM4_OPCODE_SET_CONFIG_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONFIG_REG << 8))
136 #define PM4_OPCODE_SET_ALU_CONST (R700_PM4_PACKET3_NOP | (IT_SET_ALU_CONST << 8))
137 #define PM4_OPCODE_SET_RESOURCE (R700_PM4_PACKET3_NOP | (IT_SET_RESOURCE << 8))
138 #define PM4_OPCODE_SET_SAMPLER (R700_PM4_PACKET3_NOP | (IT_SET_SAMPLER << 8))
139 #define PM4_OPCODE_CONTEXT_CONTROL (R700_PM4_PACKET3_NOP | (IT_CONTEXT_CONTROL << 8))
140
141 union UINT_FLOAT
142 {
143 unsigned int u32All;
144 float f32All;
145 };
146
147 typedef struct _TEXTURE_STATE_STRUCT
148 {
149 union UINT_FLOAT SQ_TEX_RESOURCE0;
150 union UINT_FLOAT SQ_TEX_RESOURCE1;
151 union UINT_FLOAT SQ_TEX_RESOURCE2;
152 union UINT_FLOAT SQ_TEX_RESOURCE3;
153 union UINT_FLOAT SQ_TEX_RESOURCE4;
154 union UINT_FLOAT SQ_TEX_RESOURCE5;
155 union UINT_FLOAT SQ_TEX_RESOURCE6;
156 GLboolean enabled;
157 } TEXTURE_STATE_STRUCT;
158
159 typedef struct _SAMPLER_STATE_STRUCT
160 {
161 union UINT_FLOAT SQ_TEX_SAMPLER0;
162 union UINT_FLOAT SQ_TEX_SAMPLER1;
163 union UINT_FLOAT SQ_TEX_SAMPLER2;
164 GLboolean enabled;
165 } SAMPLER_STATE_STRUCT;
166
167 typedef struct _R700_TEXTURE_STATES
168 {
169 TEXTURE_STATE_STRUCT *textures[R700_TEXTURE_NUMBERUNITS];
170 SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS];
171 } R700_TEXTURE_STATES;
172
173 typedef struct ContextState
174 {
175 unsigned int * puiValue;
176 unsigned int unOffset;
177 struct ContextState * pNext;
178 } ContextState;
179
180 typedef struct _R700_CHIP_CONTEXT
181 {
182 union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */
183 union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */
184
185 union UINT_FLOAT DB_DEPTH_BASE ; /* 0xA003 */
186 union UINT_FLOAT DB_DEPTH_INFO ; /* 0xA004 */
187 union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */
188
189 union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */
190 union UINT_FLOAT DB_DEPTH_CLEAR ; /* 0xA00B */
191
192 union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */
193 union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */
194
195 union UINT_FLOAT CB_COLOR0_BASE ; /* 0xA010 */
196
197 union UINT_FLOAT CB_COLOR0_SIZE ; /* 0xA018 */
198
199 union UINT_FLOAT CB_COLOR0_VIEW ; /* 0xA020 */
200
201 union UINT_FLOAT CB_COLOR0_INFO ; /* 0xA028 */
202 union UINT_FLOAT CB_COLOR1_INFO ; /* 0xA029 */
203 union UINT_FLOAT CB_COLOR2_INFO ; /* 0xA02A */
204 union UINT_FLOAT CB_COLOR3_INFO ; /* 0xA02B */
205 union UINT_FLOAT CB_COLOR4_INFO ; /* 0xA02C */
206 union UINT_FLOAT CB_COLOR5_INFO ; /* 0xA02D */
207 union UINT_FLOAT CB_COLOR6_INFO ; /* 0xA02E */
208 union UINT_FLOAT CB_COLOR7_INFO ; /* 0xA02F */
209
210 union UINT_FLOAT CB_COLOR0_TILE ; /* 0xA030 */
211
212 union UINT_FLOAT CB_COLOR0_FRAG ; /* 0xA038 */
213
214 union UINT_FLOAT CB_COLOR0_MASK ; /* 0xA040 */
215
216 union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */
217 union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */
218 union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */
219 union UINT_FLOAT PA_SC_CLIPRECT_RULE ; /* 0xA083 */
220 union UINT_FLOAT PA_SC_CLIPRECT_0_TL ; /* 0xA084 */
221 union UINT_FLOAT PA_SC_CLIPRECT_0_BR ; /* 0xA085 */
222 union UINT_FLOAT PA_SC_CLIPRECT_1_TL ; /* 0xA086 */
223 union UINT_FLOAT PA_SC_CLIPRECT_1_BR ; /* 0xA087 */
224 union UINT_FLOAT PA_SC_CLIPRECT_2_TL ; /* 0xA088 */
225 union UINT_FLOAT PA_SC_CLIPRECT_2_BR ; /* 0xA089 */
226 union UINT_FLOAT PA_SC_CLIPRECT_3_TL ; /* 0xA08A */
227 union UINT_FLOAT PA_SC_CLIPRECT_3_BR ; /* 0xA08B */
228
229 union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */
230
231 union UINT_FLOAT CB_TARGET_MASK ; /* 0xA08E */
232 union UINT_FLOAT CB_SHADER_MASK ; /* 0xA08F */
233 union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */
234 union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */
235
236 union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL ; /* 0xA094 */
237 union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR ; /* 0xA095 */
238 union UINT_FLOAT PA_SC_VPORT_SCISSOR_1_TL ; /* 0xA096 */
239 union UINT_FLOAT PA_SC_VPORT_SCISSOR_1_BR ; /* 0xA097 */
240
241 union UINT_FLOAT PA_SC_VPORT_ZMIN_0 ; /* 0xA0B4 */
242 union UINT_FLOAT PA_SC_VPORT_ZMAX_0 ; /* 0xA0B5 */
243
244 union UINT_FLOAT SX_MISC ; /* 0xA0D4 */
245
246 union UINT_FLOAT SQ_VTX_SEMANTIC_0 ; /* 0xA0E0 */
247 union UINT_FLOAT SQ_VTX_SEMANTIC_1 ; /* 0xA0E1 */
248 union UINT_FLOAT SQ_VTX_SEMANTIC_2 ; /* 0xA0E2 */
249 union UINT_FLOAT SQ_VTX_SEMANTIC_3 ; /* 0xA0E3 */
250 union UINT_FLOAT SQ_VTX_SEMANTIC_4 ; /* 0xA0E4 */
251 union UINT_FLOAT SQ_VTX_SEMANTIC_5 ; /* 0xA0E5 */
252 union UINT_FLOAT SQ_VTX_SEMANTIC_6 ; /* 0xA0E6 */
253 union UINT_FLOAT SQ_VTX_SEMANTIC_7 ; /* 0xA0E7 */
254 union UINT_FLOAT SQ_VTX_SEMANTIC_8 ; /* 0xA0E8 */
255 union UINT_FLOAT SQ_VTX_SEMANTIC_9 ; /* 0xA0E9 */
256 union UINT_FLOAT SQ_VTX_SEMANTIC_10 ; /* 0xA0EA */
257 union UINT_FLOAT SQ_VTX_SEMANTIC_11 ; /* 0xA0EB */
258 union UINT_FLOAT SQ_VTX_SEMANTIC_12 ; /* 0xA0EC */
259 union UINT_FLOAT SQ_VTX_SEMANTIC_13 ; /* 0xA0ED */
260 union UINT_FLOAT SQ_VTX_SEMANTIC_14 ; /* 0xA0EE */
261 union UINT_FLOAT SQ_VTX_SEMANTIC_15 ; /* 0xA0EF */
262 union UINT_FLOAT SQ_VTX_SEMANTIC_16 ; /* 0xA0F0 */
263 union UINT_FLOAT SQ_VTX_SEMANTIC_17 ; /* 0xA0F1 */
264 union UINT_FLOAT SQ_VTX_SEMANTIC_18 ; /* 0xA0F2 */
265 union UINT_FLOAT SQ_VTX_SEMANTIC_19 ; /* 0xA0F3 */
266 union UINT_FLOAT SQ_VTX_SEMANTIC_20 ; /* 0xA0F4 */
267 union UINT_FLOAT SQ_VTX_SEMANTIC_21 ; /* 0xA0F5 */
268 union UINT_FLOAT SQ_VTX_SEMANTIC_22 ; /* 0xA0F6 */
269 union UINT_FLOAT SQ_VTX_SEMANTIC_23 ; /* 0xA0F7 */
270 union UINT_FLOAT SQ_VTX_SEMANTIC_24 ; /* 0xA0F8 */
271 union UINT_FLOAT SQ_VTX_SEMANTIC_25 ; /* 0xA0F9 */
272 union UINT_FLOAT SQ_VTX_SEMANTIC_26 ; /* 0xA0FA */
273 union UINT_FLOAT SQ_VTX_SEMANTIC_27 ; /* 0xA0FB */
274 union UINT_FLOAT SQ_VTX_SEMANTIC_28 ; /* 0xA0FC */
275 union UINT_FLOAT SQ_VTX_SEMANTIC_29 ; /* 0xA0FD */
276 union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */
277 union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */
278
279 union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */
280 union UINT_FLOAT VGT_MIN_VTX_INDX ; /* 0xA101 */
281 union UINT_FLOAT VGT_INDX_OFFSET ; /* 0xA102 */
282 union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */
283 union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */
284
285 union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */
286 union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */
287 union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */
288 union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */
289
290 union UINT_FLOAT PA_CL_VPORT_XSCALE ; /* 0xA10F */
291 union UINT_FLOAT PA_CL_VPORT_XOFFSET ; /* 0xA110 */
292 union UINT_FLOAT PA_CL_VPORT_YSCALE ; /* 0xA111 */
293 union UINT_FLOAT PA_CL_VPORT_YOFFSET ; /* 0xA112 */
294 union UINT_FLOAT PA_CL_VPORT_ZSCALE ; /* 0xA113 */
295 union UINT_FLOAT PA_CL_VPORT_ZOFFSET ; /* 0xA114 */
296
297 union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */
298 union UINT_FLOAT SPI_VS_OUT_ID_1 ; /* 0xA186 */
299 union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */
300 union UINT_FLOAT SPI_VS_OUT_ID_3 ; /* 0xA188 */
301 union UINT_FLOAT SPI_VS_OUT_ID_4 ; /* 0xA189 */
302 union UINT_FLOAT SPI_VS_OUT_ID_5 ; /* 0xA18A */
303 union UINT_FLOAT SPI_VS_OUT_ID_6 ; /* 0xA18B */
304 union UINT_FLOAT SPI_VS_OUT_ID_7 ; /* 0xA18C */
305 union UINT_FLOAT SPI_VS_OUT_ID_8 ; /* 0xA18D */
306 union UINT_FLOAT SPI_VS_OUT_ID_9 ; /* 0xA18E */
307
308 union UINT_FLOAT SPI_PS_INPUT_CNTL_0 ; /* 0xA191 */
309 union UINT_FLOAT SPI_PS_INPUT_CNTL_1 ; /* 0xA192 */
310 union UINT_FLOAT SPI_PS_INPUT_CNTL_2 ; /* 0xA193 */
311 union UINT_FLOAT SPI_PS_INPUT_CNTL_3 ; /* 0xA194 */
312 union UINT_FLOAT SPI_PS_INPUT_CNTL_4 ; /* 0xA195 */
313 union UINT_FLOAT SPI_PS_INPUT_CNTL_5 ; /* 0xA196 */
314 union UINT_FLOAT SPI_PS_INPUT_CNTL_6 ; /* 0xA197 */
315 union UINT_FLOAT SPI_PS_INPUT_CNTL_7 ; /* 0xA198 */
316 union UINT_FLOAT SPI_PS_INPUT_CNTL_8 ; /* 0xA199 */
317 union UINT_FLOAT SPI_PS_INPUT_CNTL_9 ; /* 0xA19A */
318 union UINT_FLOAT SPI_PS_INPUT_CNTL_10 ; /* 0xA19B */
319 union UINT_FLOAT SPI_PS_INPUT_CNTL_11 ; /* 0xA19C */
320 union UINT_FLOAT SPI_PS_INPUT_CNTL_12 ; /* 0xA19D */
321 union UINT_FLOAT SPI_PS_INPUT_CNTL_13 ; /* 0xA19E */
322 union UINT_FLOAT SPI_PS_INPUT_CNTL_14 ; /* 0xA19F */
323 union UINT_FLOAT SPI_PS_INPUT_CNTL_15 ; /* 0xA1A0 */
324 union UINT_FLOAT SPI_PS_INPUT_CNTL_16 ; /* 0xA1A1 */
325 union UINT_FLOAT SPI_PS_INPUT_CNTL_17 ; /* 0xA1A2 */
326 union UINT_FLOAT SPI_PS_INPUT_CNTL_18 ; /* 0xA1A3 */
327 union UINT_FLOAT SPI_PS_INPUT_CNTL_19 ; /* 0xA1A4 */
328 union UINT_FLOAT SPI_PS_INPUT_CNTL_20 ; /* 0xA1A5 */
329 union UINT_FLOAT SPI_PS_INPUT_CNTL_21 ; /* 0xA1A6 */
330 union UINT_FLOAT SPI_PS_INPUT_CNTL_22 ; /* 0xA1A7 */
331 union UINT_FLOAT SPI_PS_INPUT_CNTL_23 ; /* 0xA1A8 */
332 union UINT_FLOAT SPI_PS_INPUT_CNTL_24 ; /* 0xA1A9 */
333 union UINT_FLOAT SPI_PS_INPUT_CNTL_25 ; /* 0xA1AA */
334 union UINT_FLOAT SPI_PS_INPUT_CNTL_26 ; /* 0xA1AB */
335 union UINT_FLOAT SPI_PS_INPUT_CNTL_27 ; /* 0xA1AC */
336 union UINT_FLOAT SPI_PS_INPUT_CNTL_28 ; /* 0xA1AD */
337 union UINT_FLOAT SPI_PS_INPUT_CNTL_29 ; /* 0xA1AE */
338 union UINT_FLOAT SPI_PS_INPUT_CNTL_30 ; /* 0xA1AF */
339 union UINT_FLOAT SPI_PS_INPUT_CNTL_31 ; /* 0xA1B0 */
340 union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */
341 union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */
342 union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */
343 union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */
344
345 union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */
346 union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */
347
348 union UINT_FLOAT CB_BLEND0_CONTROL ; /* 0xA1E0 */
349
350 union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */
351
352 /*union UINT_FLOAT VGT_DRAW_INITIATOR*/ ; /* 0xA1FC */
353
354 union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */
355
356 union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */
357 union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */
358 union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */
359 union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */
360 union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */
361 union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */
362 union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */
363
364 union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */
365 union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */
366 union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */
367 union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */
368 union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */
369 union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */
370 union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */
371 union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */
372 union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */
373 union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */
374 union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */
375 union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */
376 union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */
377 union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */
378 union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */
379 union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */
380 union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */
381 union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */
382 union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */
383 union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */
384 union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */
385 union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */
386 union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */
387 union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */
388 union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */
389
390 union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */
391 union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */
392 union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */
393 union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */
394 union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */
395
396 union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */
397
398 union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */
399 union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */
400
401 union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */
402 union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */
403
404 union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */
405
406 union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */
407 union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */
408
409 union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */
410 union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */
411
412 union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */
413 union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */
414 union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */
415 union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */
416 union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */
417 union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */
418 union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */
419 union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */
420 union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */
421
422 union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */
423 union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */
424 union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */
425 union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */
426
427 union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */
428
429 union UINT_FLOAT VGT_VERTEX_REUSE_BLOCK_CNTL; /* 0xA316 */
430 union UINT_FLOAT VGT_OUT_DEALLOC_CNTL ; /* 0xA317 */
431
432 union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */
433 union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */
434
435 union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */
436
437 union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */
438
439 union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */
440 union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */
441 union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */
442 union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */
443 union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */
444 union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */
445
446 ContextState * pStateList;
447
448 R700_TEXTURE_STATES texture_states;
449
450 } R700_CHIP_CONTEXT;
451
452 #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj))
453
454 extern GLboolean r700InitChipObject(context_t *context);
455 extern GLboolean r700SendContextStates(context_t *context);
456
457 #endif /* _R700_CHIP_H_ */
458