2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
30 #include "r600_context.h"
33 #include "r600_reg_auto_r6xx.h"
34 #include "r600_reg_r6xx.h"
35 #include "r600_reg_r7xx.h"
37 #include "r700_chipoffset.h"
39 #define SETfield(x, val, shift, mask) ( (x) = ((x) & ~(mask)) | ((val) << (shift)) ) /* u32All */
40 #define CLEARfield(x, mask) ( (x) &= ~(mask) )
41 #define SETbit(x, bit) ( (x) |= (bit) )
42 #define CLEARbit(x, bit) ( (x) &= ~(bit) )
44 #define R700_TEXTURE_NUMBERUNITS 16
45 #define R700_MAX_RENDER_TARGETS 8
46 #define R700_MAX_VIEWPORTS 16
47 #define R700_MAX_SHADER_EXPORTS 32
48 #define R700_MAX_UCP 6
49 #define R700_MAX_DX9_CONSTS 256
51 /* Enum not show in r600_*.h */
53 #define FETCH_RESOURCE_STRIDE 7
55 #define ASIC_CONFIG_BASE_INDEX 0x2000
56 #define ASIC_CONTEXT_BASE_INDEX 0xA000
57 #define ASIC_CTL_CONST_BASE_INDEX 0xF3FC
62 SQ_ABSOLUTE
= 0x00000000,
63 SQ_RELATIVE
= 0x00000001,
68 SQ_ALU_SCL_210
= 0x00000000,
69 SQ_ALU_SCL_122
= 0x00000001,
70 SQ_ALU_SCL_212
= 0x00000002,
71 SQ_ALU_SCL_221
= 0x00000003,
76 SQ_TEX_UNNORMALIZED
= 0x00000000,
77 SQ_TEX_NORMALIZED
= 0x00000001,
82 SQ_CF_PIXEL_MRT0
= 0x00000000,
83 SQ_CF_PIXEL_MRT1
= 0x00000001,
84 SQ_CF_PIXEL_MRT2
= 0x00000002,
85 SQ_CF_PIXEL_MRT3
= 0x00000003,
86 SQ_CF_PIXEL_MRT4
= 0x00000004,
87 SQ_CF_PIXEL_MRT5
= 0x00000005,
88 SQ_CF_PIXEL_MRT6
= 0x00000006,
89 SQ_CF_PIXEL_MRT7
= 0x00000007,
90 SQ_CF_PIXEL_Z
= 0x0000003d,
93 typedef enum ENUM_SQ_CF_ARRAY_BASE_POS
{
94 SQ_CF_POS_0
= 0x0000003c,
95 SQ_CF_POS_1
= 0x0000003d,
96 SQ_CF_POS_2
= 0x0000003e,
97 SQ_CF_POS_3
= 0x0000003f,
98 } ENUM_SQ_CF_ARRAY_BASE_POS
;
102 PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit
= 23,
107 TEX_XYFilter_Point
= 0x00000000,
108 TEX_XYFilter_Linear
= 0x00000001,
109 TEX_XYFilter_Cubic
= 0x00000002,
110 TEX_XYFilter_Cleartype
= 0x00000003,
112 TEX_MipFilter_None
= 0x00000000,
113 TEX_MipFilter_Point
= 0x00000001,
114 TEX_MipFilter_Linear
= 0x00000002,
119 SQ_EXPORT_WRITE
= 0x00000000,
120 SQ_EXPORT_WRITE_IND
= 0x00000001,
121 SQ_EXPORT_WRITE_ACK
= 0x00000002,
122 SQ_EXPORT_WRITE_IND_ACK
= 0x00000003,
125 /* --------------------------------- */
129 R700_PM4_PACKET0_NOP
= 0x00000000,
130 R700_PM4_PACKET1_NOP
= 0x40000000,
131 R700_PM4_PACKET2_NOP
= 0x80000000,
132 R700_PM4_PACKET3_NOP
= 0xC0000000,
135 #define PM4_OPCODE_SET_INDEX_TYPE (R700_PM4_PACKET3_NOP | (IT_INDEX_TYPE << 8))
137 #define PM4_OPCODE_DRAW_INDEX_AUTO (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_AUTO << 8))
138 #define PM4_OPCODE_DRAW_INDEX_IMMD (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_IMMD << 8))
139 #define PM4_OPCODE_WAIT_REG_MEM (R700_PM4_PACKET3_NOP | (IT_WAIT_REG_MEM << 8))
140 #define PM4_OPCODE_SET_CONTEXT_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONTEXT_REG << 8))
141 #define PM4_OPCODE_SET_CONFIG_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONFIG_REG << 8))
142 #define PM4_OPCODE_SET_ALU_CONST (R700_PM4_PACKET3_NOP | (IT_SET_ALU_CONST << 8))
143 #define PM4_OPCODE_SET_RESOURCE (R700_PM4_PACKET3_NOP | (IT_SET_RESOURCE << 8))
144 #define PM4_OPCODE_SET_SAMPLER (R700_PM4_PACKET3_NOP | (IT_SET_SAMPLER << 8))
145 #define PM4_OPCODE_CONTEXT_CONTROL (R700_PM4_PACKET3_NOP | (IT_CONTEXT_CONTROL << 8))
154 typedef struct _TEXTURE_STATE_STRUCT
156 union UINT_FLOAT SQ_TEX_RESOURCE0
;
157 union UINT_FLOAT SQ_TEX_RESOURCE1
;
158 union UINT_FLOAT SQ_TEX_RESOURCE2
;
159 union UINT_FLOAT SQ_TEX_RESOURCE3
;
160 union UINT_FLOAT SQ_TEX_RESOURCE4
;
161 union UINT_FLOAT SQ_TEX_RESOURCE5
;
162 union UINT_FLOAT SQ_TEX_RESOURCE6
;
164 } TEXTURE_STATE_STRUCT
;
166 typedef struct _SAMPLER_STATE_STRUCT
168 union UINT_FLOAT SQ_TEX_SAMPLER0
;
169 union UINT_FLOAT SQ_TEX_SAMPLER1
;
170 union UINT_FLOAT SQ_TEX_SAMPLER2
;
172 } SAMPLER_STATE_STRUCT
;
174 typedef struct _R700_TEXTURE_STATES
176 TEXTURE_STATE_STRUCT
*textures
[R700_TEXTURE_NUMBERUNITS
];
177 SAMPLER_STATE_STRUCT
*samplers
[R700_TEXTURE_NUMBERUNITS
];
178 } R700_TEXTURE_STATES
;
181 typedef struct _RENDER_TARGET_STATE_STRUCT
183 union UINT_FLOAT CB_COLOR0_BASE
; /* 0xA010 */
184 union UINT_FLOAT CB_COLOR0_SIZE
; /* 0xA018 */
185 union UINT_FLOAT CB_COLOR0_VIEW
; /* 0xA020 */
186 union UINT_FLOAT CB_COLOR0_INFO
; /* 0xA028 */
187 union UINT_FLOAT CB_COLOR0_TILE
; /* 0xA030 */
188 union UINT_FLOAT CB_COLOR0_FRAG
; /* 0xA038 */
189 union UINT_FLOAT CB_COLOR0_MASK
; /* 0xA040 */
190 union UINT_FLOAT CB_BLEND0_CONTROL
; /* 0xA1E0 */
193 } RENDER_TARGET_STATE_STRUCT
;
195 typedef struct _VIEWPORT_STATE_STRUCT
197 union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL
; /* 0xA094 */
198 union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR
; /* 0xA095 */
199 union UINT_FLOAT PA_SC_VPORT_ZMIN_0
; /* 0xA0B4 */
200 union UINT_FLOAT PA_SC_VPORT_ZMAX_0
; /* 0xA0B5 */
201 union UINT_FLOAT PA_CL_VPORT_XSCALE
; /* 0xA10F */
202 union UINT_FLOAT PA_CL_VPORT_XOFFSET
; /* 0xA110 */
203 union UINT_FLOAT PA_CL_VPORT_YSCALE
; /* 0xA111 */
204 union UINT_FLOAT PA_CL_VPORT_YOFFSET
; /* 0xA112 */
205 union UINT_FLOAT PA_CL_VPORT_ZSCALE
; /* 0xA113 */
206 union UINT_FLOAT PA_CL_VPORT_ZOFFSET
; /* 0xA114 */
209 } VIEWPORT_STATE_STRUCT
;
211 typedef struct _UCP_STATE_STRUCT
213 union UINT_FLOAT PA_CL_UCP_0_X
;
214 union UINT_FLOAT PA_CL_UCP_0_Y
;
215 union UINT_FLOAT PA_CL_UCP_0_Z
;
216 union UINT_FLOAT PA_CL_UCP_0_W
;
221 typedef struct _PS_STATE_STRUCT
223 union UINT_FLOAT SQ_PGM_START_PS
; /* 0xA210 */
224 union UINT_FLOAT SQ_PGM_RESOURCES_PS
; /* 0xA214 */
225 union UINT_FLOAT SQ_PGM_EXPORTS_PS
; /* 0xA215 */
226 union UINT_FLOAT SQ_PGM_CF_OFFSET_PS
; /* 0xA233 */
229 union UINT_FLOAT consts
[R700_MAX_DX9_CONSTS
][4];
232 typedef struct _VS_STATE_STRUCT
234 union UINT_FLOAT SQ_PGM_START_VS
; /* 0xA216 */
235 union UINT_FLOAT SQ_PGM_RESOURCES_VS
; /* 0xA21A */
236 union UINT_FLOAT SQ_PGM_CF_OFFSET_VS
; /* 0xA234 */
239 union UINT_FLOAT consts
[R700_MAX_DX9_CONSTS
][4];
242 typedef struct _GS_STATE_STRUCT
244 union UINT_FLOAT SQ_PGM_START_GS
; /* 0xA21B */
245 union UINT_FLOAT SQ_PGM_RESOURCES_GS
; /* 0xA21F */
246 union UINT_FLOAT SQ_PGM_CF_OFFSET_GS
; /* 0xA235 */
250 typedef struct _ES_STATE_STRUCT
252 union UINT_FLOAT SQ_PGM_START_ES
; /* 0xA220 */
253 union UINT_FLOAT SQ_PGM_RESOURCES_ES
; /* 0xA224 */
254 union UINT_FLOAT SQ_PGM_CF_OFFSET_ES
; /* 0xA236 */
258 typedef struct _FS_STATE_STRUCT
260 union UINT_FLOAT SQ_PGM_START_FS
; /* 0xA225 */
261 union UINT_FLOAT SQ_PGM_RESOURCES_FS
; /* 0xA229 */
262 union UINT_FLOAT SQ_PGM_CF_OFFSET_FS
; /* 0xA237 */
266 typedef struct _SQ_CONFIG_STRUCT
268 union UINT_FLOAT SQ_CONFIG
; /* 0x2300 */
269 union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_1
; /* 0x2301 */
270 union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_2
; /* 0x2302 */
271 union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT
; /* 0x2303 */
272 union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_1
; /* 0x2304 */
273 union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2
; /* 0x2305 */
276 typedef struct _R700_CHIP_CONTEXT
279 union UINT_FLOAT DB_DEPTH_SIZE
; /* 0xA000 */
280 union UINT_FLOAT DB_DEPTH_VIEW
; /* 0xA001 */
281 union UINT_FLOAT DB_DEPTH_BASE
; /* 0xA003 */
282 union UINT_FLOAT DB_DEPTH_INFO
; /* 0xA004 */
283 GLboolean db_target_dirty
;
284 union UINT_FLOAT DB_HTILE_DATA_BASE
; /* 0xA005 */
285 union UINT_FLOAT DB_STENCIL_CLEAR
; /* 0xA00A */
286 union UINT_FLOAT DB_DEPTH_CLEAR
; /* 0xA00B */
287 union UINT_FLOAT DB_STENCILREFMASK
; /* 0xA10C */
288 union UINT_FLOAT DB_STENCILREFMASK_BF
; /* 0xA10D */
289 union UINT_FLOAT DB_RENDER_CONTROL
; /* 0xA343 */
290 union UINT_FLOAT DB_RENDER_OVERRIDE
; /* 0xA344 */
291 union UINT_FLOAT DB_HTILE_SURFACE
; /* 0xA349 */
292 union UINT_FLOAT DB_ALPHA_TO_MASK
; /* 0xA351 */
293 union UINT_FLOAT DB_DEPTH_CONTROL
; /* 0xA200 */
294 union UINT_FLOAT DB_SHADER_CONTROL
; /* 0xA203 */
298 union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL
; /* 0xA00C */
299 union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR
; /* 0xA00D */
300 union UINT_FLOAT PA_SC_WINDOW_OFFSET
; /* 0xA080 */
301 union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL
; /* 0xA081 */
302 union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR
; /* 0xA082 */
303 union UINT_FLOAT PA_SC_CLIPRECT_RULE
; /* 0xA083 */
304 union UINT_FLOAT PA_SC_CLIPRECT_0_TL
; /* 0xA084 */
305 union UINT_FLOAT PA_SC_CLIPRECT_0_BR
; /* 0xA085 */
306 union UINT_FLOAT PA_SC_CLIPRECT_1_TL
; /* 0xA086 */
307 union UINT_FLOAT PA_SC_CLIPRECT_1_BR
; /* 0xA087 */
308 union UINT_FLOAT PA_SC_CLIPRECT_2_TL
; /* 0xA088 */
309 union UINT_FLOAT PA_SC_CLIPRECT_2_BR
; /* 0xA089 */
310 union UINT_FLOAT PA_SC_CLIPRECT_3_TL
; /* 0xA08A */
311 union UINT_FLOAT PA_SC_CLIPRECT_3_BR
; /* 0xA08B */
312 union UINT_FLOAT PA_SC_EDGERULE
; /* 0xA08C */
313 union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL
; /* 0xA090 */
314 union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR
; /* 0xA091 */
315 GLboolean scissor_dirty
;
317 union UINT_FLOAT PA_SC_LINE_STIPPLE
; /* 0xA283 */
318 union UINT_FLOAT PA_SC_LINE_CNTL
; /* 0xA300 */
319 union UINT_FLOAT PA_SC_AA_CONFIG
; /* 0xA301 */
320 union UINT_FLOAT PA_SC_MPASS_PS_CNTL
; /* 0xA292 */
321 union UINT_FLOAT PA_SC_MODE_CNTL
; /* 0xA293 */
322 union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX
; /* 0xA307 */
323 union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
; /* 0xA308 */
324 union UINT_FLOAT PA_SC_AA_MASK
; /* 0xA312 */
328 union UINT_FLOAT PA_CL_CLIP_CNTL
; /* 0xA204 */
329 union UINT_FLOAT PA_CL_VTE_CNTL
; /* 0xA206 */
330 union UINT_FLOAT PA_CL_VS_OUT_CNTL
; /* 0xA207 */
331 union UINT_FLOAT PA_CL_NANINF_CNTL
; /* 0xA208 */
332 union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ
; /* 0xA303 */
333 union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ
; /* 0xA304 */
334 union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ
; /* 0xA305 */
335 union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ
; /* 0xA306 */
339 union UINT_FLOAT PA_SU_SC_MODE_CNTL
; /* 0xA205 */
340 union UINT_FLOAT PA_SU_POINT_SIZE
; /* 0xA280 */
341 union UINT_FLOAT PA_SU_POINT_MINMAX
; /* 0xA281 */
342 union UINT_FLOAT PA_SU_LINE_CNTL
; /* 0xA282 */
343 union UINT_FLOAT PA_SU_VTX_CNTL
; /* 0xA302 */
344 union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL
; /* 0xA37E */
345 union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP
; /* 0xA37F */
346 union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE
; /* 0xA380 */
347 union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET
; /* 0xA381 */
348 union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE
; /* 0xA382 */
349 union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET
; /* 0xA383 */
352 VIEWPORT_STATE_STRUCT viewport
[R700_MAX_VIEWPORTS
];
353 UCP_STATE_STRUCT ucp
[R700_MAX_UCP
];
356 union UINT_FLOAT CB_CLEAR_RED_R6XX
; /* 0xA048 */
357 union UINT_FLOAT CB_CLEAR_GREEN_R6XX
; /* 0xA049 */
358 union UINT_FLOAT CB_CLEAR_BLUE_R6XX
; /* 0xA04A */
359 union UINT_FLOAT CB_CLEAR_ALPHA_R6XX
; /* 0xA04B */
360 union UINT_FLOAT CB_TARGET_MASK
; /* 0xA08E */
361 union UINT_FLOAT CB_SHADER_MASK
; /* 0xA08F */
362 union UINT_FLOAT CB_BLEND_RED
; /* 0xA105 */
363 union UINT_FLOAT CB_BLEND_GREEN
; /* 0xA106 */
364 union UINT_FLOAT CB_BLEND_BLUE
; /* 0xA107 */
365 union UINT_FLOAT CB_BLEND_ALPHA
; /* 0xA108 */
366 union UINT_FLOAT CB_FOG_RED_R6XX
; /* 0xA109 */
367 union UINT_FLOAT CB_FOG_GREEN_R6XX
; /* 0xA10A */
368 union UINT_FLOAT CB_FOG_BLUE_R6XX
; /* 0xA10B */
369 union UINT_FLOAT CB_SHADER_CONTROL
; /* 0xA1E8 */
370 union UINT_FLOAT CB_COLOR_CONTROL
; /* 0xA202 */
371 union UINT_FLOAT CB_CLRCMP_CONTROL
; /* 0xA30C */
372 union UINT_FLOAT CB_CLRCMP_SRC
; /* 0xA30D */
373 union UINT_FLOAT CB_CLRCMP_DST
; /* 0xA30E */
374 union UINT_FLOAT CB_CLRCMP_MSK
; /* 0xA30F */
375 union UINT_FLOAT CB_BLEND_CONTROL
; /* 0xABD0 */
377 RENDER_TARGET_STATE_STRUCT render_target
[R700_MAX_RENDER_TARGETS
];
380 union UINT_FLOAT SX_MISC
; /* 0xA0D4 */
381 union UINT_FLOAT SX_ALPHA_TEST_CONTROL
; /* 0xA104 */
382 union UINT_FLOAT SX_ALPHA_REF
; /* 0xA10E */
386 union UINT_FLOAT VGT_MAX_VTX_INDX
; /* 0xA100 */
387 union UINT_FLOAT VGT_MIN_VTX_INDX
; /* 0xA101 */
388 union UINT_FLOAT VGT_INDX_OFFSET
; /* 0xA102 */
389 union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX
; /* 0xA103 */
390 union UINT_FLOAT VGT_OUTPUT_PATH_CNTL
; /* 0xA284 */
391 union UINT_FLOAT VGT_HOS_CNTL
; /* 0xA285 */
392 union UINT_FLOAT VGT_HOS_MAX_TESS_LEVEL
; /* 0xA286 */
393 union UINT_FLOAT VGT_HOS_MIN_TESS_LEVEL
; /* 0xA287 */
394 union UINT_FLOAT VGT_HOS_REUSE_DEPTH
; /* 0xA288 */
395 union UINT_FLOAT VGT_GROUP_PRIM_TYPE
; /* 0xA289 */
396 union UINT_FLOAT VGT_GROUP_FIRST_DECR
; /* 0xA28A */
397 union UINT_FLOAT VGT_GROUP_DECR
; /* 0xA28B */
398 union UINT_FLOAT VGT_GROUP_VECT_0_CNTL
; /* 0xA28C */
399 union UINT_FLOAT VGT_GROUP_VECT_1_CNTL
; /* 0xA28D */
400 union UINT_FLOAT VGT_GROUP_VECT_0_FMT_CNTL
; /* 0xA28E */
401 union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL
; /* 0xA28F */
402 union UINT_FLOAT VGT_GS_MODE
; /* 0xA290 */
403 union UINT_FLOAT VGT_PRIMITIVEID_EN
; /* 0xA2A1 */
404 union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN
; /* 0xA2A5 */
405 union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0
; /* 0xA2A8 */
406 union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1
; /* 0xA2A9 */
407 union UINT_FLOAT VGT_STRMOUT_EN
; /* 0xA2AC */
408 union UINT_FLOAT VGT_REUSE_OFF
; /* 0xA2AD */
409 union UINT_FLOAT VGT_VTX_CNT_EN
; /* 0xA2AE */
410 union UINT_FLOAT VGT_STRMOUT_BUFFER_EN
; /* 0xA2C8 */
414 union UINT_FLOAT SPI_VS_OUT_ID_0
; /* 0xA185 */
415 union UINT_FLOAT SPI_VS_OUT_ID_1
; /* 0xA186 */
416 union UINT_FLOAT SPI_VS_OUT_ID_2
; /* 0xA187 */
417 union UINT_FLOAT SPI_VS_OUT_ID_3
; /* 0xA188 */
418 union UINT_FLOAT SPI_VS_OUT_ID_4
; /* 0xA189 */
419 union UINT_FLOAT SPI_VS_OUT_ID_5
; /* 0xA18A */
420 union UINT_FLOAT SPI_VS_OUT_ID_6
; /* 0xA18B */
421 union UINT_FLOAT SPI_VS_OUT_ID_7
; /* 0xA18C */
422 union UINT_FLOAT SPI_VS_OUT_ID_8
; /* 0xA18D */
423 union UINT_FLOAT SPI_VS_OUT_ID_9
; /* 0xA18E */
424 union UINT_FLOAT SPI_VS_OUT_CONFIG
; /* 0xA1B1 */
425 union UINT_FLOAT SPI_THREAD_GROUPING
; /* 0xA1B2 */
426 union UINT_FLOAT SPI_PS_IN_CONTROL_0
; /* 0xA1B3 */
427 union UINT_FLOAT SPI_PS_IN_CONTROL_1
; /* 0xA1B4 */
428 union UINT_FLOAT SPI_INTERP_CONTROL_0
; /* 0xA1B5 */
429 union UINT_FLOAT SPI_INPUT_Z
; /* 0xA1B6 */
430 union UINT_FLOAT SPI_FOG_CNTL
; /* 0xA1B7 */
431 union UINT_FLOAT SPI_FOG_FUNC_SCALE
; /* 0xA1B8 */
432 union UINT_FLOAT SPI_FOG_FUNC_BIAS
; /* 0xA1B9 */
434 union UINT_FLOAT SQ_VTX_SEMANTIC_0
; /* 0xA0E0 */
435 union UINT_FLOAT SQ_VTX_SEMANTIC_1
; /* 0xA0E1 */
436 union UINT_FLOAT SQ_VTX_SEMANTIC_2
; /* 0xA0E2 */
437 union UINT_FLOAT SQ_VTX_SEMANTIC_3
; /* 0xA0E3 */
438 union UINT_FLOAT SQ_VTX_SEMANTIC_4
; /* 0xA0E4 */
439 union UINT_FLOAT SQ_VTX_SEMANTIC_5
; /* 0xA0E5 */
440 union UINT_FLOAT SQ_VTX_SEMANTIC_6
; /* 0xA0E6 */
441 union UINT_FLOAT SQ_VTX_SEMANTIC_7
; /* 0xA0E7 */
442 union UINT_FLOAT SQ_VTX_SEMANTIC_8
; /* 0xA0E8 */
443 union UINT_FLOAT SQ_VTX_SEMANTIC_9
; /* 0xA0E9 */
444 union UINT_FLOAT SQ_VTX_SEMANTIC_10
; /* 0xA0EA */
445 union UINT_FLOAT SQ_VTX_SEMANTIC_11
; /* 0xA0EB */
446 union UINT_FLOAT SQ_VTX_SEMANTIC_12
; /* 0xA0EC */
447 union UINT_FLOAT SQ_VTX_SEMANTIC_13
; /* 0xA0ED */
448 union UINT_FLOAT SQ_VTX_SEMANTIC_14
; /* 0xA0EE */
449 union UINT_FLOAT SQ_VTX_SEMANTIC_15
; /* 0xA0EF */
450 union UINT_FLOAT SQ_VTX_SEMANTIC_16
; /* 0xA0F0 */
451 union UINT_FLOAT SQ_VTX_SEMANTIC_17
; /* 0xA0F1 */
452 union UINT_FLOAT SQ_VTX_SEMANTIC_18
; /* 0xA0F2 */
453 union UINT_FLOAT SQ_VTX_SEMANTIC_19
; /* 0xA0F3 */
454 union UINT_FLOAT SQ_VTX_SEMANTIC_20
; /* 0xA0F4 */
455 union UINT_FLOAT SQ_VTX_SEMANTIC_21
; /* 0xA0F5 */
456 union UINT_FLOAT SQ_VTX_SEMANTIC_22
; /* 0xA0F6 */
457 union UINT_FLOAT SQ_VTX_SEMANTIC_23
; /* 0xA0F7 */
458 union UINT_FLOAT SQ_VTX_SEMANTIC_24
; /* 0xA0F8 */
459 union UINT_FLOAT SQ_VTX_SEMANTIC_25
; /* 0xA0F9 */
460 union UINT_FLOAT SQ_VTX_SEMANTIC_26
; /* 0xA0FA */
461 union UINT_FLOAT SQ_VTX_SEMANTIC_27
; /* 0xA0FB */
462 union UINT_FLOAT SQ_VTX_SEMANTIC_28
; /* 0xA0FC */
463 union UINT_FLOAT SQ_VTX_SEMANTIC_29
; /* 0xA0FD */
464 union UINT_FLOAT SQ_VTX_SEMANTIC_30
; /* 0xA0FE */
465 union UINT_FLOAT SQ_VTX_SEMANTIC_31
; /* 0xA0FF */
466 union UINT_FLOAT SPI_PS_INPUT_CNTL
[R700_MAX_SHADER_EXPORTS
];
477 SQ_CONFIG_STRUCT sq_config
;
479 union UINT_FLOAT TA_CNTL_AUX
; /* 0x2542 */
480 union UINT_FLOAT VC_ENHANCE
; /* 0x25C5 */
481 union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
; /* 0x2363 */
482 union UINT_FLOAT DB_DEBUG
; /* 0x260C */
483 union UINT_FLOAT DB_WATERMARKS
; /* 0x260E */
485 union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE
; /* 0xA22A */
486 union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE
; /* 0xA22B */
487 union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE
; /* 0xA22C */
488 union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE
; /* 0xA22D */
489 union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE
; /* 0xA22E */
490 union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE
; /* 0xA22F */
491 union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE
; /* 0xA230 */
492 union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE
; /* 0xA231 */
493 union UINT_FLOAT SQ_GS_VERT_ITEMSIZE
; /* 0xA232 */
496 radeonTexObj
* textures
[R700_TEXTURE_NUMBERUNITS
];
498 GLboolean bEnablePerspective
;
502 #endif /* _R700_CHIP_H_ */